blob: a23048417db57fff102510e790a33cfc55d9621d [file] [log] [blame]
Christophe Favergeonfeb73932020-05-20 14:48:06 +02001option(SEMIHOSTING "Test trace using printf" OFF)
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +02002
3if (PLATFORM STREQUAL "FVP")
Christophe Favergeonec574202019-08-09 06:54:05 +01004SET(PLATFORMFOLDER ${ROOT}/CMSIS/DSP/Platforms/FVP)
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +02005SET(PLATFORMID "FVP")
Christophe Favergeon3f7bbfb2020-05-06 07:10:29 +02006SET(PLATFORMOPT "-DFVP")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +02007list(APPEND CMAKE_MODULE_PATH ${ROOT}/CMSIS/DSP/Platforms/FVP)
8endif()
9
GorgonMeducerf8d8ec82019-11-05 14:09:36 +000010if (PLATFORM STREQUAL "MPS3")
11SET(PLATFORMFOLDER ${ROOT}/CMSIS/DSP/Platforms/MPS3)
12SET(PLATFORMID "MPS3")
13list(APPEND CMAKE_MODULE_PATH ${ROOT}/CMSIS/DSP/Platforms/MPS3)
14endif()
15
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020016if (PLATFORM STREQUAL "SDSIM")
Christophe Favergeonec574202019-08-09 06:54:05 +010017SET(PLATFORMFOLDER ${SDSIMROOT})
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020018SET(PLATFORMID "SDSIM")
Christophe Favergeonec574202019-08-09 06:54:05 +010019list(APPEND CMAKE_MODULE_PATH ${SDSIMROOT})
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020020endif()
21
Christophe Favergeon21bb6202020-04-30 09:07:33 +020022if (PLATFORM STREQUAL "IPSS")
23SET(PLATFORMFOLDER ${ROOT}/CMSIS/DSP/Platforms/IPSS)
24SET(PLATFORMID "IPSS")
25list(APPEND CMAKE_MODULE_PATH ${ROOT}/CMSIS/DSP/Platforms/IPSS)
26endif()
27
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020028SET(CORE ARMCM7)
29
Christophe Favergeon512b1482020-02-07 11:25:11 +010030
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020031include(platform)
32
33function(set_platform_core)
Christophe Favergeon26c2f682019-09-06 14:43:32 +010034
35 if(EXPERIMENTAL)
36 experimental_set_platform_core()
37 SET(CORE ${CORE} PARENT_SCOPE)
38 endif()
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020039 ###################
40 #
41 # Cortex cortex-m7
42 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020043 if (ARM_CPU MATCHES "^[cC]ortex-[mM]7([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020044 SET(CORE ARMCM7 PARENT_SCOPE)
45 endif()
46
47 ###################
48 #
49 # Cortex cortex-m4
50 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020051 if (ARM_CPU MATCHES "^[cC]ortex-[mM]4([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020052 SET(CORE ARMCM4 PARENT_SCOPE)
53 endif()
54
55 ###################
56 #
57 # Cortex cortex-m35p
58 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020059 if (ARM_CPU MATCHES "^[cC]ortex-[mM]35([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020060 SET(CORE ARMCM35P PARENT_SCOPE)
61
62 endif()
63
64 ###################
65 #
66 # Cortex cortex-m33
67 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020068 if (ARM_CPU MATCHES "^[cC]ortex-[mM]33([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020069 SET(CORE ARMCM33 PARENT_SCOPE)
70
71 endif()
Christophe Favergeon512b1482020-02-07 11:25:11 +010072
73 ###################
74 #
75 # Cortex cortex-m55
76 #
77 if (ARM_CPU MATCHES "^[cC]ortex-[mM]55([^0-9].*)?$")
78 SET(CORE ARMv81MML PARENT_SCOPE)
79 endif()
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020080
81 ###################
82 #
83 # Cortex cortex-m23
84 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020085 if (ARM_CPU MATCHES "^[cC]ortex-[mM]23([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020086 SET(CORE ARMCM23 PARENT_SCOPE)
87
88 endif()
89
90 ###################
91 #
92 # Cortex cortex-m0+
93 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020094 if (ARM_CPU MATCHES "^[cC]ortex-[mM]0p([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020095 SET(CORE ARMCM0plus PARENT_SCOPE)
96
97 endif()
98
99 ###################
100 #
101 # Cortex cortex-m0
102 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +0200103 if (ARM_CPU MATCHES "^[cC]ortex-[mM]0([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200104 SET(CORE ARMCM0 PARENT_SCOPE)
105
106 endif()
Christophe Favergeonc67252c2020-06-18 11:11:51 +0200107
108 ###################
109 #
110 # Cortex cortex-a32
111 #
112 if (ARM_CPU MATCHES "^[cC]ortex-[aA]32([^0-9].*)?$")
113 SET(CORE ARMCA32 PARENT_SCOPE)
114
115 endif()
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200116
117 ###################
118 #
119 # Cortex cortex-a5
120 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +0200121 if (ARM_CPU MATCHES "^[cC]ortex-[aA]5([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200122 SET(CORE ARMCA5 PARENT_SCOPE)
123
124 endif()
125
126 ###################
127 #
128 # Cortex cortex-a7
129 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +0200130 if (ARM_CPU MATCHES "^[cC]ortex-[aA]7([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200131 SET(CORE ARMCA7 PARENT_SCOPE)
132
133 endif()
134
135 ###################
136 #
137 # Cortex cortex-a9
138 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +0200139 if (ARM_CPU MATCHES "^[cC]ortex-[aA]9([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200140 SET(CORE ARMCA9 PARENT_SCOPE)
141
142 endif()
143
144 ###################
145 #
146 # Cortex cortex-a15
147 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +0200148 if (ARM_CPU MATCHES "^[cC]ortex-[aA]15([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200149 SET(CORE ARMCA15 PARENT_SCOPE)
150 endif()
Christophe Favergeon0e0449a2020-07-28 09:44:14 +0200151
152 ###################
153 #
154 # Cortex cortex-r5
155 #
156 if (ARM_CPU MATCHES "^[cC]ortex-[rR]5([^0-9].*)?$")
157 SET(CORE ARMCR5 PARENT_SCOPE)
158 endif()
159
160 ###################
161 #
162 # Cortex cortex-r8
163 #
164 if (ARM_CPU MATCHES "^[cC]ortex-[rR]8([^0-9].*)?$")
165 SET(CORE ARMCR8 PARENT_SCOPE)
166 endif()
Christophe Favergeonfe27d872020-07-31 07:20:18 +0200167
168 ###################
169 #
170 # Cortex cortex-r52
171 #
172 if (ARM_CPU MATCHES "^[cC]ortex-[rR]52([^0-9].*)?$")
173 SET(CORE ARMCR52 PARENT_SCOPE)
174 endif()
175
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200176endfunction()
177
178function(core_includes PROJECTNAME)
Christophe Favergeon0e0449a2020-07-28 09:44:14 +0200179 if (CORTEXR)
180 target_include_directories(${PROJECTNAME} PRIVATE ${CORER}/Include)
181 else()
182 target_include_directories(${PROJECTNAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/Include)
Christophe Favergeon7e532c72020-07-23 11:20:10 +0200183 #target_compile_options(${PROJECTNAME} PRIVATE ${PLATFORMOPT})
Christophe Favergeon0e0449a2020-07-28 09:44:14 +0200184 endif()
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200185endfunction()
186
187function (configplatformForLib PROJECTNAME ROOT)
188 if (SEMIHOSTING)
189 target_compile_definitions(${PROJECTNAME} PRIVATE SEMIHOSTING)
190 endif()
191 if (CORTEXM)
192 compilerSpecificPlatformConfigLibForM(${PROJECTNAME} ${ROOT} )
Christophe Favergeon0e0449a2020-07-28 09:44:14 +0200193 elseif(CORTEXA)
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200194 compilerSpecificPlatformConfigLibForA(${PROJECTNAME} ${ROOT} )
Christophe Favergeon0e0449a2020-07-28 09:44:14 +0200195 else()
196 compilerSpecificPlatformConfigLibForR(${PROJECTNAME} ${ROOT} )
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200197 endif()
198
199endfunction()
200
201function (configplatformForApp PROJECTNAME ROOT CORE PLATFORMFOLDER)
202 if (SEMIHOSTING)
203 target_compile_definitions(${PROJECTNAME} PRIVATE SEMIHOSTING)
204 endif()
205
206 configure_platform(${PROJECTNAME} ${ROOT} ${CORE} ${PLATFORMFOLDER})
207 SET(PLATFORMID ${PLATFORMID} PARENT_SCOPE)
208
209 if (CORTEXM)
210 compilerSpecificPlatformConfigAppForM(${PROJECTNAME} ${ROOT} )
Christophe Favergeon0e0449a2020-07-28 09:44:14 +0200211 elseif(CORTEXA)
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200212 compilerSpecificPlatformConfigAppForA(${PROJECTNAME} ${ROOT} )
Christophe Favergeon0e0449a2020-07-28 09:44:14 +0200213 else()
214 compilerSpecificPlatformConfigAppForR(${PROJECTNAME} ${ROOT} )
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200215 endif()
216
217endfunction()