Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 1 | option(SEMIHOSTING "Test trace using printf" ON) |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 2 | |
| 3 | if (PLATFORM STREQUAL "FVP") |
Christophe Favergeon | ec57420 | 2019-08-09 06:54:05 +0100 | [diff] [blame] | 4 | SET(PLATFORMFOLDER ${ROOT}/CMSIS/DSP/Platforms/FVP) |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 5 | SET(PLATFORMID "FVP") |
| 6 | list(APPEND CMAKE_MODULE_PATH ${ROOT}/CMSIS/DSP/Platforms/FVP) |
| 7 | endif() |
| 8 | |
GorgonMeducer | f8d8ec8 | 2019-11-05 14:09:36 +0000 | [diff] [blame] | 9 | if (PLATFORM STREQUAL "MPS3") |
| 10 | SET(PLATFORMFOLDER ${ROOT}/CMSIS/DSP/Platforms/MPS3) |
| 11 | SET(PLATFORMID "MPS3") |
| 12 | list(APPEND CMAKE_MODULE_PATH ${ROOT}/CMSIS/DSP/Platforms/MPS3) |
| 13 | endif() |
| 14 | |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 15 | if (PLATFORM STREQUAL "SDSIM") |
Christophe Favergeon | ec57420 | 2019-08-09 06:54:05 +0100 | [diff] [blame] | 16 | SET(PLATFORMFOLDER ${SDSIMROOT}) |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 17 | SET(PLATFORMID "SDSIM") |
Christophe Favergeon | ec57420 | 2019-08-09 06:54:05 +0100 | [diff] [blame] | 18 | list(APPEND CMAKE_MODULE_PATH ${SDSIMROOT}) |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 19 | endif() |
| 20 | |
Christophe Favergeon | 21bb620 | 2020-04-30 09:07:33 +0200 | [diff] [blame^] | 21 | if (PLATFORM STREQUAL "IPSS") |
| 22 | SET(PLATFORMFOLDER ${ROOT}/CMSIS/DSP/Platforms/IPSS) |
| 23 | SET(PLATFORMID "IPSS") |
| 24 | list(APPEND CMAKE_MODULE_PATH ${ROOT}/CMSIS/DSP/Platforms/IPSS) |
| 25 | endif() |
| 26 | |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 27 | SET(CORE ARMCM7) |
| 28 | |
Christophe Favergeon | 512b148 | 2020-02-07 11:25:11 +0100 | [diff] [blame] | 29 | |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 30 | include(platform) |
| 31 | |
| 32 | function(set_platform_core) |
Christophe Favergeon | 26c2f68 | 2019-09-06 14:43:32 +0100 | [diff] [blame] | 33 | |
| 34 | if(EXPERIMENTAL) |
| 35 | experimental_set_platform_core() |
| 36 | SET(CORE ${CORE} PARENT_SCOPE) |
| 37 | endif() |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 38 | ################### |
| 39 | # |
| 40 | # Cortex cortex-m7 |
| 41 | # |
Christophe Favergeon | c4c3480 | 2019-09-24 14:05:01 +0200 | [diff] [blame] | 42 | if (ARM_CPU MATCHES "^[cC]ortex-[mM]7([^0-9].*)?$") |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 43 | SET(CORE ARMCM7 PARENT_SCOPE) |
| 44 | endif() |
| 45 | |
| 46 | ################### |
| 47 | # |
| 48 | # Cortex cortex-m4 |
| 49 | # |
Christophe Favergeon | c4c3480 | 2019-09-24 14:05:01 +0200 | [diff] [blame] | 50 | if (ARM_CPU MATCHES "^[cC]ortex-[mM]4([^0-9].*)?$") |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 51 | SET(CORE ARMCM4 PARENT_SCOPE) |
| 52 | endif() |
| 53 | |
| 54 | ################### |
| 55 | # |
| 56 | # Cortex cortex-m35p |
| 57 | # |
Christophe Favergeon | c4c3480 | 2019-09-24 14:05:01 +0200 | [diff] [blame] | 58 | if (ARM_CPU MATCHES "^[cC]ortex-[mM]35([^0-9].*)?$") |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 59 | SET(CORE ARMCM35P PARENT_SCOPE) |
| 60 | |
| 61 | endif() |
| 62 | |
| 63 | ################### |
| 64 | # |
| 65 | # Cortex cortex-m33 |
| 66 | # |
Christophe Favergeon | c4c3480 | 2019-09-24 14:05:01 +0200 | [diff] [blame] | 67 | if (ARM_CPU MATCHES "^[cC]ortex-[mM]33([^0-9].*)?$") |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 68 | SET(CORE ARMCM33 PARENT_SCOPE) |
| 69 | |
| 70 | endif() |
Christophe Favergeon | 512b148 | 2020-02-07 11:25:11 +0100 | [diff] [blame] | 71 | |
| 72 | ################### |
| 73 | # |
| 74 | # Cortex cortex-m55 |
| 75 | # |
| 76 | if (ARM_CPU MATCHES "^[cC]ortex-[mM]55([^0-9].*)?$") |
| 77 | SET(CORE ARMv81MML PARENT_SCOPE) |
| 78 | endif() |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 79 | |
| 80 | ################### |
| 81 | # |
| 82 | # Cortex cortex-m23 |
| 83 | # |
Christophe Favergeon | c4c3480 | 2019-09-24 14:05:01 +0200 | [diff] [blame] | 84 | if (ARM_CPU MATCHES "^[cC]ortex-[mM]23([^0-9].*)?$") |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 85 | SET(CORE ARMCM23 PARENT_SCOPE) |
| 86 | |
| 87 | endif() |
| 88 | |
| 89 | ################### |
| 90 | # |
| 91 | # Cortex cortex-m0+ |
| 92 | # |
Christophe Favergeon | c4c3480 | 2019-09-24 14:05:01 +0200 | [diff] [blame] | 93 | if (ARM_CPU MATCHES "^[cC]ortex-[mM]0p([^0-9].*)?$") |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 94 | SET(CORE ARMCM0plus PARENT_SCOPE) |
| 95 | |
| 96 | endif() |
| 97 | |
| 98 | ################### |
| 99 | # |
| 100 | # Cortex cortex-m0 |
| 101 | # |
Christophe Favergeon | c4c3480 | 2019-09-24 14:05:01 +0200 | [diff] [blame] | 102 | if (ARM_CPU MATCHES "^[cC]ortex-[mM]0([^0-9].*)?$") |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 103 | SET(CORE ARMCM0 PARENT_SCOPE) |
| 104 | |
| 105 | endif() |
| 106 | |
| 107 | ################### |
| 108 | # |
| 109 | # Cortex cortex-a5 |
| 110 | # |
Christophe Favergeon | c4c3480 | 2019-09-24 14:05:01 +0200 | [diff] [blame] | 111 | if (ARM_CPU MATCHES "^[cC]ortex-[aA]5([^0-9].*)?$") |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 112 | SET(CORE ARMCA5 PARENT_SCOPE) |
| 113 | |
| 114 | endif() |
| 115 | |
| 116 | ################### |
| 117 | # |
| 118 | # Cortex cortex-a7 |
| 119 | # |
Christophe Favergeon | c4c3480 | 2019-09-24 14:05:01 +0200 | [diff] [blame] | 120 | if (ARM_CPU MATCHES "^[cC]ortex-[aA]7([^0-9].*)?$") |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 121 | SET(CORE ARMCA7 PARENT_SCOPE) |
| 122 | |
| 123 | endif() |
| 124 | |
| 125 | ################### |
| 126 | # |
| 127 | # Cortex cortex-a9 |
| 128 | # |
Christophe Favergeon | c4c3480 | 2019-09-24 14:05:01 +0200 | [diff] [blame] | 129 | if (ARM_CPU MATCHES "^[cC]ortex-[aA]9([^0-9].*)?$") |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 130 | SET(CORE ARMCA9 PARENT_SCOPE) |
| 131 | |
| 132 | endif() |
| 133 | |
| 134 | ################### |
| 135 | # |
| 136 | # Cortex cortex-a15 |
| 137 | # |
Christophe Favergeon | c4c3480 | 2019-09-24 14:05:01 +0200 | [diff] [blame] | 138 | if (ARM_CPU MATCHES "^[cC]ortex-[aA]15([^0-9].*)?$") |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 139 | SET(CORE ARMCA15 PARENT_SCOPE) |
| 140 | endif() |
| 141 | endfunction() |
| 142 | |
| 143 | function(core_includes PROJECTNAME) |
Christophe Favergeon | ec57420 | 2019-08-09 06:54:05 +0100 | [diff] [blame] | 144 | target_include_directories(${PROJECTNAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/Include) |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 145 | endfunction() |
| 146 | |
| 147 | function (configplatformForLib PROJECTNAME ROOT) |
| 148 | if (SEMIHOSTING) |
| 149 | target_compile_definitions(${PROJECTNAME} PRIVATE SEMIHOSTING) |
| 150 | endif() |
| 151 | if (CORTEXM) |
| 152 | compilerSpecificPlatformConfigLibForM(${PROJECTNAME} ${ROOT} ) |
| 153 | else() |
| 154 | compilerSpecificPlatformConfigLibForA(${PROJECTNAME} ${ROOT} ) |
| 155 | endif() |
| 156 | |
| 157 | endfunction() |
| 158 | |
| 159 | function (configplatformForApp PROJECTNAME ROOT CORE PLATFORMFOLDER) |
| 160 | if (SEMIHOSTING) |
| 161 | target_compile_definitions(${PROJECTNAME} PRIVATE SEMIHOSTING) |
| 162 | endif() |
| 163 | |
| 164 | configure_platform(${PROJECTNAME} ${ROOT} ${CORE} ${PLATFORMFOLDER}) |
| 165 | SET(PLATFORMID ${PLATFORMID} PARENT_SCOPE) |
| 166 | |
| 167 | if (CORTEXM) |
| 168 | compilerSpecificPlatformConfigAppForM(${PROJECTNAME} ${ROOT} ) |
| 169 | else() |
| 170 | compilerSpecificPlatformConfigAppForA(${PROJECTNAME} ${ROOT} ) |
| 171 | endif() |
| 172 | |
| 173 | endfunction() |