blob: 1b6514e7e378a16d8d68e7069c3a2f65a3907fb1 [file] [log] [blame]
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +02001option(SEMIHOSTING "Test trace using printf" ON)
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +02002
3if (PLATFORM STREQUAL "FVP")
Christophe Favergeonec574202019-08-09 06:54:05 +01004SET(PLATFORMFOLDER ${ROOT}/CMSIS/DSP/Platforms/FVP)
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +02005SET(PLATFORMID "FVP")
6list(APPEND CMAKE_MODULE_PATH ${ROOT}/CMSIS/DSP/Platforms/FVP)
7endif()
8
GorgonMeducerf8d8ec82019-11-05 14:09:36 +00009if (PLATFORM STREQUAL "MPS3")
10SET(PLATFORMFOLDER ${ROOT}/CMSIS/DSP/Platforms/MPS3)
11SET(PLATFORMID "MPS3")
12list(APPEND CMAKE_MODULE_PATH ${ROOT}/CMSIS/DSP/Platforms/MPS3)
13endif()
14
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020015if (PLATFORM STREQUAL "SDSIM")
Christophe Favergeonec574202019-08-09 06:54:05 +010016SET(PLATFORMFOLDER ${SDSIMROOT})
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020017SET(PLATFORMID "SDSIM")
Christophe Favergeonec574202019-08-09 06:54:05 +010018list(APPEND CMAKE_MODULE_PATH ${SDSIMROOT})
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020019endif()
20
Christophe Favergeon21bb6202020-04-30 09:07:33 +020021if (PLATFORM STREQUAL "IPSS")
22SET(PLATFORMFOLDER ${ROOT}/CMSIS/DSP/Platforms/IPSS)
23SET(PLATFORMID "IPSS")
24list(APPEND CMAKE_MODULE_PATH ${ROOT}/CMSIS/DSP/Platforms/IPSS)
25endif()
26
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020027SET(CORE ARMCM7)
28
Christophe Favergeon512b1482020-02-07 11:25:11 +010029
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020030include(platform)
31
32function(set_platform_core)
Christophe Favergeon26c2f682019-09-06 14:43:32 +010033
34 if(EXPERIMENTAL)
35 experimental_set_platform_core()
36 SET(CORE ${CORE} PARENT_SCOPE)
37 endif()
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020038 ###################
39 #
40 # Cortex cortex-m7
41 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020042 if (ARM_CPU MATCHES "^[cC]ortex-[mM]7([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020043 SET(CORE ARMCM7 PARENT_SCOPE)
44 endif()
45
46 ###################
47 #
48 # Cortex cortex-m4
49 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020050 if (ARM_CPU MATCHES "^[cC]ortex-[mM]4([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020051 SET(CORE ARMCM4 PARENT_SCOPE)
52 endif()
53
54 ###################
55 #
56 # Cortex cortex-m35p
57 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020058 if (ARM_CPU MATCHES "^[cC]ortex-[mM]35([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020059 SET(CORE ARMCM35P PARENT_SCOPE)
60
61 endif()
62
63 ###################
64 #
65 # Cortex cortex-m33
66 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020067 if (ARM_CPU MATCHES "^[cC]ortex-[mM]33([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020068 SET(CORE ARMCM33 PARENT_SCOPE)
69
70 endif()
Christophe Favergeon512b1482020-02-07 11:25:11 +010071
72 ###################
73 #
74 # Cortex cortex-m55
75 #
76 if (ARM_CPU MATCHES "^[cC]ortex-[mM]55([^0-9].*)?$")
77 SET(CORE ARMv81MML PARENT_SCOPE)
78 endif()
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020079
80 ###################
81 #
82 # Cortex cortex-m23
83 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020084 if (ARM_CPU MATCHES "^[cC]ortex-[mM]23([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020085 SET(CORE ARMCM23 PARENT_SCOPE)
86
87 endif()
88
89 ###################
90 #
91 # Cortex cortex-m0+
92 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020093 if (ARM_CPU MATCHES "^[cC]ortex-[mM]0p([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020094 SET(CORE ARMCM0plus PARENT_SCOPE)
95
96 endif()
97
98 ###################
99 #
100 # Cortex cortex-m0
101 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +0200102 if (ARM_CPU MATCHES "^[cC]ortex-[mM]0([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200103 SET(CORE ARMCM0 PARENT_SCOPE)
104
105 endif()
106
107 ###################
108 #
109 # Cortex cortex-a5
110 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +0200111 if (ARM_CPU MATCHES "^[cC]ortex-[aA]5([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200112 SET(CORE ARMCA5 PARENT_SCOPE)
113
114 endif()
115
116 ###################
117 #
118 # Cortex cortex-a7
119 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +0200120 if (ARM_CPU MATCHES "^[cC]ortex-[aA]7([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200121 SET(CORE ARMCA7 PARENT_SCOPE)
122
123 endif()
124
125 ###################
126 #
127 # Cortex cortex-a9
128 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +0200129 if (ARM_CPU MATCHES "^[cC]ortex-[aA]9([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200130 SET(CORE ARMCA9 PARENT_SCOPE)
131
132 endif()
133
134 ###################
135 #
136 # Cortex cortex-a15
137 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +0200138 if (ARM_CPU MATCHES "^[cC]ortex-[aA]15([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200139 SET(CORE ARMCA15 PARENT_SCOPE)
140 endif()
141endfunction()
142
143function(core_includes PROJECTNAME)
Christophe Favergeonec574202019-08-09 06:54:05 +0100144 target_include_directories(${PROJECTNAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/Include)
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200145endfunction()
146
147function (configplatformForLib PROJECTNAME ROOT)
148 if (SEMIHOSTING)
149 target_compile_definitions(${PROJECTNAME} PRIVATE SEMIHOSTING)
150 endif()
151 if (CORTEXM)
152 compilerSpecificPlatformConfigLibForM(${PROJECTNAME} ${ROOT} )
153 else()
154 compilerSpecificPlatformConfigLibForA(${PROJECTNAME} ${ROOT} )
155 endif()
156
157endfunction()
158
159function (configplatformForApp PROJECTNAME ROOT CORE PLATFORMFOLDER)
160 if (SEMIHOSTING)
161 target_compile_definitions(${PROJECTNAME} PRIVATE SEMIHOSTING)
162 endif()
163
164 configure_platform(${PROJECTNAME} ${ROOT} ${CORE} ${PLATFORMFOLDER})
165 SET(PLATFORMID ${PLATFORMID} PARENT_SCOPE)
166
167 if (CORTEXM)
168 compilerSpecificPlatformConfigAppForM(${PROJECTNAME} ${ROOT} )
169 else()
170 compilerSpecificPlatformConfigAppForA(${PROJECTNAME} ${ROOT} )
171 endif()
172
173endfunction()