blob: d6ca4e896ecc65a461741241a1b433639b3ec0a4 [file] [log] [blame]
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +02001option(SEMIHOSTING "Test trace using printf" ON)
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +02002
3if (PLATFORM STREQUAL "FVP")
Christophe Favergeonec574202019-08-09 06:54:05 +01004SET(PLATFORMFOLDER ${ROOT}/CMSIS/DSP/Platforms/FVP)
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +02005SET(PLATFORMID "FVP")
6list(APPEND CMAKE_MODULE_PATH ${ROOT}/CMSIS/DSP/Platforms/FVP)
7endif()
8
GorgonMeducerf8d8ec82019-11-05 14:09:36 +00009if (PLATFORM STREQUAL "MPS3")
10SET(PLATFORMFOLDER ${ROOT}/CMSIS/DSP/Platforms/MPS3)
11SET(PLATFORMID "MPS3")
12list(APPEND CMAKE_MODULE_PATH ${ROOT}/CMSIS/DSP/Platforms/MPS3)
13endif()
14
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020015if (PLATFORM STREQUAL "SDSIM")
Christophe Favergeonec574202019-08-09 06:54:05 +010016SET(PLATFORMFOLDER ${SDSIMROOT})
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020017SET(PLATFORMID "SDSIM")
Christophe Favergeonec574202019-08-09 06:54:05 +010018list(APPEND CMAKE_MODULE_PATH ${SDSIMROOT})
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020019endif()
20
21SET(CORE ARMCM7)
22
23include(platform)
24
25function(set_platform_core)
Christophe Favergeon26c2f682019-09-06 14:43:32 +010026
27 if(EXPERIMENTAL)
28 experimental_set_platform_core()
29 SET(CORE ${CORE} PARENT_SCOPE)
30 endif()
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020031 ###################
32 #
33 # Cortex cortex-m7
34 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020035 if (ARM_CPU MATCHES "^[cC]ortex-[mM]7([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020036 SET(CORE ARMCM7 PARENT_SCOPE)
37 endif()
38
39 ###################
40 #
41 # Cortex cortex-m4
42 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020043 if (ARM_CPU MATCHES "^[cC]ortex-[mM]4([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020044 SET(CORE ARMCM4 PARENT_SCOPE)
45 endif()
46
47 ###################
48 #
49 # Cortex cortex-m35p
50 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020051 if (ARM_CPU MATCHES "^[cC]ortex-[mM]35([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020052 SET(CORE ARMCM35P PARENT_SCOPE)
53
54 endif()
55
56 ###################
57 #
58 # Cortex cortex-m33
59 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020060 if (ARM_CPU MATCHES "^[cC]ortex-[mM]33([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020061 SET(CORE ARMCM33 PARENT_SCOPE)
62
63 endif()
64
65 ###################
66 #
67 # Cortex cortex-m23
68 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020069 if (ARM_CPU MATCHES "^[cC]ortex-[mM]23([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020070 SET(CORE ARMCM23 PARENT_SCOPE)
71
72 endif()
73
74 ###################
75 #
76 # Cortex cortex-m0+
77 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020078 if (ARM_CPU MATCHES "^[cC]ortex-[mM]0p([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020079 SET(CORE ARMCM0plus PARENT_SCOPE)
80
81 endif()
82
83 ###################
84 #
85 # Cortex cortex-m0
86 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020087 if (ARM_CPU MATCHES "^[cC]ortex-[mM]0([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020088 SET(CORE ARMCM0 PARENT_SCOPE)
89
90 endif()
91
92 ###################
93 #
94 # Cortex cortex-a5
95 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020096 if (ARM_CPU MATCHES "^[cC]ortex-[aA]5([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020097 SET(CORE ARMCA5 PARENT_SCOPE)
98
99 endif()
100
101 ###################
102 #
103 # Cortex cortex-a7
104 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +0200105 if (ARM_CPU MATCHES "^[cC]ortex-[aA]7([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200106 SET(CORE ARMCA7 PARENT_SCOPE)
107
108 endif()
109
110 ###################
111 #
112 # Cortex cortex-a9
113 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +0200114 if (ARM_CPU MATCHES "^[cC]ortex-[aA]9([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200115 SET(CORE ARMCA9 PARENT_SCOPE)
116
117 endif()
118
119 ###################
120 #
121 # Cortex cortex-a15
122 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +0200123 if (ARM_CPU MATCHES "^[cC]ortex-[aA]15([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200124 SET(CORE ARMCA15 PARENT_SCOPE)
125 endif()
126endfunction()
127
128function(core_includes PROJECTNAME)
Christophe Favergeonec574202019-08-09 06:54:05 +0100129 target_include_directories(${PROJECTNAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/Include)
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200130endfunction()
131
132function (configplatformForLib PROJECTNAME ROOT)
133 if (SEMIHOSTING)
134 target_compile_definitions(${PROJECTNAME} PRIVATE SEMIHOSTING)
135 endif()
136 if (CORTEXM)
137 compilerSpecificPlatformConfigLibForM(${PROJECTNAME} ${ROOT} )
138 else()
139 compilerSpecificPlatformConfigLibForA(${PROJECTNAME} ${ROOT} )
140 endif()
141
142endfunction()
143
144function (configplatformForApp PROJECTNAME ROOT CORE PLATFORMFOLDER)
145 if (SEMIHOSTING)
146 target_compile_definitions(${PROJECTNAME} PRIVATE SEMIHOSTING)
147 endif()
148
149 configure_platform(${PROJECTNAME} ${ROOT} ${CORE} ${PLATFORMFOLDER})
150 SET(PLATFORMID ${PLATFORMID} PARENT_SCOPE)
151
152 if (CORTEXM)
153 compilerSpecificPlatformConfigAppForM(${PROJECTNAME} ${ROOT} )
154 else()
155 compilerSpecificPlatformConfigAppForA(${PROJECTNAME} ${ROOT} )
156 endif()
157
158endfunction()