Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 1 | option(SEMIHOSTING "Test trace using printf" ON) |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 2 | |
| 3 | if (PLATFORM STREQUAL "FVP") |
Christophe Favergeon | ec57420 | 2019-08-09 06:54:05 +0100 | [diff] [blame] | 4 | SET(PLATFORMFOLDER ${ROOT}/CMSIS/DSP/Platforms/FVP) |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 5 | SET(PLATFORMID "FVP") |
| 6 | list(APPEND CMAKE_MODULE_PATH ${ROOT}/CMSIS/DSP/Platforms/FVP) |
| 7 | endif() |
| 8 | |
| 9 | if (PLATFORM STREQUAL "SDSIM") |
Christophe Favergeon | ec57420 | 2019-08-09 06:54:05 +0100 | [diff] [blame] | 10 | SET(PLATFORMFOLDER ${SDSIMROOT}) |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 11 | SET(PLATFORMID "SDSIM") |
Christophe Favergeon | ec57420 | 2019-08-09 06:54:05 +0100 | [diff] [blame] | 12 | list(APPEND CMAKE_MODULE_PATH ${SDSIMROOT}) |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 13 | endif() |
| 14 | |
| 15 | SET(CORE ARMCM7) |
| 16 | |
| 17 | include(platform) |
| 18 | |
| 19 | function(set_platform_core) |
Christophe Favergeon | 26c2f68 | 2019-09-06 14:43:32 +0100 | [diff] [blame] | 20 | |
| 21 | if(EXPERIMENTAL) |
| 22 | experimental_set_platform_core() |
| 23 | SET(CORE ${CORE} PARENT_SCOPE) |
| 24 | endif() |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 25 | ################### |
| 26 | # |
| 27 | # Cortex cortex-m7 |
| 28 | # |
Christophe Favergeon | c4c3480 | 2019-09-24 14:05:01 +0200 | [diff] [blame^] | 29 | if (ARM_CPU MATCHES "^[cC]ortex-[mM]7([^0-9].*)?$") |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 30 | SET(CORE ARMCM7 PARENT_SCOPE) |
| 31 | endif() |
| 32 | |
| 33 | ################### |
| 34 | # |
| 35 | # Cortex cortex-m4 |
| 36 | # |
Christophe Favergeon | c4c3480 | 2019-09-24 14:05:01 +0200 | [diff] [blame^] | 37 | if (ARM_CPU MATCHES "^[cC]ortex-[mM]4([^0-9].*)?$") |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 38 | SET(CORE ARMCM4 PARENT_SCOPE) |
| 39 | endif() |
| 40 | |
| 41 | ################### |
| 42 | # |
| 43 | # Cortex cortex-m35p |
| 44 | # |
Christophe Favergeon | c4c3480 | 2019-09-24 14:05:01 +0200 | [diff] [blame^] | 45 | if (ARM_CPU MATCHES "^[cC]ortex-[mM]35([^0-9].*)?$") |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 46 | SET(CORE ARMCM35P PARENT_SCOPE) |
| 47 | |
| 48 | endif() |
| 49 | |
| 50 | ################### |
| 51 | # |
| 52 | # Cortex cortex-m33 |
| 53 | # |
Christophe Favergeon | c4c3480 | 2019-09-24 14:05:01 +0200 | [diff] [blame^] | 54 | if (ARM_CPU MATCHES "^[cC]ortex-[mM]33([^0-9].*)?$") |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 55 | SET(CORE ARMCM33 PARENT_SCOPE) |
| 56 | |
| 57 | endif() |
| 58 | |
| 59 | ################### |
| 60 | # |
| 61 | # Cortex cortex-m23 |
| 62 | # |
Christophe Favergeon | c4c3480 | 2019-09-24 14:05:01 +0200 | [diff] [blame^] | 63 | if (ARM_CPU MATCHES "^[cC]ortex-[mM]23([^0-9].*)?$") |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 64 | SET(CORE ARMCM23 PARENT_SCOPE) |
| 65 | |
| 66 | endif() |
| 67 | |
| 68 | ################### |
| 69 | # |
| 70 | # Cortex cortex-m0+ |
| 71 | # |
Christophe Favergeon | c4c3480 | 2019-09-24 14:05:01 +0200 | [diff] [blame^] | 72 | if (ARM_CPU MATCHES "^[cC]ortex-[mM]0p([^0-9].*)?$") |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 73 | SET(CORE ARMCM0plus PARENT_SCOPE) |
| 74 | |
| 75 | endif() |
| 76 | |
| 77 | ################### |
| 78 | # |
| 79 | # Cortex cortex-m0 |
| 80 | # |
Christophe Favergeon | c4c3480 | 2019-09-24 14:05:01 +0200 | [diff] [blame^] | 81 | if (ARM_CPU MATCHES "^[cC]ortex-[mM]0([^0-9].*)?$") |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 82 | SET(CORE ARMCM0 PARENT_SCOPE) |
| 83 | |
| 84 | endif() |
| 85 | |
| 86 | ################### |
| 87 | # |
| 88 | # Cortex cortex-a5 |
| 89 | # |
Christophe Favergeon | c4c3480 | 2019-09-24 14:05:01 +0200 | [diff] [blame^] | 90 | if (ARM_CPU MATCHES "^[cC]ortex-[aA]5([^0-9].*)?$") |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 91 | SET(CORE ARMCA5 PARENT_SCOPE) |
| 92 | |
| 93 | endif() |
| 94 | |
| 95 | ################### |
| 96 | # |
| 97 | # Cortex cortex-a7 |
| 98 | # |
Christophe Favergeon | c4c3480 | 2019-09-24 14:05:01 +0200 | [diff] [blame^] | 99 | if (ARM_CPU MATCHES "^[cC]ortex-[aA]7([^0-9].*)?$") |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 100 | SET(CORE ARMCA7 PARENT_SCOPE) |
| 101 | |
| 102 | endif() |
| 103 | |
| 104 | ################### |
| 105 | # |
| 106 | # Cortex cortex-a9 |
| 107 | # |
Christophe Favergeon | c4c3480 | 2019-09-24 14:05:01 +0200 | [diff] [blame^] | 108 | if (ARM_CPU MATCHES "^[cC]ortex-[aA]9([^0-9].*)?$") |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 109 | SET(CORE ARMCA9 PARENT_SCOPE) |
| 110 | |
| 111 | endif() |
| 112 | |
| 113 | ################### |
| 114 | # |
| 115 | # Cortex cortex-a15 |
| 116 | # |
Christophe Favergeon | c4c3480 | 2019-09-24 14:05:01 +0200 | [diff] [blame^] | 117 | if (ARM_CPU MATCHES "^[cC]ortex-[aA]15([^0-9].*)?$") |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 118 | SET(CORE ARMCA15 PARENT_SCOPE) |
| 119 | endif() |
| 120 | endfunction() |
| 121 | |
| 122 | function(core_includes PROJECTNAME) |
Christophe Favergeon | ec57420 | 2019-08-09 06:54:05 +0100 | [diff] [blame] | 123 | target_include_directories(${PROJECTNAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/Include) |
Christophe Favergeon | 3b2a0ee | 2019-06-12 13:29:14 +0200 | [diff] [blame] | 124 | endfunction() |
| 125 | |
| 126 | function (configplatformForLib PROJECTNAME ROOT) |
| 127 | if (SEMIHOSTING) |
| 128 | target_compile_definitions(${PROJECTNAME} PRIVATE SEMIHOSTING) |
| 129 | endif() |
| 130 | if (CORTEXM) |
| 131 | compilerSpecificPlatformConfigLibForM(${PROJECTNAME} ${ROOT} ) |
| 132 | else() |
| 133 | compilerSpecificPlatformConfigLibForA(${PROJECTNAME} ${ROOT} ) |
| 134 | endif() |
| 135 | |
| 136 | endfunction() |
| 137 | |
| 138 | function (configplatformForApp PROJECTNAME ROOT CORE PLATFORMFOLDER) |
| 139 | if (SEMIHOSTING) |
| 140 | target_compile_definitions(${PROJECTNAME} PRIVATE SEMIHOSTING) |
| 141 | endif() |
| 142 | |
| 143 | configure_platform(${PROJECTNAME} ${ROOT} ${CORE} ${PLATFORMFOLDER}) |
| 144 | SET(PLATFORMID ${PLATFORMID} PARENT_SCOPE) |
| 145 | |
| 146 | if (CORTEXM) |
| 147 | compilerSpecificPlatformConfigAppForM(${PROJECTNAME} ${ROOT} ) |
| 148 | else() |
| 149 | compilerSpecificPlatformConfigAppForA(${PROJECTNAME} ${ROOT} ) |
| 150 | endif() |
| 151 | |
| 152 | endfunction() |