blob: bd306add60b9c46bbdf24ce8bbe9c600c8c95719 [file] [log] [blame]
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +02001option(SEMIHOSTING "Test trace using printf" ON)
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +02002
3if (PLATFORM STREQUAL "FVP")
Christophe Favergeonec574202019-08-09 06:54:05 +01004SET(PLATFORMFOLDER ${ROOT}/CMSIS/DSP/Platforms/FVP)
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +02005SET(PLATFORMID "FVP")
6list(APPEND CMAKE_MODULE_PATH ${ROOT}/CMSIS/DSP/Platforms/FVP)
7endif()
8
9if (PLATFORM STREQUAL "SDSIM")
Christophe Favergeonec574202019-08-09 06:54:05 +010010SET(PLATFORMFOLDER ${SDSIMROOT})
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020011SET(PLATFORMID "SDSIM")
Christophe Favergeonec574202019-08-09 06:54:05 +010012list(APPEND CMAKE_MODULE_PATH ${SDSIMROOT})
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020013endif()
14
15SET(CORE ARMCM7)
16
17include(platform)
18
19function(set_platform_core)
Christophe Favergeon26c2f682019-09-06 14:43:32 +010020
21 if(EXPERIMENTAL)
22 experimental_set_platform_core()
23 SET(CORE ${CORE} PARENT_SCOPE)
24 endif()
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020025 ###################
26 #
27 # Cortex cortex-m7
28 #
29 if (ARM_CPU STREQUAL "cortex-m7")
30 SET(CORE ARMCM7 PARENT_SCOPE)
31 endif()
32
33 ###################
34 #
35 # Cortex cortex-m4
36 #
37 if (ARM_CPU STREQUAL "cortex-m4")
38 SET(CORE ARMCM4 PARENT_SCOPE)
39 endif()
40
41 ###################
42 #
43 # Cortex cortex-m35p
44 #
45 if (ARM_CPU STREQUAL "cortex-m35")
46 SET(CORE ARMCM35P PARENT_SCOPE)
47
48 endif()
49
50 ###################
51 #
52 # Cortex cortex-m33
53 #
54 if (ARM_CPU STREQUAL "cortex-m33")
55 SET(CORE ARMCM33 PARENT_SCOPE)
56
57 endif()
58
59 ###################
60 #
61 # Cortex cortex-m23
62 #
63 if (ARM_CPU STREQUAL "cortex-m23")
64 SET(CORE ARMCM23 PARENT_SCOPE)
65
66 endif()
67
68 ###################
69 #
70 # Cortex cortex-m0+
71 #
72 if (ARM_CPU STREQUAL "cortex-m0p")
73 SET(CORE ARMCM0plus PARENT_SCOPE)
74
75 endif()
76
77 ###################
78 #
79 # Cortex cortex-m0
80 #
81 if (ARM_CPU STREQUAL "cortex-m0")
82 SET(CORE ARMCM0 PARENT_SCOPE)
83
84 endif()
85
86 ###################
87 #
88 # Cortex cortex-a5
89 #
90 if (ARM_CPU STREQUAL "cortex-a5")
91 SET(CORE ARMCA5 PARENT_SCOPE)
92
93 endif()
94
95 ###################
96 #
97 # Cortex cortex-a7
98 #
99 if (ARM_CPU STREQUAL "cortex-a7")
100 SET(CORE ARMCA7 PARENT_SCOPE)
101
102 endif()
103
104 ###################
105 #
106 # Cortex cortex-a9
107 #
108 if (ARM_CPU STREQUAL "cortex-a9")
109 SET(CORE ARMCA9 PARENT_SCOPE)
110
111 endif()
112
113 ###################
114 #
115 # Cortex cortex-a15
116 #
117 if (ARM_CPU STREQUAL "cortex-a15")
118 SET(CORE ARMCA15 PARENT_SCOPE)
119 endif()
120endfunction()
121
122function(core_includes PROJECTNAME)
Christophe Favergeonec574202019-08-09 06:54:05 +0100123 target_include_directories(${PROJECTNAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/Include)
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200124endfunction()
125
126function (configplatformForLib PROJECTNAME ROOT)
127 if (SEMIHOSTING)
128 target_compile_definitions(${PROJECTNAME} PRIVATE SEMIHOSTING)
129 endif()
130 if (CORTEXM)
131 compilerSpecificPlatformConfigLibForM(${PROJECTNAME} ${ROOT} )
132 else()
133 compilerSpecificPlatformConfigLibForA(${PROJECTNAME} ${ROOT} )
134 endif()
135
136endfunction()
137
138function (configplatformForApp PROJECTNAME ROOT CORE PLATFORMFOLDER)
139 if (SEMIHOSTING)
140 target_compile_definitions(${PROJECTNAME} PRIVATE SEMIHOSTING)
141 endif()
142
143 configure_platform(${PROJECTNAME} ${ROOT} ${CORE} ${PLATFORMFOLDER})
144 SET(PLATFORMID ${PLATFORMID} PARENT_SCOPE)
145
146 if (CORTEXM)
147 compilerSpecificPlatformConfigAppForM(${PROJECTNAME} ${ROOT} )
148 else()
149 compilerSpecificPlatformConfigAppForA(${PROJECTNAME} ${ROOT} )
150 endif()
151
152endfunction()