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Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -05001#!/usr/bin/env bash
Fathi Boudra422bf772019-12-02 11:10:16 +02002#
Rohit Mathew17675f22024-02-14 22:41:37 +00003# Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
Fathi Boudra422bf772019-12-02 11:10:16 +02004#
5# SPDX-License-Identifier: BSD-3-Clause
6#
7
8#
9# This script builds the TF in different configs.
10# Rather than telling cov-build to build TF using a simple 'make all' command,
11# the goal here is to combine several build flags to analyse more of our source
12# code in a single 'build'. The Coverity Scan service does not have the notion
13# of separate types of build - there is just one linear sequence of builds in
14# the project history.
15#
16
Harrison Mutaiee958c12023-09-06 12:16:21 +010017set -E
Harrison Mutai3f483132024-05-09 09:48:58 +000018error() {
19 rc=$?;
20 error_count=$((error_count+1));
21 echo "ERROR: signal $rc at ${1} ${2} (error_count = $error_count)"
22}
23trap 'error "${BASH_SOURCE}" "${LINENO}"' ERR INT
Fathi Boudra422bf772019-12-02 11:10:16 +020024
25TF_SOURCES=$1
26if [ ! -d "$TF_SOURCES" ]; then
27 echo "ERROR: '$TF_SOURCES' does not exist or is not a directory"
28 echo "Usage: $(basename "$0") <trusted-firmware-directory>"
29 exit 1
30fi
31
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050032containing_dir="$(readlink -f "$(dirname "$0")/")"
33. $containing_dir/common-def.sh
34
Fathi Boudra422bf772019-12-02 11:10:16 +020035# Get mbed TLS library code to build Trusted Firmware with Trusted Board Boot
36# support. The version of mbed TLS to use here must be the same as when
37# building TF in the usual context.
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050038if [ ! -d "$MBED_TLS_DIR" ]; then
39 git clone -q --depth 1 -b "$MBED_TLS_SOURCES_TAG" "$MBED_TLS_URL_REPO" "$MBED_TLS_DIR"
Fathi Boudra422bf772019-12-02 11:10:16 +020040fi
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050041
David Vincze82db6932024-02-21 12:05:50 +010042if [ ! -d "$QCBOR_LIB_DIR" ]; then
43 git clone "$QCBOR_URL_REPO" "$QCBOR_LIB_DIR"
44 cd "$QCBOR_LIB_DIR"
45 git checkout v1.2
46fi
47
Fathi Boudra422bf772019-12-02 11:10:16 +020048cd "$TF_SOURCES"
49
50# Clean TF source dir to make sure we don't analyse temporary files.
51make distclean
52
53#
54# Build TF in different configurations to get as much coverage as possible
55#
56
Fathi Boudra422bf772019-12-02 11:10:16 +020057#
58# FVP platform
59# We'll use the following flags for all FVP builds.
60#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050061fvp_common_flags="$(common_flags) PLAT=fvp"
Fathi Boudra422bf772019-12-02 11:10:16 +020062
63# Try all possible SPDs.
Chris Kayab29d432023-08-10 13:06:18 +000064clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram \
65 SPD=tspd FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +020066clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd TSP_INIT_ASYNC=1 \
Sona Mathew40e5be92023-08-10 16:31:45 -050067 TSP_NS_INTR_ASYNC_PREEMPT=1 FVP_TRUSTED_SRAM_SIZE=384
Manish V Badarkhe48ed0bf2023-06-28 09:33:16 +010068clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed FVP_TRUSTED_SRAM_SIZE=384
Elizabeth Ho1a04df12023-07-27 16:06:24 +010069clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tlkd FVP_TRUSTED_SRAM_SIZE=384
Manish V Badarkhee7528ff2023-07-01 10:20:05 +010070clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=pncd SPD_PNCD_NS_IRQ=126 \
71 SPD_PNCD_S_IRQ=15 FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +020072
Zelalemc9531f82020-08-04 15:37:08 -050073# Dualroot chain of trust.
Harrison Mutai0dd5f532024-03-15 13:42:40 +000074clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tspd COT=dualroot \
75 FVP_TRUSTED_SRAM_SIZE=384
Zelalemc9531f82020-08-04 15:37:08 -050076
laurenw-armf48e9d22022-04-22 11:30:13 -050077# FEAT_RME with CCA chain of trust.
Manish V Badarkhe5304aaf2023-08-18 14:38:20 +010078clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} USE_ROMLIB=1 \
Manish V Badarkhed5e9c752023-11-07 17:57:36 +000079 ENABLE_RME=1 MEASURED_BOOT=1
laurenw-armf48e9d22022-04-22 11:30:13 -050080
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050081clean_build $fvp_common_flags SPD=trusty
82clean_build $fvp_common_flags SPD=trusty TRUSTY_SPD_WITH_GENERIC_SERVICES=1
Fathi Boudra422bf772019-12-02 11:10:16 +020083
Sona Mathewff9c2a72023-05-10 21:18:01 -050084# ERRATA ABI
85clean_build $fvp_common_flags ERRATA_ABI_SUPPORT=1
86
Fathi Boudra422bf772019-12-02 11:10:16 +020087# SDEI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050088clean_build $fvp_common_flags SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Fathi Boudra422bf772019-12-02 11:10:16 +020089
Zelalemc9531f82020-08-04 15:37:08 -050090# SDEI with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050091clean_build $fvp_common_flags SDEI_IN_FCONF=1 SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Zelalemc9531f82020-08-04 15:37:08 -050092
Zelalem4f3633e2021-06-18 11:53:47 -050093# PCI Service
94clean_build $fvp_common_flags SMC_PCI_SUPPORT=1
95
Zelalemc9531f82020-08-04 15:37:08 -050096# Secure interrupt descriptors with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050097clean_build $fvp_common_flags SEC_INT_DESC_IN_FCONF=1
Zelalemc9531f82020-08-04 15:37:08 -050098
Fathi Boudra422bf772019-12-02 11:10:16 +020099# Without coherent memory
Sona Mathewa06f62d2023-08-24 16:34:13 -0500100clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd \
101 USE_COHERENT_MEM=0 FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +0200102
103# Using PSCI extended State ID format rather than the original format
Sona Mathewa06f62d2023-08-24 16:34:13 -0500104clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd \
105 PSCI_EXTENDED_STATE_ID=1 ARM_RECOM_STATE_ID_ENC=1 FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +0200106
107# Alternative boot flows (This changes some of the platform initialisation code)
Elizabeth Ho4cdb2f42023-07-11 12:27:14 +0100108clean_build $fvp_common_flags EL3_PAYLOAD_BASE=0x80000000
Fathi Boudra422bf772019-12-02 11:10:16 +0200109clean_build $fvp_common_flags PRELOADED_BL33_BASE=0x80000000
110
111# Using the SP804 timer instead of the Generic Timer
112clean_build $fvp_common_flags FVP_USE_SP804_TIMER=1
113
114# Using the CCN driver and multi cluster topology
115clean_build $fvp_common_flags FVP_CLUSTER_COUNT=4
116
117# PMF
118clean_build $fvp_common_flags ENABLE_PMF=1
119
120# stack protector
121clean_build $fvp_common_flags ENABLE_STACK_PROTECTOR=strong
122
123# AArch32 build
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500124clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200125 ARCH=aarch32 AARCH32_SP=sp_min \
126 RESET_TO_SP_MIN=1 PRELOADED_BL33_BASE=0x80000000
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500127clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200128 ARCH=aarch32 AARCH32_SP=sp_min
129
130# Xlat tables lib version 1 (AArch64 and AArch32)
131clean_build $fvp_common_flags ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500132clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200133 ARCH=aarch32 AARCH32_SP=sp_min ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
134
Zelalemc9531f82020-08-04 15:37:08 -0500135# SPM support based on Management Mode Interface Specification
Manish Pandeyaa9a03b2021-11-17 10:03:17 +0000136clean_build $fvp_common_flags SPM_MM=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0
Fathi Boudra422bf772019-12-02 11:10:16 +0200137
Zelalemc9531f82020-08-04 15:37:08 -0500138# SPM support with TOS(optee) as SPM sitting at S-EL1
139clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0
140
Shruti Gupta8cc89b92022-08-09 12:23:46 +0100141# SPM support with SPM at EL3 and TSP at S-EL1
142clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 CTX_INCLUDE_EL2_REGS=0 EL3_EXCEPTION_HANDLING=0 \
143 SPD=spmd SPMD_SPM_AT_SEL2=0 SPMC_AT_EL3=1 \
144 ARM_SPMC_MANIFEST_DTS=plat/arm/board/fvp/fdts/fvp_tsp_sp_manifest.dts
145
Zelalemc9531f82020-08-04 15:37:08 -0500146# SPM support with Secure hafnium as SPM sitting at S-EL2
147# SP_LAYOUT_FILE is used only during FIP creation but build won't progress
148# if we have NULL value to it, so passing a dummy string.
149clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=1 ARM_ARCH_MINOR=4 \
Max Shvetsov44d2a702021-02-18 16:41:45 +0000150 CTX_INCLUDE_EL2_REGS=1 SP_LAYOUT_FILE=dummy
Fathi Boudra422bf772019-12-02 11:10:16 +0200151
J-Alves85ba07b2023-07-12 14:37:45 +0100152# SPM support with logical partitions in the SPMD.
153clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=1 ARM_ARCH_MINOR=4 \
154 CTX_INCLUDE_EL2_REGS=1 SP_LAYOUT_FILE=dummy ENABLE_SPMD_LP=1
155
Marc Bonnici502fdaa2022-01-10 12:38:23 +0000156# SPM support with SPM sitting at EL3
157clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0 SPMC_AT_EL3=1
158
Harrison Mutaib352c0e2023-08-11 18:27:57 +0100159# Firmware Handoff framework support
160clean_build $fvp_common_flags TRANSFER_LIST=1
161
Fathi Boudra422bf772019-12-02 11:10:16 +0200162#BL2 at EL3 support
Harrison Mutaic3c8cfc2023-09-05 12:03:03 +0100163clean_build $fvp_common_flags RESET_TO_BL2=1 FVP_TRUSTED_SRAM_SIZE=384
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500164clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Maksims Svecovs7a0da522023-03-06 16:28:27 +0000165 ARCH=aarch32 AARCH32_SP=sp_min RESET_TO_BL2=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200166
Zelalemc9531f82020-08-04 15:37:08 -0500167# RAS Extension Support
Manish Pandeyc1fa25b2023-02-16 17:35:36 +0000168clean_build $fvp_common_flags EL3_EXCEPTION_HANDLING=1 ENABLE_FEAT_RAS=1 \
Manish Pandeyf3816802023-10-11 17:13:58 +0100169 FAULT_INJECTION_SUPPORT=1 HANDLE_EA_EL3_FIRST_NS=1 \
Manish Pandey010e9b42023-04-24 15:49:27 +0100170 SDEI_SUPPORT=1 PLATFORM_TEST_RAS_FFH=1
Zelalemc9531f82020-08-04 15:37:08 -0500171
Manish Pandeyfd4c6b72023-04-24 10:29:52 +0100172# EA handled in EL3 first
173clean_build $fvp_common_flags HANDLE_EA_EL3_FIRST_NS=1 PLATFORM_TEST_EA_FFH=1
174
Zelalemc9531f82020-08-04 15:37:08 -0500175# Hardware Assisted Coherency(DynamIQ)
176clean_build $fvp_common_flags FVP_CLUSTER_COUNT=1 FVP_MAX_CPUS_PER_CLUSTER=8 \
177 HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0
178
179# Pointer Authentication Support
180clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 \
Sona Mathewa06f62d2023-08-24 16:34:13 -0500181 ARM_ARCH_MINOR=5 EL3_EXCEPTION_HANDLING=1 BRANCH_PROTECTION=1 SDEI_SUPPORT=1 SPD=tspd \
Sona Mathew08c17962023-08-28 09:36:17 -0500182 TSP_NS_INTR_ASYNC_PREEMPT=1 FVP_TRUSTED_SRAM_SIZE=384
Zelalemc9531f82020-08-04 15:37:08 -0500183
184# Undefined Behaviour Sanitizer
185# Building with UBSAN SANITIZE_UB=on increases the executable size.
186# Hence it is only properly supported in bl31 with RESET_TO_BL31 enabled
187make $fvp_common_flags clean
Manish V Badarkhe4e79cab2023-09-07 10:07:58 +0100188make $fvp_common_flags SANITIZE_UB=on RESET_TO_BL31=1 FVP_TRUSTED_SRAM_SIZE=384 bl31
Zelalemc9531f82020-08-04 15:37:08 -0500189
190# debugfs feature
191clean_build $fvp_common_flags DEBUG=1 USE_DEBUGFS=1
192
193# MPAM feature
Arvind Ram Prakashbd4e43a2023-10-02 11:12:34 -0500194clean_build $fvp_common_flags ENABLE_FEAT_MPAM=1
Zelalemc9531f82020-08-04 15:37:08 -0500195
Arvind Ram Prakashd2e27e62024-06-17 14:28:12 -0500196# Debugv8p9 feature
197clean_build $fvp_common_flags ENABLE_FEAT_DEBUGV8P9=1
198
Zelalemc9531f82020-08-04 15:37:08 -0500199# Using GICv3.1 driver with extended PPI and SPI range
200clean_build $fvp_common_flags GIC_EXT_INTID=1
201
202# Using GICv4 features with extended PPI and SPI range
203clean_build $fvp_common_flags GIC_ENABLE_V4_EXTN=1 GIC_EXT_INTID=1
204
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100205# Measured Boot
laurenw-arm8531e702022-06-09 15:32:37 -0500206clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} MBOOT_EL_HASH_ALG=sha256 MEASURED_BOOT=1 USE_ROMLIB=1
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100207
Manish V Badarkhef43e3f52022-06-21 20:37:25 +0100208# DRTM
209clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} TPM_HASH_ALG=sha256 DRTM_SUPPORT=1 USE_ROMLIB=1
210
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100211# CoT descriptors in device tree
laurenw-arm23b77592024-06-07 15:54:30 -0500212# TBBR chain of trust
Manish V Badarkhe81102d12020-10-05 08:02:30 +0100213clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} COT_DESC_IN_DTB=1 USE_ROMLIB=1
laurenw-arm23b77592024-06-07 15:54:30 -0500214# Dualroot chain of trust
215clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} COT_DESC_IN_DTB=1 COT=dualroot FVP_TRUSTED_SRAM_SIZE=384 SPD=tspd
216# CCA chain of trust
217clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} COT_DESC_IN_DTB=1 COT=cca FVP_TRUSTED_SRAM_SIZE=384
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100218
Chris Kayf4789fe2023-06-12 15:52:28 +0100219# PSA FWU support
220clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_GPT_SUPPORT=1 PSA_FWU_SUPPORT=1 USE_ROMLIB=1 FVP_TRUSTED_SRAM_SIZE=384
Manish V Badarkhe107c8e32021-08-02 19:49:32 +0100221
Manish V Badarkhe92616ae2023-09-18 10:06:00 +0100222# PSA Crypto support
223clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} PSA_CRYPTO=1 FVP_TRUSTED_SRAM_SIZE=384
224
johpow01153c8b22021-11-03 14:38:36 -0500225# SME and HCX features
226clean_build $fvp_common_flags ENABLE_SME_FOR_NS=1 ENABLE_FEAT_HCX=1
227
Jayanth Dodderi Chidanand41edd012023-01-12 14:50:34 +0000228# SME2
229clean_build $fvp_common_flags ENABLE_SME2_FOR_NS=1 ENABLE_SME_FOR_NS=1 ENABLE_FEAT_HCX=1
230
Jayanth Dodderi Chidanand84da1962022-04-11 11:38:44 +0100231# Architectural Feature Detection mechanism
232clean_build $fvp_common_flags FEATURE_DETECTION=1
233
Manish Pandeye3561fd2023-01-05 10:46:25 +0000234# RNG trap feature
235clean_build $fvp_common_flags ENABLE_FEAT_RNG=1 ENABLE_FEAT_RNG_TRAP=1
236
Yi Choua765ae42023-05-26 15:51:02 +0800237# OPTEE_ALLOW_SMC_LOAD and CROS_WIDEVINE_SMC features
238clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed OPTEE_ALLOW_SMC_LOAD=1 CROS_WIDEVINE_SMC=1 PLAT_XLAT_TABLES_DYNAMIC=1 FVP_TRUSTED_SRAM_SIZE=384
Jeffrey Kardatzke09e18e22023-01-25 12:24:13 -0800239
Jayanth Dodderi Chidanand508936d2023-12-22 14:33:38 +0000240# Report Context_Memory
241clean_build $fvp_common_flags PLATFORM_REPORT_CTX_MEM_USE=1
242
Govindraj Rajaef67db82024-05-02 09:57:13 -0500243# Build newer CPU's with no model available yet.
244clean_build $fvp_common_flags CTX_INCLUDE_AARCH32_REGS=0 HW_ASSISTED_COHERENCY=1 \
245 USE_COHERENT_MEM=0 BUILD_CPUS_WITH_NO_FVP_MODEL=1 FVP_TRUSTED_SRAM_SIZE=384
246
Fathi Boudra422bf772019-12-02 11:10:16 +0200247#
248# Juno platform
249# We'll use the following flags for all Juno builds.
250#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500251juno_common_flags="$(common_flags) PLAT=juno"
Fathi Boudra422bf772019-12-02 11:10:16 +0200252clean_build $juno_common_flags SPD=tspd ${ARM_TBB_OPTIONS}
Elizabeth Ho4cdb2f42023-07-11 12:27:14 +0100253clean_build $juno_common_flags EL3_PAYLOAD_BASE=0x80000000
Manish V Badarkhe05626442023-09-12 09:54:50 +0100254clean_build $juno_common_flags ENABLE_STACK_PROTECTOR=strong ETHOSN_NPU_DRIVER=1
Harrison Mutaid8aff2a2024-05-08 10:40:21 +0000255# FIXME: temporarily disable debug builds for this configuration until BL2 size
256# issues are resolved.
Harrison Mutaic70ba542024-05-09 13:17:12 +0000257clean_build "$(common_flags release) PLAT=juno" ${ARM_TBB_OPTIONS} \
Harrison Mutaid8aff2a2024-05-08 10:40:21 +0000258 ENABLE_STACK_PROTECTOR=strong ETHOSN_NPU_DRIVER=1 ETHOSN_NPU_TZMP1=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200259clean_build $juno_common_flags CSS_USE_SCMI_SDS_DRIVER=0
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500260
Jayanth Dodderi Chidanand055394a2022-10-19 09:20:20 +0100261# TRNG Service
262clean_build $juno_common_flags TRNG_SUPPORT=1
263
Fathi Boudra422bf772019-12-02 11:10:16 +0200264#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530265# Reference Design platform RD-V1
Zelalemc9531f82020-08-04 15:37:08 -0500266#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530267make $(common_flags) PLAT=rdv1 ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500268
269#
Aditya Angadi61c54762021-01-04 09:30:52 +0530270# Reference Design platform RD-V1-MC
Zelalemc9531f82020-08-04 15:37:08 -0500271#
Rohit Mathew17675f22024-02-14 22:41:37 +0000272make $(common_flags) PLAT=rdv1mc ${ARM_TBB_OPTIONS} NRD_CHIP_COUNT=4 all
Zelalemc9531f82020-08-04 15:37:08 -0500273
274#
Vijayenthiran Subramaniama66de332020-11-23 14:20:14 +0530275# Reference Design Platform RD-N2
276#
277make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} all
Omkar Anand Kulkarnif6e268e2023-06-21 20:32:22 +0530278# RAS Extension Support
279make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} ENABLE_FEAT_RAS=1 \
Manish Pandeyf3816802023-10-11 17:13:58 +0100280 HANDLE_EA_EL3_FIRST_NS=1 SDEI_SUPPORT=1 SPM_MM=1 all
281
Nishant Sharmabd7092e2023-10-11 09:17:13 +0100282# SPMC At EL3 Support
283make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} SPMC_AT_EL3=1 SPD=spmd \
284 SPMD_SPM_AT_SEL2=0 BL32=1 SPMC_AT_EL3_SEL0_SP=1 EL3_EXCEPTION_HANDLING=1 \
285 PLAT_RO_XLAT_TABLES=1 all
Vijayenthiran Subramaniama66de332020-11-23 14:20:14 +0530286
287#
Jerry Wang700472b2024-07-12 11:36:42 +0100288# Reference Design Platform RD-V3
Nuno Lopesd791e272024-04-25 14:46:49 +0100289#
Jerry Wang700472b2024-07-12 11:36:42 +0100290make $(common_flags) PLAT=rdv3 ${ARM_TBB_OPTIONS} COT=cca DEBUG=1 \
Nuno Lopesd791e272024-04-25 14:46:49 +0100291 ENABLE_RME=1 MEASURED_BOOT=1 PLAT_MHU_VERSION=3 RMM=/dev/null \
292 RME_GPT_BITLOCK_BLOCK=0 all
293
294#
Zelalemc9531f82020-08-04 15:37:08 -0500295# Neoverse N1 SDP platform
296#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500297make $(common_flags) PLAT=n1sdp ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500298
299#
300# FVP VE platform
301#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500302make $(common_flags) PLAT=fvp_ve AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500303 CROSS_COMPILE=arm-none-eabi- ARM_ARCH_MAJOR=7 \
304 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
305 FVP_HW_CONFIG_DTS=fdts/fvp-ve-Cortex-A5x1.dts all
306
307#
308# A5 DesignStart Platform
309#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500310make $(common_flags) PLAT=a5ds AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500311 ARM_ARCH_MAJOR=7 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
312 CROSS_COMPILE=arm-none-eabi- FVP_HW_CONFIG_DTS=fdts/a5ds.dts
313
314#
315# Corstone700 Platform
316#
317
318corstone700_common_flags="CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500319 $(common_flags) \
Zelalemc9531f82020-08-04 15:37:08 -0500320 PLAT=corstone700 \
321 ARCH=aarch32 \
322 RESET_TO_SP_MIN=1 \
323 AARCH32_SP=sp_min \
324 ARM_LINUX_KERNEL_AS_BL33=0 \
325 ARM_PRELOADED_DTB_BASE=0x80400000 \
326 ENABLE_PIE=1 \
Zelalemc9531f82020-08-04 15:37:08 -0500327 ENABLE_STACK_PROTECTOR=all \
328 all"
329
330echo "Info: Building Corstone700 FVP ..."
331
332make TARGET_PLATFORM=fvp ${corstone700_common_flags}
333
334echo "Info: Building Corstone700 FPGA ..."
335
336make TARGET_PLATFORM=fpga ${corstone700_common_flags}
337
338#
339# Arm internal FPGA port
340#
Andre Przywara13361b62022-04-26 11:16:55 +0100341make PLAT=arm_fpga $(common_flags release) \
342 FPGA_PRELOADED_DTB_BASE=0x88000000 PRELOADED_BL33_BASE=0x82080000 all
Zelalemc9531f82020-08-04 15:37:08 -0500343
344#
Usama Arifcba711d2021-08-04 15:53:42 +0100345# Total Compute platforms
Zelalemc9531f82020-08-04 15:37:08 -0500346#
Joel Goddard571a93c2024-02-29 15:31:48 +0000347clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} MEASURED_BOOT=1 \
348 PLAT_MHU_VERSION=3
David Vincze82db6932024-02-21 12:05:50 +0100349clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} MEASURED_BOOT=1 \
350 DICE_PROTECTION_ENVIRONMENT=1 QCBOR_DIR=$(pwd)/qcbor
David Vinczed8ed5622024-02-23 17:00:12 +0100351clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} PLATFORM_TEST=rse-nv-counters
Manish V Badarkhe58a88f02023-11-06 21:42:11 +0000352clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} PLATFORM_TEST=tfm-testsuite \
Manish V Badarkhe8f3a3fa2024-03-13 11:37:46 +0000353 MEASURED_BOOT=1 TF_M_TESTS_PATH=$(pwd)/../tf-m-tests TF_M_EXTRAS_PATH=$(pwd)/../tf-m-extras
Quoc Khanh Le2acaceb2024-06-20 15:07:43 +0100354clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=3 ${ARM_TBB_OPTIONS} \
355 PLAT_MHU_VERSION=3
356clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=3 ${ARM_TBB_OPTIONS} PLATFORM_TEST=rse-rotpk
357clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=3 ${ARM_TBB_OPTIONS} PLATFORM_TEST=rse-nv-counters
358clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=3 ${ARM_TBB_OPTIONS} PLATFORM_TEST=tfm-testsuite \
359 TF_M_TESTS_PATH=$(pwd)/../tf-m-tests TF_M_EXTRAS_PATH=$(pwd)/../tf-m-extras
Fathi Boudra422bf772019-12-02 11:10:16 +0200360
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530361#
362# Morello platform
363#
Chandni Cherukuricbd45962021-12-12 13:37:33 +0530364clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=fvp ${ARM_TBB_OPTIONS}
365clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=soc ${ARM_TBB_OPTIONS}
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530366
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100367#
Vishnu Banavath2cb72b32022-01-20 14:27:55 +0000368# corstone1000 Platform
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100369#
370
371make $(common_flags) \
Vishnu Banavath2cb72b32022-01-20 14:27:55 +0000372 PLAT=corstone1000 \
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100373 SPD=spmd \
374 TARGET_PLATFORM=fpga \
375 ENABLE_STACK_PROTECTOR=strong \
376 ENABLE_PIE=1 \
Maksims Svecovs7a0da522023-03-06 16:28:27 +0000377 RESET_TO_BL2=1 \
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100378 SPMD_SPM_AT_SEL2=0 \
379 ${ARM_TBB_OPTIONS} \
380 CREATE_KEYS=1 \
381 COT=tbbr \
382 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
383 bl2 \
384 bl31
385
johpow01aac58582021-10-05 16:51:34 -0500386#
387# FVP-R platform
388#
389clean_build $(common_flags) PLAT=fvp_r ${ARM_TBB_OPTIONS} ENABLE_STACK_PROTECTOR=all
390
Fathi Boudra422bf772019-12-02 11:10:16 +0200391# Partners' platforms.
392# Enable as many features as possible.
393# We don't need to clean between each build here because we only do one build
394# per platform so we don't hit the build flags dependency problem.
Fathi Boudra422bf772019-12-02 11:10:16 +0200395
Manish Pandey9c0ee742021-07-08 09:55:59 +0100396# Platforms from Mediatek
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500397make PLAT=mt8173 $(common_flags) all
398make PLAT=mt8183 $(common_flags) all
Rex-BC Chen946cace2021-11-17 10:15:42 +0800399make PLAT=mt8186 $(common_flags) COREBOOT=1 all
Bo-Chen Chen4d63afd2022-08-30 16:34:57 +0800400make PLAT=mt8188 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500401make PLAT=mt8192 $(common_flags) COREBOOT=1 all
Manish Pandey9c0ee742021-07-08 09:55:59 +0100402make PLAT=mt8195 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500403
404# Platforms from Qualcomm
405make PLAT=sc7180 $(common_flags) COREBOOT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200406
Zelalemc9531f82020-08-04 15:37:08 -0500407make PLAT=rk3288 CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500408 $(common_flags) ARCH=aarch32 AARCH32_SP=sp_min all
Madhukar Pappireddyd491ad02020-12-03 10:37:05 -0600409make PLAT=rk3368 $(common_flags) COREBOOT=1 \
410 ENABLE_STACK_PROTECTOR=strong all
411make PLAT=rk3399 $(common_flags) COREBOOT=1 PLAT_RK_DP_HDCP=1 \
412 ENABLE_STACK_PROTECTOR=strong all
413make PLAT=rk3328 $(common_flags) COREBOOT=1 PLAT_RK_SECURE_DDR_MINILOADER=1 \
414 ENABLE_STACK_PROTECTOR=strong all
415make PLAT=px30 $(common_flags) PLAT_RK_SECURE_DDR_MINILOADER=1 \
416 ENABLE_STACK_PROTECTOR=strong all
Fathi Boudra422bf772019-12-02 11:10:16 +0200417
418# Although we do several consecutive builds for the Tegra platform below, we
419# don't need to clean between each one because the Tegra makefiles specify
420# a different build directory per SoC.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500421make PLAT=tegra TARGET_SOC=t210 $(common_flags) all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500422make PLAT=tegra TARGET_SOC=t186 $(common_flags) all
423make PLAT=tegra TARGET_SOC=t194 $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200424
425# For the Xilinx platform, artificially increase the extents of BL31 memory
426# (using the platform-specific build options ZYNQMP_ATF_MEM_{BASE,SIZE}).
427# If we keep the default values, BL31 doesn't fit when it is built with all
428# these build flags.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500429make PLAT=zynqmp $(common_flags) \
Fathi Boudra422bf772019-12-02 11:10:16 +0200430 RESET_TO_BL31=1 SPD=tspd \
Zelalem4f3633e2021-06-18 11:53:47 -0500431 SDEI_SUPPORT=1 \
Fathi Boudra422bf772019-12-02 11:10:16 +0200432 ZYNQMP_ATF_MEM_BASE=0xFFFC0000 ZYNQMP_ATF_MEM_SIZE=0x00040000 \
433 all
434
Zelalemc9531f82020-08-04 15:37:08 -0500435# Build both for silicon (default) and virtual QEMU platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500436clean_build PLAT=versal $(common_flags)
437clean_build PLAT=versal $(common_flags) VERSAL_PLATFORM=versal_virt
Zelalemc9531f82020-08-04 15:37:08 -0500438
Michal Simek0f135242022-09-20 15:24:56 +0200439# Build Xilinx Versal NET platform
440clean_build PLAT=versal_net $(common_flags)
441
Jayanth Dodderi Chidanand0a2dd1e2022-10-27 11:17:37 +0100442# Build Xilinx Versal NET without Platform Management support
443clean_build PLAT=versal_net $(common_flags) TFA_NO_PM=1
444
Amit Nagalfb428442024-06-11 12:01:23 +0530445# Build Xilinx Versal Gen 2 platform
446clean_build PLAT=versal2 $(common_flags)
447
Zelalemc9531f82020-08-04 15:37:08 -0500448# Platforms from Allwinner
Andre Przywara3a78c102022-04-26 11:08:54 +0100449clean_build PLAT=sun50i_a64 $(common_flags release) all
450clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_NATIVE=0 all
451clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_SCPI=0 all
452clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_AMEND_DTB=1 all
Andre Przywaracf78a512021-09-03 14:59:38 +0100453clean_build PLAT=sun50i_h6 $(common_flags) all
454clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_NATIVE=0 all
455clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_SCPI=0 all
456clean_build PLAT=sun50i_h616 $(common_flags) all
457clean_build PLAT=sun50i_r329 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500458
459# Platforms from i.MX
460make AARCH32_SP=optee ARCH=aarch32 ARM_ARCH_MAJOR=7 ARM_CORTEX_A7=yes \
461 CROSS_COMPILE=arm-none-eabi- PLAT=warp7 ${TBB_OPTIONS} \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500462 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500463make AARCH32_SP=optee ARCH=aarch32 CROSS_COMPILE=arm-none-eabi- PLAT=picopi \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500464 $(common_flags) all
Ying-Chun Liu (PaulLiu)f6528982021-11-17 17:20:00 +0800465make PLAT=imx8mm $(common_flags) NEED_BL2=yes MEASURED_BOOT=1 \
laurenw-arm8531e702022-06-09 15:32:37 -0500466 MBOOT_EL_HASH_ALG=sha256 ${TBB_OPTIONS} all
Madhukar Pappireddyc3ec06b2022-05-18 11:15:16 -0500467make PLAT=imx8mn $(common_flags) SDEI_SUPPORT=1 all
Ying-Chun Liu (PaulLiu)413e6102021-09-14 00:22:08 +0800468make PLAT=imx8mp $(common_flags) NEED_BL2=yes ${TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500469
Jacky Baib6cecc82021-06-07 09:49:46 +0800470# Due to the limited OCRAM space that can be used for TF-A, build test
471# will report failure caused by too small RAM size, so comment out the
472# build test for imx8mq in CI. It can also resolve the following ticket:
Zelalemc9531f82020-08-04 15:37:08 -0500473# https://developer.trustedfirmware.org/T626
Jacky Baib6cecc82021-06-07 09:49:46 +0800474#make PLAT=imx8mq $(common_flags release) all
Zelalemc9531f82020-08-04 15:37:08 -0500475
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500476make PLAT=imx8qm $(common_flags) all
477make PLAT=imx8qx $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500478
Jacky Baif5e936c2023-12-27 11:11:09 +0800479make PLAT=imx8ulp $(common_flags) all
480
Jacky Bai87091a62023-06-21 16:25:12 +0800481make PLAT=imx93 $(common_flags) all
482
Olivier Deprezbac70192021-04-02 08:55:36 +0200483# Platforms for NXP Layerscape
Jiafei Pane48e56c2021-09-30 10:32:54 +0800484nxp_sb_flags="TRUSTED_BOARD_BOOT=1 CST_DIR=$(pwd) SPD=opteed"
485nxp_sb_fuse_flags="${nxp_sb_flags} FUSE_PROG=1"
486
487# Platform lx2
Olivier Deprezbac70192021-04-02 08:55:36 +0200488make PLAT=lx2160aqds $(common_flags) all
489make PLAT=lx2160ardb $(common_flags) all
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500490
491#CSF Based CoT:
Jiafei Pane48e56c2021-09-30 10:32:54 +0800492clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
493 $nxp_sb_fuse_flags DDR_PHY_BIN_PATH=$(pwd)
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500494
495#X509 Based CoT
Jiafei Pane48e56c2021-09-30 10:32:54 +0800496clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
497 $nxp_sb_flags GENERATE_COT=1 \
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500498 MBEDTLS_DIR=$(pwd)/mbedtls
499
500#BOOT_MODE=emmc and Stack protector
Jiafei Pane48e56c2021-09-30 10:32:54 +0800501clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=emmc \
502 $nxp_sb_fuse_flags ENABLE_STACK_PROTECTOR=strong
503
504# Platform ls1028ardb
505clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor
506clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc
507clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd
508
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800509# ls1028a Secure Boot
Jiafei Pane48e56c2021-09-30 10:32:54 +0800510clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor $nxp_sb_fuse_flags
511clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
512clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
Olivier Deprezbac70192021-04-02 08:55:36 +0200513
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800514# Platform ls1043ardb
515clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor
516clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand
517clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd
518
519# ls1043ardb Secure Boot
520clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
521clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
522clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
523
Jiafei Panbd0c22a2022-01-29 00:04:44 +0800524# ls1046ardb Secure Boot
525clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
526clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
527clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
528
529# ls1046afrwy Secure Boot
530clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
531clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
532
533# ls1046aqds Secure Boot
534clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
535clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
536clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
537clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
538
Jiafei Pan332cd792022-02-24 16:44:48 +0800539# ls1088ardb Secure Boot
540clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
541clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
542
543# ls1088aqds Secure Boot
544clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
545clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
546clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
547
Ghennadi Procopciuc731b0042024-02-01 09:22:26 +0200548# s32g274ardb2
549clean_build PLAT=s32g274ardb2 $(common_flags) all
550
Zelalemc9531f82020-08-04 15:37:08 -0500551# Platforms from Intel
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500552make PLAT=stratix10 $(common_flags) all
553make PLAT=agilex $(common_flags) all
Sieu Mun Tang9081bac2023-05-29 18:08:24 +0800554make PLAT=agilex5 $(common_flags) all
Sieu Mun Tang03b57362022-03-05 01:54:59 +0800555make PLAT=n5x $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500556
557# Platforms from Broadcom
Madhukar Pappireddy97ad2582021-11-15 10:29:23 -0600558clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t \
559 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 DRIVER_I2C_ENABLE=1
560clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t-ns3 \
561 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 USE_USB=yes
Zelalemc9531f82020-08-04 15:37:08 -0500562
563# Platforms from Marvell
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500564make PLAT=a3700 $(common_flags) SCP_BL2=/dev/null CM3_SYSTEM_RESET=1 \
Manish Pandey9ef33c52022-10-25 16:41:49 +0100565 A3720_DB_PM_WAKEUP_SRC=1 HANDLE_EA_EL3_FIRST_NS=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500566
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600567# Source files from mv-ddr-marvell repository are necessary
568# to build below four platforms
Manish Pandey7c1e7452021-11-05 12:54:15 +0000569wget https://downloads.trustedfirmware.org/tf-a/mv-ddr-marvell/mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
570tar -xzf mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600571mv mv-ddr-marvell drivers/marvell/mv_ddr
Zelalemc9531f82020-08-04 15:37:08 -0500572
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600573# These platforms from Marvell have dependency on GCC-6.2.1 toolchain
Pali Rohár8f890402021-07-19 13:48:05 +0200574make PLAT=a80x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200575 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200576make PLAT=a80x0_mcbin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200577 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200578make PLAT=a70x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200579 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200580make PLAT=a70x0_amc DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200581 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Robert Markodf3319e2021-10-20 11:01:12 +0200582make PLAT=a70x0_mochabin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
583 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200584make PLAT=a80x0_puzzle DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200585 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200586make PLAT=t9130 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200587 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500588make PLAT=t9130_cex7_eval DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
589 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500590
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600591# Removing the source files
592rm -rf drivers/marvell/mv_ddr 2> /dev/null
Zelalemc9531f82020-08-04 15:37:08 -0500593
594# Platforms from Meson
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500595make PLAT=gxbb $(common_flags) all
596make PLAT=gxl $(common_flags) all
597make PLAT=g12a $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500598
599# Platforms from Renesas
600# Renesas R-Car D3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500601clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500602 BL33=Makefile LIFEC_DBSC_PROTECT_ENABLE=0 LSI=D3 \
603 MBEDTLS_DIR=$(pwd)/mbedtls PMIC_ROHM_BD9571=0 \
604 RCAR_AVS_SETTING_ENABLE=0 SPD=none RCAR_LOSSY_ENABLE=0 \
605 RCAR_SA0_SIZE=0 RCAR_SYSTEM_SUSPEND=0 TRUSTED_BOARD_BOOT=1
606
607# Renesas R-Car H3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500608clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500609 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3 \
610 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
611 RCAR_DRAM_SPLIT=1 RCAR_GEN3_ULCB=1 SPD=opteed \
612 TRUSTED_BOARD_BOOT=1
613
614# Renesas R-Car H3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500615clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500616 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3N \
617 SPD=opteed TRUSTED_BOARD_BOOT=1
618
619# Renesas R-Car M3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500620clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500621 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3 \
622 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
623 RCAR_DRAM_SPLIT=2 RCAR_GEN3_ULCB=1 SPD=opteed \
624 TRUSTED_BOARD_BOOT=1
625
626# Renesas R-Car M3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500627clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500628 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3N \
629 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
630 RCAR_GEN3_ULCB=1 SPD=opteed TRUSTED_BOARD_BOOT=1
631
632# Renesas R-Car E3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500633clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500634 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=E3 \
635 RCAR_AVS_SETTING_ENABLE=0 RCAR_DRAM_DDR3L_MEMCONF=0 \
636 RCAR_SA0_SIZE=0 SPD=opteed TRUSTED_BOARD_BOOT=1
637
638# Renesas R-Car V3M Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500639clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500640 MBEDTLS_DIR=$(pwd)/mbedtls BL33=Makefile LSI=V3M MACHINE=eagle \
641 PMIC_ROHM_BD9571=0 RCAR_DRAM_SPLIT=0 RCAR_SYSTEM_SUSPEND=0 \
642 AVS_SETTING_ENABLE=0 SPD=none TRUSTED_BOARD_BOOT=1
643
Zelalemf4299672021-01-29 12:52:59 -0600644# Renesas HiHope RZ/G2M development kit
645clean_build PLAT=rzg $(common_flags) \
646 MBEDTLS_DIR=$(pwd)/mbedtls LSI=G2M \
647 RCAR_DRAM_SPLIT=2 RCAR_LOSSY_ENABLE=1 SPD=none
648
Zelalemc9531f82020-08-04 15:37:08 -0500649# Platforms from ST
Yann Gautier868044b2024-06-19 10:42:51 +0200650stm32mp1_common_flags="ARCH=aarch32 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100651 ARM_ARCH_MAJOR=7 \
652 CROSS_COMPILE=arm-none-eabi- \
653 ENABLE_STACK_PROTECTOR=strong \
654 PLAT=stm32mp1"
655
Yann Gautiera69cf792021-09-01 11:19:01 +0200656# STM32MP1 SDMMC boot
Yann Gautierb6821192024-06-19 10:45:56 +0200657clean_build $(common_flags) ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200658 BUILD_PLAT=build/stm32mp1-sdmmc/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100659 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200660
Yann Gautier15c45392023-08-21 11:03:33 +0200661# STM32MP1 SDMMC boot BL2 without AARCH32_SP
Yann Gautierb6821192024-06-19 10:45:56 +0200662clean_build $(common_flags) ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
Yann Gautier15c45392023-08-21 11:03:33 +0200663 BUILD_PLAT=build/stm32mp1-sdmmc/debug \
664 bl2
665
Yann Gautierbd871522024-01-05 15:13:58 +0100666# STM32MP1 SDMMC boot BL2 with OP-TEE & FWU
Yann Gautierb6821192024-06-19 10:45:56 +0200667clean_build $(common_flags) ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
Yann Gautierbd871522024-01-05 15:13:58 +0100668 BUILD_PLAT=build/stm32mp1-sdmmc/debug \
669 PSA_FWU_SUPPORT=1 AARCH32_SP=optee \
670 bl2
671
Yann Gautiera69cf792021-09-01 11:19:01 +0200672# STM32MP1 eMMC boot
Yann Gautierb6821192024-06-19 10:45:56 +0200673clean_build $(common_flags) ${stm32mp1_common_flags} STM32MP_EMMC=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200674 BUILD_PLAT=build/stm32mp1-emmc/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100675 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200676
677# STM32MP1 Raw NAND boot
Yann Gautierb6821192024-06-19 10:45:56 +0200678clean_build $(common_flags) ${stm32mp1_common_flags} STM32MP_RAW_NAND=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200679 BUILD_PLAT=build/stm32mp1-nand/debug \
Yann Gautierbd871522024-01-05 15:13:58 +0100680 PSA_FWU_SUPPORT=1 AARCH32_SP=optee \
681 bl2
Yann Gautiera69cf792021-09-01 11:19:01 +0200682
683# STM32MP1 SPI NAND boot
Yann Gautierb6821192024-06-19 10:45:56 +0200684clean_build $(common_flags) ${stm32mp1_common_flags} STM32MP_SPI_NAND=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200685 BUILD_PLAT=build/stm32mp1-snand/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100686 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200687
688# STM32MP1 SPI NOR boot
Yann Gautierb6821192024-06-19 10:45:56 +0200689clean_build $(common_flags) ${stm32mp1_common_flags} STM32MP_SPI_NOR=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200690 BUILD_PLAT=build/stm32mp1-snor/debug \
Govindraj Raja95f855c2023-03-01 13:11:42 +0000691 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200692
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100693# STM32MP1 UART boot
Yann Gautierb6821192024-06-19 10:45:56 +0200694clean_build $(common_flags) ${stm32mp1_common_flags} STM32MP_UART_PROGRAMMER=1 \
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100695 BUILD_PLAT=build/stm32mp1-uart/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100696 AARCH32_SP=sp_min bl2 bl32
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100697
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200698# STM32MP1 USB boot
Yann Gautierb6821192024-06-19 10:45:56 +0200699clean_build $(common_flags) ${stm32mp1_common_flags} STM32MP_USB_PROGRAMMER=1 \
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200700 BUILD_PLAT=build/stm32mp1-usb/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100701 AARCH32_SP=sp_min bl2 bl32
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200702
Lionel Debieve8f464c02022-10-13 09:25:45 +0200703# STM32MP1 TBBR
Yann Gautierb6821192024-06-19 10:45:56 +0200704clean_build $(common_flags release) ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
Yann Gautier741e8492022-11-14 19:04:27 +0100705 BUILD_PLAT=build/stm32mp1-sdmmc-tbbr/debug \
Lionel Debieve8f464c02022-10-13 09:25:45 +0200706 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100707 AARCH32_SP=sp_min bl2 bl32
Lionel Debieve8f464c02022-10-13 09:25:45 +0200708
Govindraj Raja95f855c2023-03-01 13:11:42 +0000709stm32mp13_common_flags="${stm32mp1_common_flags} \
710 AARCH32_SP=optee \
Yann Gautier937684e2024-06-20 11:41:19 +0200711 DTB_FILE_NAME=stm32mp135f-dk.dtb \
Yann Gautierbd871522024-01-05 15:13:58 +0100712 PSA_FWU_SUPPORT=1 \
Govindraj Raja95f855c2023-03-01 13:11:42 +0000713 STM32MP13=1"
714
Yann Gautier773c5502022-03-10 17:24:47 +0100715# STM32MP13 SDMMC boot
Yann Gautierb6821192024-06-19 10:45:56 +0200716clean_build $(common_flags) ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100717 BUILD_PLAT=build/stm32mp1-mp13-sdmmc/debug bl2
Yann Gautier773c5502022-03-10 17:24:47 +0100718
Yann Gautierbd871522024-01-05 15:13:58 +0100719# STM32MP13 SDMMC boot with FWU
Yann Gautierb6821192024-06-19 10:45:56 +0200720clean_build $(common_flags) ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Yann Gautierbd871522024-01-05 15:13:58 +0100721 PSA_FWU_SUPPORT=1 \
722 BUILD_PLAT=build/stm32mp1-mp13-sdmmc/debug bl2
723
Lionel Debieve8f464c02022-10-13 09:25:45 +0200724# STM32MP13 TBBR
Yann Gautierb6821192024-06-19 10:45:56 +0200725clean_build $(common_flags release) ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Lionel Debieve8f464c02022-10-13 09:25:45 +0200726 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100727 BUILD_PLAT=build/stm32mp1-mp13-sdmmc-tbbr/debug bl2
Lionel Debieve8f464c02022-10-13 09:25:45 +0200728
Yann Gautiera66e5012022-12-13 13:52:35 +0100729# STM32MP13 TBBR DECRYPTION AES GCM
Yann Gautierb6821192024-06-19 10:45:56 +0200730clean_build $(common_flags release) ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Yann Gautiera66e5012022-12-13 13:52:35 +0100731 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
732 DECRYPTION_SUPPORT=aes_gcm ENCRYPT_BL32=1 \
733 BUILD_PLAT=build/stm32mp1-mp13-sdmmc-tbbr-dec/debug bl2
734
Yann Gautier868044b2024-06-19 10:42:51 +0200735stm32mp2_common_flags="ARCH=aarch64 \
Yann Gautiere9da1e22023-08-11 14:50:04 +0200736 CROSS_COMPILE=aarch64-none-elf- \
737 PLAT=stm32mp2"
738
739# STM32MP25 SDMMC boot
Yann Gautierb6821192024-06-19 10:45:56 +0200740clean_build $(common_flags) ${stm32mp2_common_flags} STM32MP_SDMMC=1 \
Yann Gautiere9da1e22023-08-11 14:50:04 +0200741 SPD=opteed STM32MP_DDR4_TYPE=1 \
742 BUILD_PLAT=build/stm32mp2-mp25-sdmmc/debug
743
Yann Gautier83dc8702024-03-19 15:07:26 +0100744# STM32MP25 USB boot
Yann Gautierb6821192024-06-19 10:45:56 +0200745clean_build $(common_flags) ${stm32mp2_common_flags} STM32MP_USB_PROGRAMMER=1 \
Yann Gautier83dc8702024-03-19 15:07:26 +0100746 SPD=opteed STM32MP_DDR4_TYPE=1 \
Yann Gautier63ee8832024-03-20 13:49:15 +0100747 BUILD_PLAT=build/stm32mp2-mp25-usb/debug
Yann Gautier83dc8702024-03-19 15:07:26 +0100748
Zelalemc9531f82020-08-04 15:37:08 -0500749# Platforms from TI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500750make PLAT=k3 $(common_flags) all
Hari Nagalladadd89f2022-08-30 12:10:00 -0500751make PLAT=k3 TARGET_BOARD=j784s4 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500752
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500753clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS}
Zelalemc9531f82020-08-04 15:37:08 -0500754# Use GICV3 driver
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500755clean_build PLAT=qemu $(common_flags) QEMU_USE_GIC_DRIVER=QEMU_GICV3 \
Zelalemc9531f82020-08-04 15:37:08 -0500756 ENABLE_STACK_PROTECTOR=strong
Dongjiu Geng72819ee2023-06-16 18:48:57 +0800757# Use GICV3 driver with SDEI support
758clean_build PLAT=qemu $(common_flags) QEMU_USE_GIC_DRIVER=QEMU_GICV3 \
759 ENABLE_STACK_PROTECTOR=strong SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Zelalemc9531f82020-08-04 15:37:08 -0500760# Use encrypted FIP feature.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500761clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500762 BL32_RAM_LOCATION=tdram DECRYPTION_SUPPORT=aes_gcm ENCRYPT_BL31=1 \
763 ENCRYPT_BL32=1 FW_ENC_STATUS=0 SPD=opteed
Jens Wiklander1a9c2be2021-11-26 09:56:55 +0100764# QEMU with SPMD support
765clean_build PLAT=qemu $(common_flags) BL32=Makefile \
766 BL32_RAM_LOCATION=tdram ARM_BL31_IN_DRAM=1 \
767 SPD=spmd CTX_INCLUDE_EL2_REGS=0 SPMD_SPM_AT_SEL2=0 SPMC_OPTEE=1
Ruchika Gupta86e7f682022-04-12 10:25:46 +0530768# Measured Boot
laurenw-arm8531e702022-06-09 15:32:37 -0500769clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} MBOOT_EL_HASH_ALG=sha256 MEASURED_BOOT=1
Raymond Mao7681ba02023-08-10 14:05:44 -0700770# Transfer List
771clean_build PLAT=qemu $(common_flags) TRANSFER_LIST=1
Zelalemc9531f82020-08-04 15:37:08 -0500772
Jean-Philippe Bruckerb586eee2023-11-02 18:13:30 +0000773# FEAT_RME
774clean_build PLAT=qemu $(common_flags) ENABLE_RME=1 \
775 QEMU_USE_GIC_DRIVER=QEMU_GICV3
776
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500777clean_build PLAT=qemu_sbsa $(common_flags)
Fathi Boudra422bf772019-12-02 11:10:16 +0200778
Zelalemd86e8762020-08-21 18:24:28 -0500779# QEMU with SPM support
780clean_build PLAT=qemu_sbsa $(common_flags) BL32=Makefile SPM_MM=1 \
Paul Sokolovskycf9fe862023-01-02 16:22:21 +0300781 EL3_EXCEPTION_HANDLING=1 ENABLE_SME_FOR_NS=0 ENABLE_SVE_FOR_NS=0
Zelalemd86e8762020-08-21 18:24:28 -0500782
Fathi Boudra422bf772019-12-02 11:10:16 +0200783# For hikey enable PMF to include all files in the platform port
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500784make PLAT=hikey $(common_flags) ${TBB_OPTIONS} ENABLE_PMF=1 all
785make PLAT=hikey960 $(common_flags) ${TBB_OPTIONS} all
Lukas Haneld0752392022-10-13 11:13:19 +0200786make PLAT=hikey960 $(common_flags) ${TBB_OPTIONS} SPD=spmd SPMC_AT_EL3=1 \
787 SPMD_SPM_AT_SEL2=0 BL32=optee PLAT_SP_MANIFEST_DTS=foo NEED_FDT=no all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500788make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200789
Zelalemc9531f82020-08-04 15:37:08 -0500790# Platforms from Socionext
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500791clean_build PLAT=uniphier $(common_flags) ${TBB_OPTIONS} SPD=tspd
792clean_build PLAT=uniphier $(common_flags) FIP_GZIP=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200793
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500794clean_build PLAT=synquacer $(common_flags) SPM_MM=1 \
Jassi Brar86080922022-06-27 14:16:34 -0500795 RESET_TO_BL31=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0 \
796 PRELOADED_BL33_BASE=0x0
Zelalemc9531f82020-08-04 15:37:08 -0500797
798# Support for SCP Message Interface protocol with platform specific drivers
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500799clean_build PLAT=synquacer $(common_flags) \
Jassi Brar86080922022-06-27 14:16:34 -0500800 RESET_TO_BL31=1 PRELOADED_BL33_BASE=0x0 SQ_USE_SCMI_DRIVER=1
Zelalemc9531f82020-08-04 15:37:08 -0500801
Jassi Brarb8c7ca02022-06-27 14:22:10 -0500802# Support for BL2 and TBBR
803clean_build PLAT=synquacer $(common_flags) \
804 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
805 SQ_USE_SCMI_DRIVER=1 SPD=opteed all
806
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500807make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200808
Zelalemc9531f82020-08-04 15:37:08 -0500809# Raspberry Pi Platforms
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500810make PLAT=rpi3 $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500811 ENABLE_STACK_PROTECTOR=strong PRELOADED_BL33_BASE=0xDEADBEEF all
Andre Przywarae917ec82021-09-03 15:01:30 +0100812clean_build PLAT=rpi4 $(common_flags) SMC_PCI_SUPPORT=1 all
Mario Bălănicăea4da5e2024-03-08 20:09:24 +0200813clean_build PLAT=rpi5 $(common_flags) SMC_PCI_SUPPORT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200814
Zelalemc9531f82020-08-04 15:37:08 -0500815# A113D (AXG) platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500816clean_build PLAT=axg $(common_flags) SPD=opteed
817clean_build PLAT=axg $(common_flags) AML_USE_ATOS=1
Zelalemc9531f82020-08-04 15:37:08 -0500818
Stephan Gerhold141a7662021-12-07 20:42:14 +0100819# QTI MSM8916 platform
Stephan Gerhold3b3976f2023-04-17 16:27:11 +0200820clean_build PLAT=mdm9607 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
821 ARCH=aarch32 AARCH32_SP=sp_min
822clean_build PLAT=msm8909 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
823 ARCH=aarch32 AARCH32_SP=sp_min
Stephan Gerhold141a7662021-12-07 20:42:14 +0100824clean_build PLAT=msm8916 $(common_flags)
Manish V Badarkhec540e622023-06-28 17:56:40 +0100825clean_build PLAT=msm8916 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
826 ARCH=aarch32 AARCH32_SP=sp_min
Stephan Gerhold998f0d62023-04-17 16:22:52 +0200827clean_build PLAT=msm8916 $(common_flags) SPD=tspd
Stephan Gerhold3b3976f2023-04-17 16:27:11 +0200828clean_build PLAT=msm8939 $(common_flags)
829clean_build PLAT=msm8939 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
830 ARCH=aarch32 AARCH32_SP=sp_min
831clean_build PLAT=msm8939 $(common_flags) SPD=tspd
Stephan Gerhold141a7662021-12-07 20:42:14 +0100832
Chia-Wei Wang7dcb0d02023-06-09 09:52:52 +0800833# Platforms from Aspeed
834clean_build PLAT=ast2700 $(common_flags) SPD=opteed
835
rutigl@gmail.com86cfcf92023-03-21 10:10:11 +0200836# Nuvoton npcm845x platform
837make PLAT=npcm845x $(common_flags) all SPD=opteed
838
Harrison Mutaiee958c12023-09-06 12:16:21 +0100839if [[ "$rc" -gt 0 ]]; then
Harrison Mutai3f483132024-05-09 09:48:58 +0000840 echo "ERROR: tf-cov-make failed with $error_count failures"
Harrison Mutaiee958c12023-09-06 12:16:21 +0100841 exit $rc
842fi
843
Fathi Boudra422bf772019-12-02 11:10:16 +0200844cd ..