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Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -05001#!/usr/bin/env bash
Fathi Boudra422bf772019-12-02 11:10:16 +02002#
Rohit Mathew17675f22024-02-14 22:41:37 +00003# Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
Fathi Boudra422bf772019-12-02 11:10:16 +02004#
5# SPDX-License-Identifier: BSD-3-Clause
6#
7
8#
9# This script builds the TF in different configs.
10# Rather than telling cov-build to build TF using a simple 'make all' command,
11# the goal here is to combine several build flags to analyse more of our source
12# code in a single 'build'. The Coverity Scan service does not have the notion
13# of separate types of build - there is just one linear sequence of builds in
14# the project history.
15#
16
Harrison Mutaiee958c12023-09-06 12:16:21 +010017set -E
18trap 'rc=$?; error_count=$((error_count+1));' ERR INT
Fathi Boudra422bf772019-12-02 11:10:16 +020019
20TF_SOURCES=$1
21if [ ! -d "$TF_SOURCES" ]; then
22 echo "ERROR: '$TF_SOURCES' does not exist or is not a directory"
23 echo "Usage: $(basename "$0") <trusted-firmware-directory>"
24 exit 1
25fi
26
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050027containing_dir="$(readlink -f "$(dirname "$0")/")"
28. $containing_dir/common-def.sh
29
Fathi Boudra422bf772019-12-02 11:10:16 +020030# Get mbed TLS library code to build Trusted Firmware with Trusted Board Boot
31# support. The version of mbed TLS to use here must be the same as when
32# building TF in the usual context.
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050033if [ ! -d "$MBED_TLS_DIR" ]; then
34 git clone -q --depth 1 -b "$MBED_TLS_SOURCES_TAG" "$MBED_TLS_URL_REPO" "$MBED_TLS_DIR"
Fathi Boudra422bf772019-12-02 11:10:16 +020035fi
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050036
David Vincze82db6932024-02-21 12:05:50 +010037if [ ! -d "$QCBOR_LIB_DIR" ]; then
38 git clone "$QCBOR_URL_REPO" "$QCBOR_LIB_DIR"
39 cd "$QCBOR_LIB_DIR"
40 git checkout v1.2
41fi
42
Fathi Boudra422bf772019-12-02 11:10:16 +020043cd "$TF_SOURCES"
44
45# Clean TF source dir to make sure we don't analyse temporary files.
46make distclean
47
48#
49# Build TF in different configurations to get as much coverage as possible
50#
51
Fathi Boudra422bf772019-12-02 11:10:16 +020052#
53# FVP platform
54# We'll use the following flags for all FVP builds.
55#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050056fvp_common_flags="$(common_flags) PLAT=fvp"
Fathi Boudra422bf772019-12-02 11:10:16 +020057
58# Try all possible SPDs.
Chris Kayab29d432023-08-10 13:06:18 +000059clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram \
60 SPD=tspd FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +020061clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd TSP_INIT_ASYNC=1 \
Sona Mathew40e5be92023-08-10 16:31:45 -050062 TSP_NS_INTR_ASYNC_PREEMPT=1 FVP_TRUSTED_SRAM_SIZE=384
Manish V Badarkhe48ed0bf2023-06-28 09:33:16 +010063clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed FVP_TRUSTED_SRAM_SIZE=384
Elizabeth Ho1a04df12023-07-27 16:06:24 +010064clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tlkd FVP_TRUSTED_SRAM_SIZE=384
Manish V Badarkhee7528ff2023-07-01 10:20:05 +010065clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=pncd SPD_PNCD_NS_IRQ=126 \
66 SPD_PNCD_S_IRQ=15 FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +020067
Zelalemc9531f82020-08-04 15:37:08 -050068# Dualroot chain of trust.
Harrison Mutai0dd5f532024-03-15 13:42:40 +000069clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tspd COT=dualroot \
70 FVP_TRUSTED_SRAM_SIZE=384
Zelalemc9531f82020-08-04 15:37:08 -050071
laurenw-armf48e9d22022-04-22 11:30:13 -050072# FEAT_RME with CCA chain of trust.
Manish V Badarkhe5304aaf2023-08-18 14:38:20 +010073clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} USE_ROMLIB=1 \
Manish V Badarkhed5e9c752023-11-07 17:57:36 +000074 ENABLE_RME=1 MEASURED_BOOT=1
laurenw-armf48e9d22022-04-22 11:30:13 -050075
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050076clean_build $fvp_common_flags SPD=trusty
77clean_build $fvp_common_flags SPD=trusty TRUSTY_SPD_WITH_GENERIC_SERVICES=1
Fathi Boudra422bf772019-12-02 11:10:16 +020078
Sona Mathewff9c2a72023-05-10 21:18:01 -050079# ERRATA ABI
80clean_build $fvp_common_flags ERRATA_ABI_SUPPORT=1
81
Fathi Boudra422bf772019-12-02 11:10:16 +020082# SDEI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050083clean_build $fvp_common_flags SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Fathi Boudra422bf772019-12-02 11:10:16 +020084
Zelalemc9531f82020-08-04 15:37:08 -050085# SDEI with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050086clean_build $fvp_common_flags SDEI_IN_FCONF=1 SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Zelalemc9531f82020-08-04 15:37:08 -050087
Zelalem4f3633e2021-06-18 11:53:47 -050088# PCI Service
89clean_build $fvp_common_flags SMC_PCI_SUPPORT=1
90
Zelalemc9531f82020-08-04 15:37:08 -050091# Secure interrupt descriptors with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050092clean_build $fvp_common_flags SEC_INT_DESC_IN_FCONF=1
Zelalemc9531f82020-08-04 15:37:08 -050093
Fathi Boudra422bf772019-12-02 11:10:16 +020094# Without coherent memory
Sona Mathewa06f62d2023-08-24 16:34:13 -050095clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd \
96 USE_COHERENT_MEM=0 FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +020097
98# Using PSCI extended State ID format rather than the original format
Sona Mathewa06f62d2023-08-24 16:34:13 -050099clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd \
100 PSCI_EXTENDED_STATE_ID=1 ARM_RECOM_STATE_ID_ENC=1 FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +0200101
102# Alternative boot flows (This changes some of the platform initialisation code)
Elizabeth Ho4cdb2f42023-07-11 12:27:14 +0100103clean_build $fvp_common_flags EL3_PAYLOAD_BASE=0x80000000
Fathi Boudra422bf772019-12-02 11:10:16 +0200104clean_build $fvp_common_flags PRELOADED_BL33_BASE=0x80000000
105
106# Using the SP804 timer instead of the Generic Timer
107clean_build $fvp_common_flags FVP_USE_SP804_TIMER=1
108
109# Using the CCN driver and multi cluster topology
110clean_build $fvp_common_flags FVP_CLUSTER_COUNT=4
111
112# PMF
113clean_build $fvp_common_flags ENABLE_PMF=1
114
115# stack protector
116clean_build $fvp_common_flags ENABLE_STACK_PROTECTOR=strong
117
118# AArch32 build
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500119clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200120 ARCH=aarch32 AARCH32_SP=sp_min \
121 RESET_TO_SP_MIN=1 PRELOADED_BL33_BASE=0x80000000
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500122clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200123 ARCH=aarch32 AARCH32_SP=sp_min
124
125# Xlat tables lib version 1 (AArch64 and AArch32)
126clean_build $fvp_common_flags ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500127clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200128 ARCH=aarch32 AARCH32_SP=sp_min ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
129
Zelalemc9531f82020-08-04 15:37:08 -0500130# SPM support based on Management Mode Interface Specification
Manish Pandeyaa9a03b2021-11-17 10:03:17 +0000131clean_build $fvp_common_flags SPM_MM=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0
Fathi Boudra422bf772019-12-02 11:10:16 +0200132
Zelalemc9531f82020-08-04 15:37:08 -0500133# SPM support with TOS(optee) as SPM sitting at S-EL1
134clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0
135
Shruti Gupta8cc89b92022-08-09 12:23:46 +0100136# SPM support with SPM at EL3 and TSP at S-EL1
137clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 CTX_INCLUDE_EL2_REGS=0 EL3_EXCEPTION_HANDLING=0 \
138 SPD=spmd SPMD_SPM_AT_SEL2=0 SPMC_AT_EL3=1 \
139 ARM_SPMC_MANIFEST_DTS=plat/arm/board/fvp/fdts/fvp_tsp_sp_manifest.dts
140
Zelalemc9531f82020-08-04 15:37:08 -0500141# SPM support with Secure hafnium as SPM sitting at S-EL2
142# SP_LAYOUT_FILE is used only during FIP creation but build won't progress
143# if we have NULL value to it, so passing a dummy string.
144clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=1 ARM_ARCH_MINOR=4 \
Max Shvetsov44d2a702021-02-18 16:41:45 +0000145 CTX_INCLUDE_EL2_REGS=1 SP_LAYOUT_FILE=dummy
Fathi Boudra422bf772019-12-02 11:10:16 +0200146
J-Alves85ba07b2023-07-12 14:37:45 +0100147# SPM support with logical partitions in the SPMD.
148clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=1 ARM_ARCH_MINOR=4 \
149 CTX_INCLUDE_EL2_REGS=1 SP_LAYOUT_FILE=dummy ENABLE_SPMD_LP=1
150
Marc Bonnici502fdaa2022-01-10 12:38:23 +0000151# SPM support with SPM sitting at EL3
152clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0 SPMC_AT_EL3=1
153
Harrison Mutaib352c0e2023-08-11 18:27:57 +0100154# Firmware Handoff framework support
155clean_build $fvp_common_flags TRANSFER_LIST=1
156
Fathi Boudra422bf772019-12-02 11:10:16 +0200157#BL2 at EL3 support
Harrison Mutaic3c8cfc2023-09-05 12:03:03 +0100158clean_build $fvp_common_flags RESET_TO_BL2=1 FVP_TRUSTED_SRAM_SIZE=384
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500159clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Maksims Svecovs7a0da522023-03-06 16:28:27 +0000160 ARCH=aarch32 AARCH32_SP=sp_min RESET_TO_BL2=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200161
Zelalemc9531f82020-08-04 15:37:08 -0500162# RAS Extension Support
Manish Pandeyc1fa25b2023-02-16 17:35:36 +0000163clean_build $fvp_common_flags EL3_EXCEPTION_HANDLING=1 ENABLE_FEAT_RAS=1 \
Manish Pandeyf3816802023-10-11 17:13:58 +0100164 FAULT_INJECTION_SUPPORT=1 HANDLE_EA_EL3_FIRST_NS=1 \
Manish Pandey010e9b42023-04-24 15:49:27 +0100165 SDEI_SUPPORT=1 PLATFORM_TEST_RAS_FFH=1
Zelalemc9531f82020-08-04 15:37:08 -0500166
Manish Pandeyfd4c6b72023-04-24 10:29:52 +0100167# EA handled in EL3 first
168clean_build $fvp_common_flags HANDLE_EA_EL3_FIRST_NS=1 PLATFORM_TEST_EA_FFH=1
169
Zelalemc9531f82020-08-04 15:37:08 -0500170# Hardware Assisted Coherency(DynamIQ)
171clean_build $fvp_common_flags FVP_CLUSTER_COUNT=1 FVP_MAX_CPUS_PER_CLUSTER=8 \
172 HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0
173
174# Pointer Authentication Support
175clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 \
Sona Mathewa06f62d2023-08-24 16:34:13 -0500176 ARM_ARCH_MINOR=5 EL3_EXCEPTION_HANDLING=1 BRANCH_PROTECTION=1 SDEI_SUPPORT=1 SPD=tspd \
Sona Mathew08c17962023-08-28 09:36:17 -0500177 TSP_NS_INTR_ASYNC_PREEMPT=1 FVP_TRUSTED_SRAM_SIZE=384
Zelalemc9531f82020-08-04 15:37:08 -0500178
179# Undefined Behaviour Sanitizer
180# Building with UBSAN SANITIZE_UB=on increases the executable size.
181# Hence it is only properly supported in bl31 with RESET_TO_BL31 enabled
182make $fvp_common_flags clean
Manish V Badarkhe4e79cab2023-09-07 10:07:58 +0100183make $fvp_common_flags SANITIZE_UB=on RESET_TO_BL31=1 FVP_TRUSTED_SRAM_SIZE=384 bl31
Zelalemc9531f82020-08-04 15:37:08 -0500184
185# debugfs feature
186clean_build $fvp_common_flags DEBUG=1 USE_DEBUGFS=1
187
188# MPAM feature
Arvind Ram Prakashbd4e43a2023-10-02 11:12:34 -0500189clean_build $fvp_common_flags ENABLE_FEAT_MPAM=1
Zelalemc9531f82020-08-04 15:37:08 -0500190
191# Using GICv3.1 driver with extended PPI and SPI range
192clean_build $fvp_common_flags GIC_EXT_INTID=1
193
194# Using GICv4 features with extended PPI and SPI range
195clean_build $fvp_common_flags GIC_ENABLE_V4_EXTN=1 GIC_EXT_INTID=1
196
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100197# Measured Boot
laurenw-arm8531e702022-06-09 15:32:37 -0500198clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} MBOOT_EL_HASH_ALG=sha256 MEASURED_BOOT=1 USE_ROMLIB=1
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100199
Manish V Badarkhef43e3f52022-06-21 20:37:25 +0100200# DRTM
201clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} TPM_HASH_ALG=sha256 DRTM_SUPPORT=1 USE_ROMLIB=1
202
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100203# CoT descriptors in device tree
Manish V Badarkhe81102d12020-10-05 08:02:30 +0100204clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} COT_DESC_IN_DTB=1 USE_ROMLIB=1
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100205
Chris Kayf4789fe2023-06-12 15:52:28 +0100206# PSA FWU support
207clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_GPT_SUPPORT=1 PSA_FWU_SUPPORT=1 USE_ROMLIB=1 FVP_TRUSTED_SRAM_SIZE=384
Manish V Badarkhe107c8e32021-08-02 19:49:32 +0100208
Manish V Badarkhe92616ae2023-09-18 10:06:00 +0100209# PSA Crypto support
210clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} PSA_CRYPTO=1 FVP_TRUSTED_SRAM_SIZE=384
211
johpow01153c8b22021-11-03 14:38:36 -0500212# SME and HCX features
213clean_build $fvp_common_flags ENABLE_SME_FOR_NS=1 ENABLE_FEAT_HCX=1
214
Jayanth Dodderi Chidanand41edd012023-01-12 14:50:34 +0000215# SME2
216clean_build $fvp_common_flags ENABLE_SME2_FOR_NS=1 ENABLE_SME_FOR_NS=1 ENABLE_FEAT_HCX=1
217
Jayanth Dodderi Chidanand84da1962022-04-11 11:38:44 +0100218# Architectural Feature Detection mechanism
219clean_build $fvp_common_flags FEATURE_DETECTION=1
220
Manish Pandeye3561fd2023-01-05 10:46:25 +0000221# RNG trap feature
222clean_build $fvp_common_flags ENABLE_FEAT_RNG=1 ENABLE_FEAT_RNG_TRAP=1
223
Yi Choua765ae42023-05-26 15:51:02 +0800224# OPTEE_ALLOW_SMC_LOAD and CROS_WIDEVINE_SMC features
225clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed OPTEE_ALLOW_SMC_LOAD=1 CROS_WIDEVINE_SMC=1 PLAT_XLAT_TABLES_DYNAMIC=1 FVP_TRUSTED_SRAM_SIZE=384
Jeffrey Kardatzke09e18e22023-01-25 12:24:13 -0800226
Jayanth Dodderi Chidanand508936d2023-12-22 14:33:38 +0000227# Report Context_Memory
228clean_build $fvp_common_flags PLATFORM_REPORT_CTX_MEM_USE=1
229
Govindraj Rajaef67db82024-05-02 09:57:13 -0500230# Build newer CPU's with no model available yet.
231clean_build $fvp_common_flags CTX_INCLUDE_AARCH32_REGS=0 HW_ASSISTED_COHERENCY=1 \
232 USE_COHERENT_MEM=0 BUILD_CPUS_WITH_NO_FVP_MODEL=1 FVP_TRUSTED_SRAM_SIZE=384
233
Fathi Boudra422bf772019-12-02 11:10:16 +0200234#
235# Juno platform
236# We'll use the following flags for all Juno builds.
237#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500238juno_common_flags="$(common_flags) PLAT=juno"
Fathi Boudra422bf772019-12-02 11:10:16 +0200239clean_build $juno_common_flags SPD=tspd ${ARM_TBB_OPTIONS}
Elizabeth Ho4cdb2f42023-07-11 12:27:14 +0100240clean_build $juno_common_flags EL3_PAYLOAD_BASE=0x80000000
Manish V Badarkhe05626442023-09-12 09:54:50 +0100241clean_build $juno_common_flags ENABLE_STACK_PROTECTOR=strong ETHOSN_NPU_DRIVER=1
Harrison Mutaid8aff2a2024-05-08 10:40:21 +0000242# FIXME: temporarily disable debug builds for this configuration until BL2 size
243# issues are resolved.
244clean_build "$(common release) PLAT=juno" ${ARM_TBB_OPTIONS} \
245 ENABLE_STACK_PROTECTOR=strong ETHOSN_NPU_DRIVER=1 ETHOSN_NPU_TZMP1=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200246clean_build $juno_common_flags CSS_USE_SCMI_SDS_DRIVER=0
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500247
Jayanth Dodderi Chidanand055394a2022-10-19 09:20:20 +0100248# TRNG Service
249clean_build $juno_common_flags TRNG_SUPPORT=1
250
Fathi Boudra422bf772019-12-02 11:10:16 +0200251#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530252# Reference Design platform RD-V1
Zelalemc9531f82020-08-04 15:37:08 -0500253#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530254make $(common_flags) PLAT=rdv1 ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500255
256#
Aditya Angadi61c54762021-01-04 09:30:52 +0530257# Reference Design platform RD-V1-MC
Zelalemc9531f82020-08-04 15:37:08 -0500258#
Rohit Mathew17675f22024-02-14 22:41:37 +0000259make $(common_flags) PLAT=rdv1mc ${ARM_TBB_OPTIONS} NRD_CHIP_COUNT=4 all
Zelalemc9531f82020-08-04 15:37:08 -0500260
261#
Vijayenthiran Subramaniama66de332020-11-23 14:20:14 +0530262# Reference Design Platform RD-N2
263#
264make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} all
Omkar Anand Kulkarnif6e268e2023-06-21 20:32:22 +0530265# RAS Extension Support
266make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} ENABLE_FEAT_RAS=1 \
Manish Pandeyf3816802023-10-11 17:13:58 +0100267 HANDLE_EA_EL3_FIRST_NS=1 SDEI_SUPPORT=1 SPM_MM=1 all
268
Nishant Sharmabd7092e2023-10-11 09:17:13 +0100269# SPMC At EL3 Support
270make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} SPMC_AT_EL3=1 SPD=spmd \
271 SPMD_SPM_AT_SEL2=0 BL32=1 SPMC_AT_EL3_SEL0_SP=1 EL3_EXCEPTION_HANDLING=1 \
272 PLAT_RO_XLAT_TABLES=1 all
Vijayenthiran Subramaniama66de332020-11-23 14:20:14 +0530273
274#
Zelalemc9531f82020-08-04 15:37:08 -0500275# Neoverse N1 SDP platform
276#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500277make $(common_flags) PLAT=n1sdp ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500278
279#
280# FVP VE platform
281#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500282make $(common_flags) PLAT=fvp_ve AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500283 CROSS_COMPILE=arm-none-eabi- ARM_ARCH_MAJOR=7 \
284 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
285 FVP_HW_CONFIG_DTS=fdts/fvp-ve-Cortex-A5x1.dts all
286
287#
288# A5 DesignStart Platform
289#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500290make $(common_flags) PLAT=a5ds AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500291 ARM_ARCH_MAJOR=7 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
292 CROSS_COMPILE=arm-none-eabi- FVP_HW_CONFIG_DTS=fdts/a5ds.dts
293
294#
295# Corstone700 Platform
296#
297
298corstone700_common_flags="CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500299 $(common_flags) \
Zelalemc9531f82020-08-04 15:37:08 -0500300 PLAT=corstone700 \
301 ARCH=aarch32 \
302 RESET_TO_SP_MIN=1 \
303 AARCH32_SP=sp_min \
304 ARM_LINUX_KERNEL_AS_BL33=0 \
305 ARM_PRELOADED_DTB_BASE=0x80400000 \
306 ENABLE_PIE=1 \
Zelalemc9531f82020-08-04 15:37:08 -0500307 ENABLE_STACK_PROTECTOR=all \
308 all"
309
310echo "Info: Building Corstone700 FVP ..."
311
312make TARGET_PLATFORM=fvp ${corstone700_common_flags}
313
314echo "Info: Building Corstone700 FPGA ..."
315
316make TARGET_PLATFORM=fpga ${corstone700_common_flags}
317
318#
319# Arm internal FPGA port
320#
Andre Przywara13361b62022-04-26 11:16:55 +0100321make PLAT=arm_fpga $(common_flags release) \
322 FPGA_PRELOADED_DTB_BASE=0x88000000 PRELOADED_BL33_BASE=0x82080000 all
Zelalemc9531f82020-08-04 15:37:08 -0500323
324#
Usama Arifcba711d2021-08-04 15:53:42 +0100325# Total Compute platforms
Zelalemc9531f82020-08-04 15:37:08 -0500326#
laurenw-arm915f70a2023-07-14 16:20:49 -0500327clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=1 ${ARM_TBB_OPTIONS}
Joel Goddard571a93c2024-02-29 15:31:48 +0000328clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} MEASURED_BOOT=1 \
329 PLAT_MHU_VERSION=3
David Vincze82db6932024-02-21 12:05:50 +0100330clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} MEASURED_BOOT=1 \
331 DICE_PROTECTION_ENVIRONMENT=1 QCBOR_DIR=$(pwd)/qcbor
David Vinczed8ed5622024-02-23 17:00:12 +0100332clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} PLATFORM_TEST=rse-rotpk
333clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} PLATFORM_TEST=rse-nv-counters
Manish V Badarkhe58a88f02023-11-06 21:42:11 +0000334clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} PLATFORM_TEST=tfm-testsuite \
Manish V Badarkhe8f3a3fa2024-03-13 11:37:46 +0000335 MEASURED_BOOT=1 TF_M_TESTS_PATH=$(pwd)/../tf-m-tests TF_M_EXTRAS_PATH=$(pwd)/../tf-m-extras
Fathi Boudra422bf772019-12-02 11:10:16 +0200336
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530337#
338# Morello platform
339#
Chandni Cherukuricbd45962021-12-12 13:37:33 +0530340clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=fvp ${ARM_TBB_OPTIONS}
341clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=soc ${ARM_TBB_OPTIONS}
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530342
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100343#
Vishnu Banavath2cb72b32022-01-20 14:27:55 +0000344# corstone1000 Platform
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100345#
346
347make $(common_flags) \
Vishnu Banavath2cb72b32022-01-20 14:27:55 +0000348 PLAT=corstone1000 \
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100349 SPD=spmd \
350 TARGET_PLATFORM=fpga \
351 ENABLE_STACK_PROTECTOR=strong \
352 ENABLE_PIE=1 \
Maksims Svecovs7a0da522023-03-06 16:28:27 +0000353 RESET_TO_BL2=1 \
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100354 SPMD_SPM_AT_SEL2=0 \
355 ${ARM_TBB_OPTIONS} \
356 CREATE_KEYS=1 \
357 COT=tbbr \
358 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
359 bl2 \
360 bl31
361
johpow01aac58582021-10-05 16:51:34 -0500362#
363# FVP-R platform
364#
365clean_build $(common_flags) PLAT=fvp_r ${ARM_TBB_OPTIONS} ENABLE_STACK_PROTECTOR=all
366
Fathi Boudra422bf772019-12-02 11:10:16 +0200367# Partners' platforms.
368# Enable as many features as possible.
369# We don't need to clean between each build here because we only do one build
370# per platform so we don't hit the build flags dependency problem.
Fathi Boudra422bf772019-12-02 11:10:16 +0200371
Manish Pandey9c0ee742021-07-08 09:55:59 +0100372# Platforms from Mediatek
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500373make PLAT=mt8173 $(common_flags) all
374make PLAT=mt8183 $(common_flags) all
Rex-BC Chen946cace2021-11-17 10:15:42 +0800375make PLAT=mt8186 $(common_flags) COREBOOT=1 all
Bo-Chen Chen4d63afd2022-08-30 16:34:57 +0800376make PLAT=mt8188 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500377make PLAT=mt8192 $(common_flags) COREBOOT=1 all
Manish Pandey9c0ee742021-07-08 09:55:59 +0100378make PLAT=mt8195 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500379
380# Platforms from Qualcomm
381make PLAT=sc7180 $(common_flags) COREBOOT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200382
Zelalemc9531f82020-08-04 15:37:08 -0500383make PLAT=rk3288 CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500384 $(common_flags) ARCH=aarch32 AARCH32_SP=sp_min all
Madhukar Pappireddyd491ad02020-12-03 10:37:05 -0600385make PLAT=rk3368 $(common_flags) COREBOOT=1 \
386 ENABLE_STACK_PROTECTOR=strong all
387make PLAT=rk3399 $(common_flags) COREBOOT=1 PLAT_RK_DP_HDCP=1 \
388 ENABLE_STACK_PROTECTOR=strong all
389make PLAT=rk3328 $(common_flags) COREBOOT=1 PLAT_RK_SECURE_DDR_MINILOADER=1 \
390 ENABLE_STACK_PROTECTOR=strong all
391make PLAT=px30 $(common_flags) PLAT_RK_SECURE_DDR_MINILOADER=1 \
392 ENABLE_STACK_PROTECTOR=strong all
Fathi Boudra422bf772019-12-02 11:10:16 +0200393
394# Although we do several consecutive builds for the Tegra platform below, we
395# don't need to clean between each one because the Tegra makefiles specify
396# a different build directory per SoC.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500397make PLAT=tegra TARGET_SOC=t210 $(common_flags) all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500398make PLAT=tegra TARGET_SOC=t186 $(common_flags) all
399make PLAT=tegra TARGET_SOC=t194 $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200400
401# For the Xilinx platform, artificially increase the extents of BL31 memory
402# (using the platform-specific build options ZYNQMP_ATF_MEM_{BASE,SIZE}).
403# If we keep the default values, BL31 doesn't fit when it is built with all
404# these build flags.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500405make PLAT=zynqmp $(common_flags) \
Fathi Boudra422bf772019-12-02 11:10:16 +0200406 RESET_TO_BL31=1 SPD=tspd \
Zelalem4f3633e2021-06-18 11:53:47 -0500407 SDEI_SUPPORT=1 \
Fathi Boudra422bf772019-12-02 11:10:16 +0200408 ZYNQMP_ATF_MEM_BASE=0xFFFC0000 ZYNQMP_ATF_MEM_SIZE=0x00040000 \
409 all
410
Zelalemc9531f82020-08-04 15:37:08 -0500411# Build both for silicon (default) and virtual QEMU platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500412clean_build PLAT=versal $(common_flags)
413clean_build PLAT=versal $(common_flags) VERSAL_PLATFORM=versal_virt
Zelalemc9531f82020-08-04 15:37:08 -0500414
Michal Simek0f135242022-09-20 15:24:56 +0200415# Build Xilinx Versal NET platform
416clean_build PLAT=versal_net $(common_flags)
417
Jayanth Dodderi Chidanand0a2dd1e2022-10-27 11:17:37 +0100418# Build Xilinx Versal NET without Platform Management support
419clean_build PLAT=versal_net $(common_flags) TFA_NO_PM=1
420
Zelalemc9531f82020-08-04 15:37:08 -0500421# Platforms from Allwinner
Andre Przywara3a78c102022-04-26 11:08:54 +0100422clean_build PLAT=sun50i_a64 $(common_flags release) all
423clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_NATIVE=0 all
424clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_SCPI=0 all
425clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_AMEND_DTB=1 all
Andre Przywaracf78a512021-09-03 14:59:38 +0100426clean_build PLAT=sun50i_h6 $(common_flags) all
427clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_NATIVE=0 all
428clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_SCPI=0 all
429clean_build PLAT=sun50i_h616 $(common_flags) all
430clean_build PLAT=sun50i_r329 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500431
432# Platforms from i.MX
433make AARCH32_SP=optee ARCH=aarch32 ARM_ARCH_MAJOR=7 ARM_CORTEX_A7=yes \
434 CROSS_COMPILE=arm-none-eabi- PLAT=warp7 ${TBB_OPTIONS} \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500435 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500436make AARCH32_SP=optee ARCH=aarch32 CROSS_COMPILE=arm-none-eabi- PLAT=picopi \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500437 $(common_flags) all
Ying-Chun Liu (PaulLiu)f6528982021-11-17 17:20:00 +0800438make PLAT=imx8mm $(common_flags) NEED_BL2=yes MEASURED_BOOT=1 \
laurenw-arm8531e702022-06-09 15:32:37 -0500439 MBOOT_EL_HASH_ALG=sha256 ${TBB_OPTIONS} all
Madhukar Pappireddyc3ec06b2022-05-18 11:15:16 -0500440make PLAT=imx8mn $(common_flags) SDEI_SUPPORT=1 all
Ying-Chun Liu (PaulLiu)413e6102021-09-14 00:22:08 +0800441make PLAT=imx8mp $(common_flags) NEED_BL2=yes ${TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500442
Jacky Baib6cecc82021-06-07 09:49:46 +0800443# Due to the limited OCRAM space that can be used for TF-A, build test
444# will report failure caused by too small RAM size, so comment out the
445# build test for imx8mq in CI. It can also resolve the following ticket:
Zelalemc9531f82020-08-04 15:37:08 -0500446# https://developer.trustedfirmware.org/T626
Jacky Baib6cecc82021-06-07 09:49:46 +0800447#make PLAT=imx8mq $(common_flags release) all
Zelalemc9531f82020-08-04 15:37:08 -0500448
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500449make PLAT=imx8qm $(common_flags) all
450make PLAT=imx8qx $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500451
Jacky Baif5e936c2023-12-27 11:11:09 +0800452make PLAT=imx8ulp $(common_flags) all
453
Jacky Bai87091a62023-06-21 16:25:12 +0800454make PLAT=imx93 $(common_flags) all
455
Olivier Deprezbac70192021-04-02 08:55:36 +0200456# Platforms for NXP Layerscape
Jiafei Pane48e56c2021-09-30 10:32:54 +0800457nxp_sb_flags="TRUSTED_BOARD_BOOT=1 CST_DIR=$(pwd) SPD=opteed"
458nxp_sb_fuse_flags="${nxp_sb_flags} FUSE_PROG=1"
459
460# Platform lx2
Olivier Deprezbac70192021-04-02 08:55:36 +0200461make PLAT=lx2160aqds $(common_flags) all
462make PLAT=lx2160ardb $(common_flags) all
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500463
464#CSF Based CoT:
Jiafei Pane48e56c2021-09-30 10:32:54 +0800465clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
466 $nxp_sb_fuse_flags DDR_PHY_BIN_PATH=$(pwd)
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500467
468#X509 Based CoT
Jiafei Pane48e56c2021-09-30 10:32:54 +0800469clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
470 $nxp_sb_flags GENERATE_COT=1 \
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500471 MBEDTLS_DIR=$(pwd)/mbedtls
472
473#BOOT_MODE=emmc and Stack protector
Jiafei Pane48e56c2021-09-30 10:32:54 +0800474clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=emmc \
475 $nxp_sb_fuse_flags ENABLE_STACK_PROTECTOR=strong
476
477# Platform ls1028ardb
478clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor
479clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc
480clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd
481
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800482# ls1028a Secure Boot
Jiafei Pane48e56c2021-09-30 10:32:54 +0800483clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor $nxp_sb_fuse_flags
484clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
485clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
Olivier Deprezbac70192021-04-02 08:55:36 +0200486
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800487# Platform ls1043ardb
488clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor
489clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand
490clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd
491
492# ls1043ardb Secure Boot
493clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
494clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
495clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
496
Jiafei Panbd0c22a2022-01-29 00:04:44 +0800497# ls1046ardb Secure Boot
498clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
499clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
500clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
501
502# ls1046afrwy Secure Boot
503clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
504clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
505
506# ls1046aqds Secure Boot
507clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
508clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
509clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
510clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
511
Jiafei Pan332cd792022-02-24 16:44:48 +0800512# ls1088ardb Secure Boot
513clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
514clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
515
516# ls1088aqds Secure Boot
517clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
518clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
519clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
520
Ghennadi Procopciuc731b0042024-02-01 09:22:26 +0200521# s32g274ardb2
522clean_build PLAT=s32g274ardb2 $(common_flags) all
523
Zelalemc9531f82020-08-04 15:37:08 -0500524# Platforms from Intel
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500525make PLAT=stratix10 $(common_flags) all
526make PLAT=agilex $(common_flags) all
Sieu Mun Tang9081bac2023-05-29 18:08:24 +0800527make PLAT=agilex5 $(common_flags) all
Sieu Mun Tang03b57362022-03-05 01:54:59 +0800528make PLAT=n5x $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500529
530# Platforms from Broadcom
Madhukar Pappireddy97ad2582021-11-15 10:29:23 -0600531clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t \
532 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 DRIVER_I2C_ENABLE=1
533clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t-ns3 \
534 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 USE_USB=yes
Zelalemc9531f82020-08-04 15:37:08 -0500535
536# Platforms from Marvell
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500537make PLAT=a3700 $(common_flags) SCP_BL2=/dev/null CM3_SYSTEM_RESET=1 \
Manish Pandey9ef33c52022-10-25 16:41:49 +0100538 A3720_DB_PM_WAKEUP_SRC=1 HANDLE_EA_EL3_FIRST_NS=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500539
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600540# Source files from mv-ddr-marvell repository are necessary
541# to build below four platforms
Manish Pandey7c1e7452021-11-05 12:54:15 +0000542wget https://downloads.trustedfirmware.org/tf-a/mv-ddr-marvell/mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
543tar -xzf mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600544mv mv-ddr-marvell drivers/marvell/mv_ddr
Zelalemc9531f82020-08-04 15:37:08 -0500545
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600546# These platforms from Marvell have dependency on GCC-6.2.1 toolchain
Pali Rohár8f890402021-07-19 13:48:05 +0200547make PLAT=a80x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200548 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200549make PLAT=a80x0_mcbin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200550 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200551make PLAT=a70x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200552 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200553make PLAT=a70x0_amc DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200554 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Robert Markodf3319e2021-10-20 11:01:12 +0200555make PLAT=a70x0_mochabin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
556 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200557make PLAT=a80x0_puzzle DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200558 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200559make PLAT=t9130 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200560 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500561make PLAT=t9130_cex7_eval DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
562 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500563
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600564# Removing the source files
565rm -rf drivers/marvell/mv_ddr 2> /dev/null
Zelalemc9531f82020-08-04 15:37:08 -0500566
567# Platforms from Meson
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500568make PLAT=gxbb $(common_flags) all
569make PLAT=gxl $(common_flags) all
570make PLAT=g12a $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500571
572# Platforms from Renesas
573# Renesas R-Car D3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500574clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500575 BL33=Makefile LIFEC_DBSC_PROTECT_ENABLE=0 LSI=D3 \
576 MBEDTLS_DIR=$(pwd)/mbedtls PMIC_ROHM_BD9571=0 \
577 RCAR_AVS_SETTING_ENABLE=0 SPD=none RCAR_LOSSY_ENABLE=0 \
578 RCAR_SA0_SIZE=0 RCAR_SYSTEM_SUSPEND=0 TRUSTED_BOARD_BOOT=1
579
580# Renesas R-Car H3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500581clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500582 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3 \
583 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
584 RCAR_DRAM_SPLIT=1 RCAR_GEN3_ULCB=1 SPD=opteed \
585 TRUSTED_BOARD_BOOT=1
586
587# Renesas R-Car H3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500588clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500589 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3N \
590 SPD=opteed TRUSTED_BOARD_BOOT=1
591
592# Renesas R-Car M3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500593clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500594 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3 \
595 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
596 RCAR_DRAM_SPLIT=2 RCAR_GEN3_ULCB=1 SPD=opteed \
597 TRUSTED_BOARD_BOOT=1
598
599# Renesas R-Car M3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500600clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500601 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3N \
602 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
603 RCAR_GEN3_ULCB=1 SPD=opteed TRUSTED_BOARD_BOOT=1
604
605# Renesas R-Car E3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500606clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500607 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=E3 \
608 RCAR_AVS_SETTING_ENABLE=0 RCAR_DRAM_DDR3L_MEMCONF=0 \
609 RCAR_SA0_SIZE=0 SPD=opteed TRUSTED_BOARD_BOOT=1
610
611# Renesas R-Car V3M Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500612clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500613 MBEDTLS_DIR=$(pwd)/mbedtls BL33=Makefile LSI=V3M MACHINE=eagle \
614 PMIC_ROHM_BD9571=0 RCAR_DRAM_SPLIT=0 RCAR_SYSTEM_SUSPEND=0 \
615 AVS_SETTING_ENABLE=0 SPD=none TRUSTED_BOARD_BOOT=1
616
Zelalemf4299672021-01-29 12:52:59 -0600617# Renesas HiHope RZ/G2M development kit
618clean_build PLAT=rzg $(common_flags) \
619 MBEDTLS_DIR=$(pwd)/mbedtls LSI=G2M \
620 RCAR_DRAM_SPLIT=2 RCAR_LOSSY_ENABLE=1 SPD=none
621
Zelalemc9531f82020-08-04 15:37:08 -0500622# Platforms from ST
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100623stm32mp1_common_flags="$(common_flags) \
624 ARCH=aarch32 \
625 ARM_ARCH_MAJOR=7 \
626 CROSS_COMPILE=arm-none-eabi- \
627 ENABLE_STACK_PROTECTOR=strong \
628 PLAT=stm32mp1"
629
Yann Gautiera69cf792021-09-01 11:19:01 +0200630# STM32MP1 SDMMC boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000631make ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200632 BUILD_PLAT=build/stm32mp1-sdmmc/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100633 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200634
Yann Gautier15c45392023-08-21 11:03:33 +0200635# STM32MP1 SDMMC boot BL2 without AARCH32_SP
636make ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
637 BUILD_PLAT=build/stm32mp1-sdmmc/debug \
638 bl2
639
Yann Gautiera69cf792021-09-01 11:19:01 +0200640# STM32MP1 eMMC boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000641make ${stm32mp1_common_flags} STM32MP_EMMC=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200642 BUILD_PLAT=build/stm32mp1-emmc/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100643 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200644
645# STM32MP1 Raw NAND boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000646make ${stm32mp1_common_flags} STM32MP_RAW_NAND=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200647 BUILD_PLAT=build/stm32mp1-nand/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100648 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200649
650# STM32MP1 SPI NAND boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000651make ${stm32mp1_common_flags} STM32MP_SPI_NAND=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200652 BUILD_PLAT=build/stm32mp1-snand/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100653 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200654
655# STM32MP1 SPI NOR boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000656make ${stm32mp1_common_flags} STM32MP_SPI_NOR=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200657 BUILD_PLAT=build/stm32mp1-snor/debug \
Govindraj Raja95f855c2023-03-01 13:11:42 +0000658 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200659
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100660# STM32MP1 UART boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000661make ${stm32mp1_common_flags} STM32MP_UART_PROGRAMMER=1 \
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100662 BUILD_PLAT=build/stm32mp1-uart/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100663 AARCH32_SP=sp_min bl2 bl32
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100664
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200665# STM32MP1 USB boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000666make ${stm32mp1_common_flags} STM32MP_USB_PROGRAMMER=1 \
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200667 BUILD_PLAT=build/stm32mp1-usb/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100668 AARCH32_SP=sp_min bl2 bl32
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200669
Lionel Debieve8f464c02022-10-13 09:25:45 +0200670# STM32MP1 TBBR
Govindraj Raja95f855c2023-03-01 13:11:42 +0000671make ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
Yann Gautier741e8492022-11-14 19:04:27 +0100672 BUILD_PLAT=build/stm32mp1-sdmmc-tbbr/debug \
Lionel Debieve8f464c02022-10-13 09:25:45 +0200673 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100674 AARCH32_SP=sp_min bl2 bl32
Lionel Debieve8f464c02022-10-13 09:25:45 +0200675
Govindraj Raja95f855c2023-03-01 13:11:42 +0000676stm32mp13_common_flags="${stm32mp1_common_flags} \
677 AARCH32_SP=optee \
678 STM32MP13=1"
679
Yann Gautier773c5502022-03-10 17:24:47 +0100680# STM32MP13 SDMMC boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000681make ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100682 BUILD_PLAT=build/stm32mp1-mp13-sdmmc/debug bl2
Yann Gautier773c5502022-03-10 17:24:47 +0100683
Lionel Debieve8f464c02022-10-13 09:25:45 +0200684# STM32MP13 TBBR
Govindraj Raja95f855c2023-03-01 13:11:42 +0000685make ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Lionel Debieve8f464c02022-10-13 09:25:45 +0200686 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100687 BUILD_PLAT=build/stm32mp1-mp13-sdmmc-tbbr/debug bl2
Lionel Debieve8f464c02022-10-13 09:25:45 +0200688
Yann Gautiera66e5012022-12-13 13:52:35 +0100689# STM32MP13 TBBR DECRYPTION AES GCM
Govindraj Raja95f855c2023-03-01 13:11:42 +0000690make ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Yann Gautiera66e5012022-12-13 13:52:35 +0100691 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
692 DECRYPTION_SUPPORT=aes_gcm ENCRYPT_BL32=1 \
693 BUILD_PLAT=build/stm32mp1-mp13-sdmmc-tbbr-dec/debug bl2
694
Yann Gautiere9da1e22023-08-11 14:50:04 +0200695stm32mp2_common_flags="$(common_flags) \
696 ARCH=aarch64 \
697 CROSS_COMPILE=aarch64-none-elf- \
698 PLAT=stm32mp2"
699
700# STM32MP25 SDMMC boot
701make ${stm32mp2_common_flags} STM32MP_SDMMC=1 \
702 SPD=opteed STM32MP_DDR4_TYPE=1 \
703 BUILD_PLAT=build/stm32mp2-mp25-sdmmc/debug
704
Yann Gautier83dc8702024-03-19 15:07:26 +0100705# STM32MP25 USB boot
706make ${stm32mp2_common_flags} STM32MP_USB_PROGRAMMER=1 \
707 SPD=opteed STM32MP_DDR4_TYPE=1 \
Yann Gautier63ee8832024-03-20 13:49:15 +0100708 BUILD_PLAT=build/stm32mp2-mp25-usb/debug
Yann Gautier83dc8702024-03-19 15:07:26 +0100709
Zelalemc9531f82020-08-04 15:37:08 -0500710# Platforms from TI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500711make PLAT=k3 $(common_flags) all
Hari Nagalladadd89f2022-08-30 12:10:00 -0500712make PLAT=k3 TARGET_BOARD=j784s4 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500713
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500714clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS}
Zelalemc9531f82020-08-04 15:37:08 -0500715# Use GICV3 driver
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500716clean_build PLAT=qemu $(common_flags) QEMU_USE_GIC_DRIVER=QEMU_GICV3 \
Zelalemc9531f82020-08-04 15:37:08 -0500717 ENABLE_STACK_PROTECTOR=strong
Dongjiu Geng72819ee2023-06-16 18:48:57 +0800718# Use GICV3 driver with SDEI support
719clean_build PLAT=qemu $(common_flags) QEMU_USE_GIC_DRIVER=QEMU_GICV3 \
720 ENABLE_STACK_PROTECTOR=strong SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Zelalemc9531f82020-08-04 15:37:08 -0500721# Use encrypted FIP feature.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500722clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500723 BL32_RAM_LOCATION=tdram DECRYPTION_SUPPORT=aes_gcm ENCRYPT_BL31=1 \
724 ENCRYPT_BL32=1 FW_ENC_STATUS=0 SPD=opteed
Jens Wiklander1a9c2be2021-11-26 09:56:55 +0100725# QEMU with SPMD support
726clean_build PLAT=qemu $(common_flags) BL32=Makefile \
727 BL32_RAM_LOCATION=tdram ARM_BL31_IN_DRAM=1 \
728 SPD=spmd CTX_INCLUDE_EL2_REGS=0 SPMD_SPM_AT_SEL2=0 SPMC_OPTEE=1
Ruchika Gupta86e7f682022-04-12 10:25:46 +0530729# Measured Boot
laurenw-arm8531e702022-06-09 15:32:37 -0500730clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} MBOOT_EL_HASH_ALG=sha256 MEASURED_BOOT=1
Raymond Mao7681ba02023-08-10 14:05:44 -0700731# Transfer List
732clean_build PLAT=qemu $(common_flags) TRANSFER_LIST=1
Zelalemc9531f82020-08-04 15:37:08 -0500733
Jean-Philippe Bruckerb586eee2023-11-02 18:13:30 +0000734# FEAT_RME
735clean_build PLAT=qemu $(common_flags) ENABLE_RME=1 \
736 QEMU_USE_GIC_DRIVER=QEMU_GICV3
737
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500738clean_build PLAT=qemu_sbsa $(common_flags)
Fathi Boudra422bf772019-12-02 11:10:16 +0200739
Zelalemd86e8762020-08-21 18:24:28 -0500740# QEMU with SPM support
741clean_build PLAT=qemu_sbsa $(common_flags) BL32=Makefile SPM_MM=1 \
Paul Sokolovskycf9fe862023-01-02 16:22:21 +0300742 EL3_EXCEPTION_HANDLING=1 ENABLE_SME_FOR_NS=0 ENABLE_SVE_FOR_NS=0
Zelalemd86e8762020-08-21 18:24:28 -0500743
Fathi Boudra422bf772019-12-02 11:10:16 +0200744# For hikey enable PMF to include all files in the platform port
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500745make PLAT=hikey $(common_flags) ${TBB_OPTIONS} ENABLE_PMF=1 all
746make PLAT=hikey960 $(common_flags) ${TBB_OPTIONS} all
Lukas Haneld0752392022-10-13 11:13:19 +0200747make PLAT=hikey960 $(common_flags) ${TBB_OPTIONS} SPD=spmd SPMC_AT_EL3=1 \
748 SPMD_SPM_AT_SEL2=0 BL32=optee PLAT_SP_MANIFEST_DTS=foo NEED_FDT=no all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500749make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200750
Zelalemc9531f82020-08-04 15:37:08 -0500751# Platforms from Socionext
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500752clean_build PLAT=uniphier $(common_flags) ${TBB_OPTIONS} SPD=tspd
753clean_build PLAT=uniphier $(common_flags) FIP_GZIP=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200754
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500755clean_build PLAT=synquacer $(common_flags) SPM_MM=1 \
Jassi Brar86080922022-06-27 14:16:34 -0500756 RESET_TO_BL31=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0 \
757 PRELOADED_BL33_BASE=0x0
Zelalemc9531f82020-08-04 15:37:08 -0500758
759# Support for SCP Message Interface protocol with platform specific drivers
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500760clean_build PLAT=synquacer $(common_flags) \
Jassi Brar86080922022-06-27 14:16:34 -0500761 RESET_TO_BL31=1 PRELOADED_BL33_BASE=0x0 SQ_USE_SCMI_DRIVER=1
Zelalemc9531f82020-08-04 15:37:08 -0500762
Jassi Brarb8c7ca02022-06-27 14:22:10 -0500763# Support for BL2 and TBBR
764clean_build PLAT=synquacer $(common_flags) \
765 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
766 SQ_USE_SCMI_DRIVER=1 SPD=opteed all
767
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500768make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200769
Zelalemc9531f82020-08-04 15:37:08 -0500770# Raspberry Pi Platforms
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500771make PLAT=rpi3 $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500772 ENABLE_STACK_PROTECTOR=strong PRELOADED_BL33_BASE=0xDEADBEEF all
Andre Przywarae917ec82021-09-03 15:01:30 +0100773clean_build PLAT=rpi4 $(common_flags) SMC_PCI_SUPPORT=1 all
Mario Bălănicăea4da5e2024-03-08 20:09:24 +0200774clean_build PLAT=rpi5 $(common_flags) SMC_PCI_SUPPORT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200775
Zelalemc9531f82020-08-04 15:37:08 -0500776# A113D (AXG) platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500777clean_build PLAT=axg $(common_flags) SPD=opteed
778clean_build PLAT=axg $(common_flags) AML_USE_ATOS=1
Zelalemc9531f82020-08-04 15:37:08 -0500779
Stephan Gerhold141a7662021-12-07 20:42:14 +0100780# QTI MSM8916 platform
Stephan Gerhold3b3976f2023-04-17 16:27:11 +0200781clean_build PLAT=mdm9607 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
782 ARCH=aarch32 AARCH32_SP=sp_min
783clean_build PLAT=msm8909 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
784 ARCH=aarch32 AARCH32_SP=sp_min
Stephan Gerhold141a7662021-12-07 20:42:14 +0100785clean_build PLAT=msm8916 $(common_flags)
Manish V Badarkhec540e622023-06-28 17:56:40 +0100786clean_build PLAT=msm8916 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
787 ARCH=aarch32 AARCH32_SP=sp_min
Stephan Gerhold998f0d62023-04-17 16:22:52 +0200788clean_build PLAT=msm8916 $(common_flags) SPD=tspd
Stephan Gerhold3b3976f2023-04-17 16:27:11 +0200789clean_build PLAT=msm8939 $(common_flags)
790clean_build PLAT=msm8939 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
791 ARCH=aarch32 AARCH32_SP=sp_min
792clean_build PLAT=msm8939 $(common_flags) SPD=tspd
Stephan Gerhold141a7662021-12-07 20:42:14 +0100793
Chia-Wei Wang7dcb0d02023-06-09 09:52:52 +0800794# Platforms from Aspeed
795clean_build PLAT=ast2700 $(common_flags) SPD=opteed
796
rutigl@gmail.com86cfcf92023-03-21 10:10:11 +0200797# Nuvoton npcm845x platform
798make PLAT=npcm845x $(common_flags) all SPD=opteed
799
Harrison Mutaiee958c12023-09-06 12:16:21 +0100800if [[ "$rc" -gt 0 ]]; then
801 echo "ERROR: tc-cov-make failed with $error_count failures"
802 exit $rc
803fi
804
Fathi Boudra422bf772019-12-02 11:10:16 +0200805cd ..