blob: a7828f31ce5679b7dfae82e87a47742ff4965f3f [file] [log] [blame]
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -05001#!/usr/bin/env bash
Fathi Boudra422bf772019-12-02 11:10:16 +02002#
Govindraj Raja95f855c2023-03-01 13:11:42 +00003# Copyright (c) 2019-2023, Arm Limited. All rights reserved.
Fathi Boudra422bf772019-12-02 11:10:16 +02004#
5# SPDX-License-Identifier: BSD-3-Clause
6#
7
8#
9# This script builds the TF in different configs.
10# Rather than telling cov-build to build TF using a simple 'make all' command,
11# the goal here is to combine several build flags to analyse more of our source
12# code in a single 'build'. The Coverity Scan service does not have the notion
13# of separate types of build - there is just one linear sequence of builds in
14# the project history.
15#
16
17# Bail out as soon as an error is encountered.
18set -e
19
20TF_SOURCES=$1
21if [ ! -d "$TF_SOURCES" ]; then
22 echo "ERROR: '$TF_SOURCES' does not exist or is not a directory"
23 echo "Usage: $(basename "$0") <trusted-firmware-directory>"
24 exit 1
25fi
26
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050027containing_dir="$(readlink -f "$(dirname "$0")/")"
28. $containing_dir/common-def.sh
29
Fathi Boudra422bf772019-12-02 11:10:16 +020030# Get mbed TLS library code to build Trusted Firmware with Trusted Board Boot
31# support. The version of mbed TLS to use here must be the same as when
32# building TF in the usual context.
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050033if [ ! -d "$MBED_TLS_DIR" ]; then
34 git clone -q --depth 1 -b "$MBED_TLS_SOURCES_TAG" "$MBED_TLS_URL_REPO" "$MBED_TLS_DIR"
Fathi Boudra422bf772019-12-02 11:10:16 +020035fi
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050036
Fathi Boudra422bf772019-12-02 11:10:16 +020037cd "$TF_SOURCES"
38
39# Clean TF source dir to make sure we don't analyse temporary files.
40make distclean
41
42#
43# Build TF in different configurations to get as much coverage as possible
44#
45
Fathi Boudra422bf772019-12-02 11:10:16 +020046#
47# FVP platform
48# We'll use the following flags for all FVP builds.
49#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050050fvp_common_flags="$(common_flags) PLAT=fvp"
Fathi Boudra422bf772019-12-02 11:10:16 +020051
52# Try all possible SPDs.
53clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd
54clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd TSP_INIT_ASYNC=1 \
55 TSP_NS_INTR_ASYNC_PREEMPT=1
56clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed
57clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tlkd
Florian Lugou70a76c02022-03-25 09:51:42 +010058clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=pncd SPD_PNCD_NS_IRQ=126 SPD_PNCD_S_IRQ=15
Fathi Boudra422bf772019-12-02 11:10:16 +020059
Zelalemc9531f82020-08-04 15:37:08 -050060# Dualroot chain of trust.
61clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tspd COT=dualroot
62
laurenw-armf48e9d22022-04-22 11:30:13 -050063# FEAT_RME with CCA chain of trust.
Sandrine Bailleuxe30bd0c2022-08-31 14:49:17 +020064#
65# Note that we override PLAT_RSS_NOT_SUPPORTED build flag (which defaults to 1
66# on the Base AEM FVP) just to analyse the RSS communication driver code through
67# Coverity. In reality, RSS is not supported on FVP right now (or on any other
68# upstream platform, for that matter) so the resulting firmware would not be
69# functional.
Manish V Badarkhe21402bb2023-03-18 12:39:33 +000070clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} USE_ROMLIB=1 \
Sandrine Bailleuxe30bd0c2022-08-31 14:49:17 +020071 ENABLE_RME=1 MEASURED_BOOT=1 PLAT_RSS_NOT_SUPPORTED=0
laurenw-armf48e9d22022-04-22 11:30:13 -050072
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050073clean_build $fvp_common_flags SPD=trusty
74clean_build $fvp_common_flags SPD=trusty TRUSTY_SPD_WITH_GENERIC_SERVICES=1
Fathi Boudra422bf772019-12-02 11:10:16 +020075
76# SDEI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050077clean_build $fvp_common_flags SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Fathi Boudra422bf772019-12-02 11:10:16 +020078
Zelalemc9531f82020-08-04 15:37:08 -050079# SDEI with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050080clean_build $fvp_common_flags SDEI_IN_FCONF=1 SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Zelalemc9531f82020-08-04 15:37:08 -050081
Zelalem4f3633e2021-06-18 11:53:47 -050082# PCI Service
83clean_build $fvp_common_flags SMC_PCI_SUPPORT=1
84
Zelalemc9531f82020-08-04 15:37:08 -050085# Secure interrupt descriptors with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050086clean_build $fvp_common_flags SEC_INT_DESC_IN_FCONF=1
Zelalemc9531f82020-08-04 15:37:08 -050087
Fathi Boudra422bf772019-12-02 11:10:16 +020088# Without coherent memory
89clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd USE_COHERENT_MEM=0
90
91# Using PSCI extended State ID format rather than the original format
92clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd PSCI_EXTENDED_STATE_ID=1 \
93 ARM_RECOM_STATE_ID_ENC=1
94
95# Alternative boot flows (This changes some of the platform initialisation code)
96clean_build $fvp_common_flags EL3_PAYLOAD=0x80000000
97clean_build $fvp_common_flags PRELOADED_BL33_BASE=0x80000000
98
99# Using the SP804 timer instead of the Generic Timer
100clean_build $fvp_common_flags FVP_USE_SP804_TIMER=1
101
102# Using the CCN driver and multi cluster topology
103clean_build $fvp_common_flags FVP_CLUSTER_COUNT=4
104
105# PMF
106clean_build $fvp_common_flags ENABLE_PMF=1
107
108# stack protector
109clean_build $fvp_common_flags ENABLE_STACK_PROTECTOR=strong
110
111# AArch32 build
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500112clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200113 ARCH=aarch32 AARCH32_SP=sp_min \
114 RESET_TO_SP_MIN=1 PRELOADED_BL33_BASE=0x80000000
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500115clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200116 ARCH=aarch32 AARCH32_SP=sp_min
117
118# Xlat tables lib version 1 (AArch64 and AArch32)
119clean_build $fvp_common_flags ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500120clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200121 ARCH=aarch32 AARCH32_SP=sp_min ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
122
Zelalemc9531f82020-08-04 15:37:08 -0500123# SPM support based on Management Mode Interface Specification
Manish Pandeyaa9a03b2021-11-17 10:03:17 +0000124clean_build $fvp_common_flags SPM_MM=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0
Fathi Boudra422bf772019-12-02 11:10:16 +0200125
Zelalemc9531f82020-08-04 15:37:08 -0500126# SPM support with TOS(optee) as SPM sitting at S-EL1
127clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0
128
Shruti Gupta8cc89b92022-08-09 12:23:46 +0100129# SPM support with SPM at EL3 and TSP at S-EL1
130clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 CTX_INCLUDE_EL2_REGS=0 EL3_EXCEPTION_HANDLING=0 \
131 SPD=spmd SPMD_SPM_AT_SEL2=0 SPMC_AT_EL3=1 \
132 ARM_SPMC_MANIFEST_DTS=plat/arm/board/fvp/fdts/fvp_tsp_sp_manifest.dts
133
Zelalemc9531f82020-08-04 15:37:08 -0500134# SPM support with Secure hafnium as SPM sitting at S-EL2
135# SP_LAYOUT_FILE is used only during FIP creation but build won't progress
136# if we have NULL value to it, so passing a dummy string.
137clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=1 ARM_ARCH_MINOR=4 \
Max Shvetsov44d2a702021-02-18 16:41:45 +0000138 CTX_INCLUDE_EL2_REGS=1 SP_LAYOUT_FILE=dummy
Fathi Boudra422bf772019-12-02 11:10:16 +0200139
Marc Bonnici502fdaa2022-01-10 12:38:23 +0000140# SPM support with SPM sitting at EL3
141clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0 SPMC_AT_EL3=1
142
Fathi Boudra422bf772019-12-02 11:10:16 +0200143#BL2 at EL3 support
Maksims Svecovs7a0da522023-03-06 16:28:27 +0000144clean_build $fvp_common_flags RESET_TO_BL2=1
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500145clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Maksims Svecovs7a0da522023-03-06 16:28:27 +0000146 ARCH=aarch32 AARCH32_SP=sp_min RESET_TO_BL2=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200147
Zelalemc9531f82020-08-04 15:37:08 -0500148# RAS Extension Support
Manish Pandeyc1fa25b2023-02-16 17:35:36 +0000149clean_build $fvp_common_flags EL3_EXCEPTION_HANDLING=1 ENABLE_FEAT_RAS=1 \
150 RAS_FFH_SUPPORT=1 FAULT_INJECTION_SUPPORT=1 HANDLE_EA_EL3_FIRST_NS=1 \
Manish Pandey010e9b42023-04-24 15:49:27 +0100151 SDEI_SUPPORT=1 PLATFORM_TEST_RAS_FFH=1
Zelalemc9531f82020-08-04 15:37:08 -0500152
Manish Pandeyfd4c6b72023-04-24 10:29:52 +0100153# EA handled in EL3 first
154clean_build $fvp_common_flags HANDLE_EA_EL3_FIRST_NS=1 PLATFORM_TEST_EA_FFH=1
155
Zelalemc9531f82020-08-04 15:37:08 -0500156# Hardware Assisted Coherency(DynamIQ)
157clean_build $fvp_common_flags FVP_CLUSTER_COUNT=1 FVP_MAX_CPUS_PER_CLUSTER=8 \
158 HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0
159
160# Pointer Authentication Support
161clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 \
162 ARM_ARCH_MINOR=5 EL3_EXCEPTION_HANDLING=1 BRANCH_PROTECTION=1 SDEI_SUPPORT=1 SPD=tspd TSP_NS_INTR_ASYNC_PREEMPT=1
163
164# Undefined Behaviour Sanitizer
165# Building with UBSAN SANITIZE_UB=on increases the executable size.
166# Hence it is only properly supported in bl31 with RESET_TO_BL31 enabled
167make $fvp_common_flags clean
168make $fvp_common_flags SANITIZE_UB=on RESET_TO_BL31=1 bl31
169
170# debugfs feature
171clean_build $fvp_common_flags DEBUG=1 USE_DEBUGFS=1
172
173# MPAM feature
174clean_build $fvp_common_flags ENABLE_MPAM_FOR_LOWER_ELS=1
175
176# Using GICv3.1 driver with extended PPI and SPI range
177clean_build $fvp_common_flags GIC_EXT_INTID=1
178
179# Using GICv4 features with extended PPI and SPI range
180clean_build $fvp_common_flags GIC_ENABLE_V4_EXTN=1 GIC_EXT_INTID=1
181
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100182# Measured Boot
laurenw-arm8531e702022-06-09 15:32:37 -0500183clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} MBOOT_EL_HASH_ALG=sha256 MEASURED_BOOT=1 USE_ROMLIB=1
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100184
Manish V Badarkhef43e3f52022-06-21 20:37:25 +0100185# DRTM
186clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} TPM_HASH_ALG=sha256 DRTM_SUPPORT=1 USE_ROMLIB=1
187
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100188# CoT descriptors in device tree
Manish V Badarkhe81102d12020-10-05 08:02:30 +0100189clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} COT_DESC_IN_DTB=1 USE_ROMLIB=1
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100190
Manish V Badarkhe107c8e32021-08-02 19:49:32 +0100191# PSA FWU support
192clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_GPT_SUPPORT=1 PSA_FWU_SUPPORT=1 USE_ROMLIB=1
193
johpow01153c8b22021-11-03 14:38:36 -0500194# SME and HCX features
195clean_build $fvp_common_flags ENABLE_SME_FOR_NS=1 ENABLE_FEAT_HCX=1
196
Jayanth Dodderi Chidanand41edd012023-01-12 14:50:34 +0000197# SME2
198clean_build $fvp_common_flags ENABLE_SME2_FOR_NS=1 ENABLE_SME_FOR_NS=1 ENABLE_FEAT_HCX=1
199
Jayanth Dodderi Chidanand84da1962022-04-11 11:38:44 +0100200# Architectural Feature Detection mechanism
201clean_build $fvp_common_flags FEATURE_DETECTION=1
202
Manish Pandeye3561fd2023-01-05 10:46:25 +0000203# RNG trap feature
204clean_build $fvp_common_flags ENABLE_FEAT_RNG=1 ENABLE_FEAT_RNG_TRAP=1
205
Govindraj Rajab06f9c82023-05-09 14:46:38 -0500206# OPTEE_ALLOW_SMC_LOAD feature - Disable debug build for this option as its causing bl31 image overflow
207clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed OPTEE_ALLOW_SMC_LOAD=1 PLAT_XLAT_TABLES_DYNAMIC=1 DEBUG=0
Jeffrey Kardatzke09e18e22023-01-25 12:24:13 -0800208
Fathi Boudra422bf772019-12-02 11:10:16 +0200209#
210# Juno platform
211# We'll use the following flags for all Juno builds.
212#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500213juno_common_flags="$(common_flags) PLAT=juno"
Fathi Boudra422bf772019-12-02 11:10:16 +0200214clean_build $juno_common_flags SPD=tspd ${ARM_TBB_OPTIONS}
215clean_build $juno_common_flags EL3_PAYLOAD=0x80000000
Madhukar Pappireddydcb31f62021-05-06 11:36:36 -0500216clean_build $juno_common_flags ENABLE_STACK_PROTECTOR=strong ARM_ETHOSN_NPU_DRIVER=1
Mikael Olssoncd8c7822023-02-28 17:30:44 +0100217clean_build $juno_common_flags ${ARM_TBB_OPTIONS} ENABLE_STACK_PROTECTOR=strong ARM_ETHOSN_NPU_DRIVER=1 ARM_ETHOSN_NPU_TZMP1=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200218clean_build $juno_common_flags CSS_USE_SCMI_SDS_DRIVER=0
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500219
Leonardo Sandoval5163b562020-11-20 17:17:59 -0600220clean_build $juno_common_flags SPD=tspd ${ARM_TBB_OPTIONS} ARM_CRYPTOCELL_INTEG=1 CCSBROM_LIB_PATH=${CRYPTOCELL_LIB_PATH} KEY_SIZE=2048
Fathi Boudra422bf772019-12-02 11:10:16 +0200221
Jayanth Dodderi Chidanand055394a2022-10-19 09:20:20 +0100222# TRNG Service
223clean_build $juno_common_flags TRNG_SUPPORT=1
224
Fathi Boudra422bf772019-12-02 11:10:16 +0200225#
Fathi Boudra422bf772019-12-02 11:10:16 +0200226# System Guidance for Infrastructure platform RD-E1Edge
227#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500228make $(common_flags) PLAT=rde1edge ${ARM_TBB_OPTIONS} CSS_SGI_CHIP_COUNT=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500229
230#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530231# Reference Design platform RD-V1
Zelalemc9531f82020-08-04 15:37:08 -0500232#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530233make $(common_flags) PLAT=rdv1 ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500234
235#
Aditya Angadi61c54762021-01-04 09:30:52 +0530236# Reference Design platform RD-V1-MC
Zelalemc9531f82020-08-04 15:37:08 -0500237#
Aditya Angadi61c54762021-01-04 09:30:52 +0530238make $(common_flags) PLAT=rdv1mc ${ARM_TBB_OPTIONS} CSS_SGI_CHIP_COUNT=4 all
Zelalemc9531f82020-08-04 15:37:08 -0500239
240#
Vijayenthiran Subramaniama66de332020-11-23 14:20:14 +0530241# Reference Design Platform RD-N2
242#
243make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} all
244
245#
Zelalemc9531f82020-08-04 15:37:08 -0500246# Neoverse N1 SDP platform
247#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500248make $(common_flags) PLAT=n1sdp ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500249
250#
251# FVP VE platform
252#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500253make $(common_flags) PLAT=fvp_ve AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500254 CROSS_COMPILE=arm-none-eabi- ARM_ARCH_MAJOR=7 \
255 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
256 FVP_HW_CONFIG_DTS=fdts/fvp-ve-Cortex-A5x1.dts all
257
258#
259# A5 DesignStart Platform
260#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500261make $(common_flags) PLAT=a5ds AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500262 ARM_ARCH_MAJOR=7 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
263 CROSS_COMPILE=arm-none-eabi- FVP_HW_CONFIG_DTS=fdts/a5ds.dts
264
265#
266# Corstone700 Platform
267#
268
269corstone700_common_flags="CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500270 $(common_flags) \
Zelalemc9531f82020-08-04 15:37:08 -0500271 PLAT=corstone700 \
272 ARCH=aarch32 \
273 RESET_TO_SP_MIN=1 \
274 AARCH32_SP=sp_min \
275 ARM_LINUX_KERNEL_AS_BL33=0 \
276 ARM_PRELOADED_DTB_BASE=0x80400000 \
277 ENABLE_PIE=1 \
Zelalemc9531f82020-08-04 15:37:08 -0500278 ENABLE_STACK_PROTECTOR=all \
279 all"
280
281echo "Info: Building Corstone700 FVP ..."
282
283make TARGET_PLATFORM=fvp ${corstone700_common_flags}
284
285echo "Info: Building Corstone700 FPGA ..."
286
287make TARGET_PLATFORM=fpga ${corstone700_common_flags}
288
289#
290# Arm internal FPGA port
291#
Andre Przywara13361b62022-04-26 11:16:55 +0100292make PLAT=arm_fpga $(common_flags release) \
293 FPGA_PRELOADED_DTB_BASE=0x88000000 PRELOADED_BL33_BASE=0x82080000 all
Zelalemc9531f82020-08-04 15:37:08 -0500294
295#
Usama Arifcba711d2021-08-04 15:53:42 +0100296# Total Compute platforms
Zelalemc9531f82020-08-04 15:37:08 -0500297#
Usama Arifcba711d2021-08-04 15:53:42 +0100298make $(common_flags) PLAT=tc TARGET_PLATFORM=0 ${ARM_TBB_OPTIONS} all
299make $(common_flags) PLAT=tc TARGET_PLATFORM=1 ${ARM_TBB_OPTIONS} all
Tamas Banaf5a6632022-09-21 16:02:39 +0200300make $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} MEASURED_BOOT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200301
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530302#
303# Morello platform
304#
Chandni Cherukuricbd45962021-12-12 13:37:33 +0530305clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=fvp ${ARM_TBB_OPTIONS}
306clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=soc ${ARM_TBB_OPTIONS}
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530307
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100308#
Vishnu Banavath2cb72b32022-01-20 14:27:55 +0000309# corstone1000 Platform
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100310#
311
312make $(common_flags) \
Vishnu Banavath2cb72b32022-01-20 14:27:55 +0000313 PLAT=corstone1000 \
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100314 SPD=spmd \
315 TARGET_PLATFORM=fpga \
316 ENABLE_STACK_PROTECTOR=strong \
317 ENABLE_PIE=1 \
Maksims Svecovs7a0da522023-03-06 16:28:27 +0000318 RESET_TO_BL2=1 \
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100319 SPMD_SPM_AT_SEL2=0 \
320 ${ARM_TBB_OPTIONS} \
321 CREATE_KEYS=1 \
322 COT=tbbr \
323 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
324 bl2 \
325 bl31
326
johpow01aac58582021-10-05 16:51:34 -0500327#
328# FVP-R platform
329#
330clean_build $(common_flags) PLAT=fvp_r ${ARM_TBB_OPTIONS} ENABLE_STACK_PROTECTOR=all
331
Fathi Boudra422bf772019-12-02 11:10:16 +0200332# Partners' platforms.
333# Enable as many features as possible.
334# We don't need to clean between each build here because we only do one build
335# per platform so we don't hit the build flags dependency problem.
Fathi Boudra422bf772019-12-02 11:10:16 +0200336
Manish Pandey9c0ee742021-07-08 09:55:59 +0100337# Platforms from Mediatek
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500338make PLAT=mt8173 $(common_flags) all
339make PLAT=mt8183 $(common_flags) all
Rex-BC Chen946cace2021-11-17 10:15:42 +0800340make PLAT=mt8186 $(common_flags) COREBOOT=1 all
Bo-Chen Chen4d63afd2022-08-30 16:34:57 +0800341make PLAT=mt8188 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500342make PLAT=mt8192 $(common_flags) COREBOOT=1 all
Manish Pandey9c0ee742021-07-08 09:55:59 +0100343make PLAT=mt8195 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500344
345# Platforms from Qualcomm
346make PLAT=sc7180 $(common_flags) COREBOOT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200347
Zelalemc9531f82020-08-04 15:37:08 -0500348make PLAT=rk3288 CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500349 $(common_flags) ARCH=aarch32 AARCH32_SP=sp_min all
Madhukar Pappireddyd491ad02020-12-03 10:37:05 -0600350make PLAT=rk3368 $(common_flags) COREBOOT=1 \
351 ENABLE_STACK_PROTECTOR=strong all
352make PLAT=rk3399 $(common_flags) COREBOOT=1 PLAT_RK_DP_HDCP=1 \
353 ENABLE_STACK_PROTECTOR=strong all
354make PLAT=rk3328 $(common_flags) COREBOOT=1 PLAT_RK_SECURE_DDR_MINILOADER=1 \
355 ENABLE_STACK_PROTECTOR=strong all
356make PLAT=px30 $(common_flags) PLAT_RK_SECURE_DDR_MINILOADER=1 \
357 ENABLE_STACK_PROTECTOR=strong all
Fathi Boudra422bf772019-12-02 11:10:16 +0200358
359# Although we do several consecutive builds for the Tegra platform below, we
360# don't need to clean between each one because the Tegra makefiles specify
361# a different build directory per SoC.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500362make PLAT=tegra TARGET_SOC=t210 $(common_flags) all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500363make PLAT=tegra TARGET_SOC=t186 $(common_flags) all
364make PLAT=tegra TARGET_SOC=t194 $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200365
366# For the Xilinx platform, artificially increase the extents of BL31 memory
367# (using the platform-specific build options ZYNQMP_ATF_MEM_{BASE,SIZE}).
368# If we keep the default values, BL31 doesn't fit when it is built with all
369# these build flags.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500370make PLAT=zynqmp $(common_flags) \
Fathi Boudra422bf772019-12-02 11:10:16 +0200371 RESET_TO_BL31=1 SPD=tspd \
Zelalem4f3633e2021-06-18 11:53:47 -0500372 SDEI_SUPPORT=1 \
Fathi Boudra422bf772019-12-02 11:10:16 +0200373 ZYNQMP_ATF_MEM_BASE=0xFFFC0000 ZYNQMP_ATF_MEM_SIZE=0x00040000 \
374 all
375
Zelalemc9531f82020-08-04 15:37:08 -0500376# Build both for silicon (default) and virtual QEMU platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500377clean_build PLAT=versal $(common_flags)
378clean_build PLAT=versal $(common_flags) VERSAL_PLATFORM=versal_virt
Zelalemc9531f82020-08-04 15:37:08 -0500379
Michal Simek0f135242022-09-20 15:24:56 +0200380# Build Xilinx Versal NET platform
381clean_build PLAT=versal_net $(common_flags)
382
Jayanth Dodderi Chidanand0a2dd1e2022-10-27 11:17:37 +0100383# Build Xilinx Versal NET without Platform Management support
384clean_build PLAT=versal_net $(common_flags) TFA_NO_PM=1
385
Zelalemc9531f82020-08-04 15:37:08 -0500386# Platforms from Allwinner
Andre Przywara3a78c102022-04-26 11:08:54 +0100387clean_build PLAT=sun50i_a64 $(common_flags release) all
388clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_NATIVE=0 all
389clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_SCPI=0 all
390clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_AMEND_DTB=1 all
Andre Przywaracf78a512021-09-03 14:59:38 +0100391clean_build PLAT=sun50i_h6 $(common_flags) all
392clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_NATIVE=0 all
393clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_SCPI=0 all
394clean_build PLAT=sun50i_h616 $(common_flags) all
395clean_build PLAT=sun50i_r329 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500396
397# Platforms from i.MX
398make AARCH32_SP=optee ARCH=aarch32 ARM_ARCH_MAJOR=7 ARM_CORTEX_A7=yes \
399 CROSS_COMPILE=arm-none-eabi- PLAT=warp7 ${TBB_OPTIONS} \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500400 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500401make AARCH32_SP=optee ARCH=aarch32 CROSS_COMPILE=arm-none-eabi- PLAT=picopi \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500402 $(common_flags) all
Ying-Chun Liu (PaulLiu)f6528982021-11-17 17:20:00 +0800403make PLAT=imx8mm $(common_flags) NEED_BL2=yes MEASURED_BOOT=1 \
laurenw-arm8531e702022-06-09 15:32:37 -0500404 MBOOT_EL_HASH_ALG=sha256 ${TBB_OPTIONS} all
Madhukar Pappireddyc3ec06b2022-05-18 11:15:16 -0500405make PLAT=imx8mn $(common_flags) SDEI_SUPPORT=1 all
Ying-Chun Liu (PaulLiu)413e6102021-09-14 00:22:08 +0800406make PLAT=imx8mp $(common_flags) NEED_BL2=yes ${TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500407
Jacky Baib6cecc82021-06-07 09:49:46 +0800408# Due to the limited OCRAM space that can be used for TF-A, build test
409# will report failure caused by too small RAM size, so comment out the
410# build test for imx8mq in CI. It can also resolve the following ticket:
Zelalemc9531f82020-08-04 15:37:08 -0500411# https://developer.trustedfirmware.org/T626
Jacky Baib6cecc82021-06-07 09:49:46 +0800412#make PLAT=imx8mq $(common_flags release) all
Zelalemc9531f82020-08-04 15:37:08 -0500413
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500414make PLAT=imx8qm $(common_flags) all
415make PLAT=imx8qx $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500416
Olivier Deprezbac70192021-04-02 08:55:36 +0200417# Platforms for NXP Layerscape
Jiafei Pane48e56c2021-09-30 10:32:54 +0800418nxp_sb_flags="TRUSTED_BOARD_BOOT=1 CST_DIR=$(pwd) SPD=opteed"
419nxp_sb_fuse_flags="${nxp_sb_flags} FUSE_PROG=1"
420
421# Platform lx2
Olivier Deprezbac70192021-04-02 08:55:36 +0200422make PLAT=lx2160aqds $(common_flags) all
423make PLAT=lx2160ardb $(common_flags) all
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500424
425#CSF Based CoT:
Jiafei Pane48e56c2021-09-30 10:32:54 +0800426clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
427 $nxp_sb_fuse_flags DDR_PHY_BIN_PATH=$(pwd)
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500428
429#X509 Based CoT
Jiafei Pane48e56c2021-09-30 10:32:54 +0800430clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
431 $nxp_sb_flags GENERATE_COT=1 \
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500432 MBEDTLS_DIR=$(pwd)/mbedtls
433
434#BOOT_MODE=emmc and Stack protector
Jiafei Pane48e56c2021-09-30 10:32:54 +0800435clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=emmc \
436 $nxp_sb_fuse_flags ENABLE_STACK_PROTECTOR=strong
437
438# Platform ls1028ardb
439clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor
440clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc
441clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd
442
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800443# ls1028a Secure Boot
Jiafei Pane48e56c2021-09-30 10:32:54 +0800444clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor $nxp_sb_fuse_flags
445clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
446clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
Olivier Deprezbac70192021-04-02 08:55:36 +0200447
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800448# Platform ls1043ardb
449clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor
450clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand
451clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd
452
453# ls1043ardb Secure Boot
454clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
455clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
456clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
457
Jiafei Panbd0c22a2022-01-29 00:04:44 +0800458# ls1046ardb Secure Boot
459clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
460clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
461clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
462
463# ls1046afrwy Secure Boot
464clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
465clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
466
467# ls1046aqds Secure Boot
468clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
469clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
470clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
471clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
472
Jiafei Pan332cd792022-02-24 16:44:48 +0800473# ls1088ardb Secure Boot
474clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
475clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
476
477# ls1088aqds Secure Boot
478clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
479clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
480clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
481
Zelalemc9531f82020-08-04 15:37:08 -0500482# Platforms from Intel
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500483make PLAT=stratix10 $(common_flags) all
484make PLAT=agilex $(common_flags) all
Sieu Mun Tang03b57362022-03-05 01:54:59 +0800485make PLAT=n5x $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500486
487# Platforms from Broadcom
Madhukar Pappireddy97ad2582021-11-15 10:29:23 -0600488clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t \
489 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 DRIVER_I2C_ENABLE=1
490clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t-ns3 \
491 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 USE_USB=yes
Zelalemc9531f82020-08-04 15:37:08 -0500492
493# Platforms from Marvell
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500494make PLAT=a3700 $(common_flags) SCP_BL2=/dev/null CM3_SYSTEM_RESET=1 \
Manish Pandey9ef33c52022-10-25 16:41:49 +0100495 A3720_DB_PM_WAKEUP_SRC=1 HANDLE_EA_EL3_FIRST_NS=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500496
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600497# Source files from mv-ddr-marvell repository are necessary
498# to build below four platforms
Manish Pandey7c1e7452021-11-05 12:54:15 +0000499wget https://downloads.trustedfirmware.org/tf-a/mv-ddr-marvell/mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
500tar -xzf mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600501mv mv-ddr-marvell drivers/marvell/mv_ddr
Zelalemc9531f82020-08-04 15:37:08 -0500502
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600503# These platforms from Marvell have dependency on GCC-6.2.1 toolchain
Pali Rohár8f890402021-07-19 13:48:05 +0200504make PLAT=a80x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200505 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200506make PLAT=a80x0_mcbin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200507 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200508make PLAT=a70x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200509 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200510make PLAT=a70x0_amc DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200511 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Robert Markodf3319e2021-10-20 11:01:12 +0200512make PLAT=a70x0_mochabin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
513 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200514make PLAT=a80x0_puzzle DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200515 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200516make PLAT=t9130 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200517 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500518make PLAT=t9130_cex7_eval DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
519 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500520
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600521# Removing the source files
522rm -rf drivers/marvell/mv_ddr 2> /dev/null
Zelalemc9531f82020-08-04 15:37:08 -0500523
524# Platforms from Meson
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500525make PLAT=gxbb $(common_flags) all
526make PLAT=gxl $(common_flags) all
527make PLAT=g12a $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500528
529# Platforms from Renesas
530# Renesas R-Car D3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500531clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500532 BL33=Makefile LIFEC_DBSC_PROTECT_ENABLE=0 LSI=D3 \
533 MBEDTLS_DIR=$(pwd)/mbedtls PMIC_ROHM_BD9571=0 \
534 RCAR_AVS_SETTING_ENABLE=0 SPD=none RCAR_LOSSY_ENABLE=0 \
535 RCAR_SA0_SIZE=0 RCAR_SYSTEM_SUSPEND=0 TRUSTED_BOARD_BOOT=1
536
537# Renesas R-Car H3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500538clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500539 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3 \
540 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
541 RCAR_DRAM_SPLIT=1 RCAR_GEN3_ULCB=1 SPD=opteed \
542 TRUSTED_BOARD_BOOT=1
543
544# Renesas R-Car H3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500545clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500546 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3N \
547 SPD=opteed TRUSTED_BOARD_BOOT=1
548
549# Renesas R-Car M3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500550clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500551 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3 \
552 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
553 RCAR_DRAM_SPLIT=2 RCAR_GEN3_ULCB=1 SPD=opteed \
554 TRUSTED_BOARD_BOOT=1
555
556# Renesas R-Car M3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500557clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500558 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3N \
559 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
560 RCAR_GEN3_ULCB=1 SPD=opteed TRUSTED_BOARD_BOOT=1
561
562# Renesas R-Car E3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500563clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500564 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=E3 \
565 RCAR_AVS_SETTING_ENABLE=0 RCAR_DRAM_DDR3L_MEMCONF=0 \
566 RCAR_SA0_SIZE=0 SPD=opteed TRUSTED_BOARD_BOOT=1
567
568# Renesas R-Car V3M Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500569clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500570 MBEDTLS_DIR=$(pwd)/mbedtls BL33=Makefile LSI=V3M MACHINE=eagle \
571 PMIC_ROHM_BD9571=0 RCAR_DRAM_SPLIT=0 RCAR_SYSTEM_SUSPEND=0 \
572 AVS_SETTING_ENABLE=0 SPD=none TRUSTED_BOARD_BOOT=1
573
Zelalemf4299672021-01-29 12:52:59 -0600574# Renesas HiHope RZ/G2M development kit
575clean_build PLAT=rzg $(common_flags) \
576 MBEDTLS_DIR=$(pwd)/mbedtls LSI=G2M \
577 RCAR_DRAM_SPLIT=2 RCAR_LOSSY_ENABLE=1 SPD=none
578
Zelalemc9531f82020-08-04 15:37:08 -0500579# Platforms from ST
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100580stm32mp1_common_flags="$(common_flags) \
581 ARCH=aarch32 \
582 ARM_ARCH_MAJOR=7 \
583 CROSS_COMPILE=arm-none-eabi- \
584 ENABLE_STACK_PROTECTOR=strong \
585 PLAT=stm32mp1"
586
Yann Gautiera69cf792021-09-01 11:19:01 +0200587# STM32MP1 SDMMC boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000588make ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200589 BUILD_PLAT=build/stm32mp1-sdmmc/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100590 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200591
592# STM32MP1 eMMC boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000593make ${stm32mp1_common_flags} STM32MP_EMMC=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200594 BUILD_PLAT=build/stm32mp1-emmc/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100595 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200596
597# STM32MP1 Raw NAND boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000598make ${stm32mp1_common_flags} STM32MP_RAW_NAND=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200599 BUILD_PLAT=build/stm32mp1-nand/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100600 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200601
602# STM32MP1 SPI NAND boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000603make ${stm32mp1_common_flags} STM32MP_SPI_NAND=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200604 BUILD_PLAT=build/stm32mp1-snand/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100605 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200606
607# STM32MP1 SPI NOR boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000608make ${stm32mp1_common_flags} STM32MP_SPI_NOR=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200609 BUILD_PLAT=build/stm32mp1-snor/debug \
Govindraj Raja95f855c2023-03-01 13:11:42 +0000610 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200611
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100612# STM32MP1 UART boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000613make ${stm32mp1_common_flags} STM32MP_UART_PROGRAMMER=1 \
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100614 BUILD_PLAT=build/stm32mp1-uart/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100615 AARCH32_SP=sp_min bl2 bl32
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100616
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200617# STM32MP1 USB boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000618make ${stm32mp1_common_flags} STM32MP_USB_PROGRAMMER=1 \
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200619 BUILD_PLAT=build/stm32mp1-usb/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100620 AARCH32_SP=sp_min bl2 bl32
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200621
Lionel Debieve8f464c02022-10-13 09:25:45 +0200622# STM32MP1 TBBR
Govindraj Raja95f855c2023-03-01 13:11:42 +0000623make ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
Yann Gautier741e8492022-11-14 19:04:27 +0100624 BUILD_PLAT=build/stm32mp1-sdmmc-tbbr/debug \
Lionel Debieve8f464c02022-10-13 09:25:45 +0200625 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100626 AARCH32_SP=sp_min bl2 bl32
Lionel Debieve8f464c02022-10-13 09:25:45 +0200627
Govindraj Raja95f855c2023-03-01 13:11:42 +0000628stm32mp13_common_flags="${stm32mp1_common_flags} \
629 AARCH32_SP=optee \
630 STM32MP13=1"
631
Yann Gautier773c5502022-03-10 17:24:47 +0100632# STM32MP13 SDMMC boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000633make ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100634 BUILD_PLAT=build/stm32mp1-mp13-sdmmc/debug bl2
Yann Gautier773c5502022-03-10 17:24:47 +0100635
Lionel Debieve8f464c02022-10-13 09:25:45 +0200636# STM32MP13 TBBR
Govindraj Raja95f855c2023-03-01 13:11:42 +0000637make ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Lionel Debieve8f464c02022-10-13 09:25:45 +0200638 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100639 BUILD_PLAT=build/stm32mp1-mp13-sdmmc-tbbr/debug bl2
Lionel Debieve8f464c02022-10-13 09:25:45 +0200640
Yann Gautiera66e5012022-12-13 13:52:35 +0100641# STM32MP13 TBBR DECRYPTION AES GCM
Govindraj Raja95f855c2023-03-01 13:11:42 +0000642make ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Yann Gautiera66e5012022-12-13 13:52:35 +0100643 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
644 DECRYPTION_SUPPORT=aes_gcm ENCRYPT_BL32=1 \
645 BUILD_PLAT=build/stm32mp1-mp13-sdmmc-tbbr-dec/debug bl2
646
Zelalemc9531f82020-08-04 15:37:08 -0500647# Platforms from TI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500648make PLAT=k3 $(common_flags) all
Hari Nagalladadd89f2022-08-30 12:10:00 -0500649make PLAT=k3 TARGET_BOARD=j784s4 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500650
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500651clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS}
Zelalemc9531f82020-08-04 15:37:08 -0500652# Use GICV3 driver
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500653clean_build PLAT=qemu $(common_flags) QEMU_USE_GIC_DRIVER=QEMU_GICV3 \
Zelalemc9531f82020-08-04 15:37:08 -0500654 ENABLE_STACK_PROTECTOR=strong
655# Use encrypted FIP feature.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500656clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500657 BL32_RAM_LOCATION=tdram DECRYPTION_SUPPORT=aes_gcm ENCRYPT_BL31=1 \
658 ENCRYPT_BL32=1 FW_ENC_STATUS=0 SPD=opteed
Jens Wiklander1a9c2be2021-11-26 09:56:55 +0100659# QEMU with SPMD support
660clean_build PLAT=qemu $(common_flags) BL32=Makefile \
661 BL32_RAM_LOCATION=tdram ARM_BL31_IN_DRAM=1 \
662 SPD=spmd CTX_INCLUDE_EL2_REGS=0 SPMD_SPM_AT_SEL2=0 SPMC_OPTEE=1
Ruchika Gupta86e7f682022-04-12 10:25:46 +0530663# Measured Boot
laurenw-arm8531e702022-06-09 15:32:37 -0500664clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} MBOOT_EL_HASH_ALG=sha256 MEASURED_BOOT=1
Zelalemc9531f82020-08-04 15:37:08 -0500665
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500666clean_build PLAT=qemu_sbsa $(common_flags)
Fathi Boudra422bf772019-12-02 11:10:16 +0200667
Zelalemd86e8762020-08-21 18:24:28 -0500668# QEMU with SPM support
669clean_build PLAT=qemu_sbsa $(common_flags) BL32=Makefile SPM_MM=1 \
Paul Sokolovskycf9fe862023-01-02 16:22:21 +0300670 EL3_EXCEPTION_HANDLING=1 ENABLE_SME_FOR_NS=0 ENABLE_SVE_FOR_NS=0
Zelalemd86e8762020-08-21 18:24:28 -0500671
Fathi Boudra422bf772019-12-02 11:10:16 +0200672# For hikey enable PMF to include all files in the platform port
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500673make PLAT=hikey $(common_flags) ${TBB_OPTIONS} ENABLE_PMF=1 all
674make PLAT=hikey960 $(common_flags) ${TBB_OPTIONS} all
Lukas Haneld0752392022-10-13 11:13:19 +0200675make PLAT=hikey960 $(common_flags) ${TBB_OPTIONS} SPD=spmd SPMC_AT_EL3=1 \
676 SPMD_SPM_AT_SEL2=0 BL32=optee PLAT_SP_MANIFEST_DTS=foo NEED_FDT=no all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500677make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200678
Zelalemc9531f82020-08-04 15:37:08 -0500679# Platforms from Socionext
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500680clean_build PLAT=uniphier $(common_flags) ${TBB_OPTIONS} SPD=tspd
681clean_build PLAT=uniphier $(common_flags) FIP_GZIP=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200682
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500683clean_build PLAT=synquacer $(common_flags) SPM_MM=1 \
Jassi Brar86080922022-06-27 14:16:34 -0500684 RESET_TO_BL31=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0 \
685 PRELOADED_BL33_BASE=0x0
Zelalemc9531f82020-08-04 15:37:08 -0500686
687# Support for SCP Message Interface protocol with platform specific drivers
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500688clean_build PLAT=synquacer $(common_flags) \
Jassi Brar86080922022-06-27 14:16:34 -0500689 RESET_TO_BL31=1 PRELOADED_BL33_BASE=0x0 SQ_USE_SCMI_DRIVER=1
Zelalemc9531f82020-08-04 15:37:08 -0500690
Jassi Brarb8c7ca02022-06-27 14:22:10 -0500691# Support for BL2 and TBBR
692clean_build PLAT=synquacer $(common_flags) \
693 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
694 SQ_USE_SCMI_DRIVER=1 SPD=opteed all
695
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500696make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200697
Zelalemc9531f82020-08-04 15:37:08 -0500698# Raspberry Pi Platforms
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500699make PLAT=rpi3 $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500700 ENABLE_STACK_PROTECTOR=strong PRELOADED_BL33_BASE=0xDEADBEEF all
Andre Przywarae917ec82021-09-03 15:01:30 +0100701clean_build PLAT=rpi4 $(common_flags) SMC_PCI_SUPPORT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200702
Zelalemc9531f82020-08-04 15:37:08 -0500703# A113D (AXG) platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500704clean_build PLAT=axg $(common_flags) SPD=opteed
705clean_build PLAT=axg $(common_flags) AML_USE_ATOS=1
Zelalemc9531f82020-08-04 15:37:08 -0500706
Stephan Gerhold141a7662021-12-07 20:42:14 +0100707# QTI MSM8916 platform
708clean_build PLAT=msm8916 $(common_flags)
709
Fathi Boudra422bf772019-12-02 11:10:16 +0200710cd ..