blob: 8f28ca51420f6fcffb0f738fdd292149a5e89adc [file] [log] [blame]
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -05001#!/usr/bin/env bash
Fathi Boudra422bf772019-12-02 11:10:16 +02002#
Yann Gautier773c5502022-03-10 17:24:47 +01003# Copyright (c) 2019-2022, Arm Limited. All rights reserved.
Fathi Boudra422bf772019-12-02 11:10:16 +02004#
5# SPDX-License-Identifier: BSD-3-Clause
6#
7
8#
9# This script builds the TF in different configs.
10# Rather than telling cov-build to build TF using a simple 'make all' command,
11# the goal here is to combine several build flags to analyse more of our source
12# code in a single 'build'. The Coverity Scan service does not have the notion
13# of separate types of build - there is just one linear sequence of builds in
14# the project history.
15#
16
17# Bail out as soon as an error is encountered.
18set -e
19
20TF_SOURCES=$1
21if [ ! -d "$TF_SOURCES" ]; then
22 echo "ERROR: '$TF_SOURCES' does not exist or is not a directory"
23 echo "Usage: $(basename "$0") <trusted-firmware-directory>"
24 exit 1
25fi
26
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050027containing_dir="$(readlink -f "$(dirname "$0")/")"
28. $containing_dir/common-def.sh
29
Fathi Boudra422bf772019-12-02 11:10:16 +020030# Get mbed TLS library code to build Trusted Firmware with Trusted Board Boot
31# support. The version of mbed TLS to use here must be the same as when
32# building TF in the usual context.
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050033if [ ! -d "$MBED_TLS_DIR" ]; then
34 git clone -q --depth 1 -b "$MBED_TLS_SOURCES_TAG" "$MBED_TLS_URL_REPO" "$MBED_TLS_DIR"
Fathi Boudra422bf772019-12-02 11:10:16 +020035fi
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050036
Fathi Boudra422bf772019-12-02 11:10:16 +020037cd "$TF_SOURCES"
38
39# Clean TF source dir to make sure we don't analyse temporary files.
40make distclean
41
42#
43# Build TF in different configurations to get as much coverage as possible
44#
45
Fathi Boudra422bf772019-12-02 11:10:16 +020046#
47# FVP platform
48# We'll use the following flags for all FVP builds.
49#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050050fvp_common_flags="$(common_flags) PLAT=fvp"
Fathi Boudra422bf772019-12-02 11:10:16 +020051
52# Try all possible SPDs.
53clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd
54clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd TSP_INIT_ASYNC=1 \
55 TSP_NS_INTR_ASYNC_PREEMPT=1
56clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed
57clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tlkd
Florian Lugou70a76c02022-03-25 09:51:42 +010058clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=pncd SPD_PNCD_NS_IRQ=126 SPD_PNCD_S_IRQ=15
Fathi Boudra422bf772019-12-02 11:10:16 +020059
Zelalemc9531f82020-08-04 15:37:08 -050060# Dualroot chain of trust.
61clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tspd COT=dualroot
62
laurenw-armf48e9d22022-04-22 11:30:13 -050063# FEAT_RME with CCA chain of trust.
Sandrine Bailleuxe30bd0c2022-08-31 14:49:17 +020064#
65# Note that we override PLAT_RSS_NOT_SUPPORTED build flag (which defaults to 1
66# on the Base AEM FVP) just to analyse the RSS communication driver code through
67# Coverity. In reality, RSS is not supported on FVP right now (or on any other
68# upstream platform, for that matter) so the resulting firmware would not be
69# functional.
70clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tspd USE_ROMLIB=1 \
71 ENABLE_RME=1 MEASURED_BOOT=1 PLAT_RSS_NOT_SUPPORTED=0
laurenw-armf48e9d22022-04-22 11:30:13 -050072
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050073clean_build $fvp_common_flags SPD=trusty
74clean_build $fvp_common_flags SPD=trusty TRUSTY_SPD_WITH_GENERIC_SERVICES=1
Fathi Boudra422bf772019-12-02 11:10:16 +020075
76# SDEI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050077clean_build $fvp_common_flags SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Fathi Boudra422bf772019-12-02 11:10:16 +020078
Zelalemc9531f82020-08-04 15:37:08 -050079# SDEI with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050080clean_build $fvp_common_flags SDEI_IN_FCONF=1 SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Zelalemc9531f82020-08-04 15:37:08 -050081
Zelalem4f3633e2021-06-18 11:53:47 -050082# PCI Service
83clean_build $fvp_common_flags SMC_PCI_SUPPORT=1
84
Zelalemc9531f82020-08-04 15:37:08 -050085# Secure interrupt descriptors with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050086clean_build $fvp_common_flags SEC_INT_DESC_IN_FCONF=1
Zelalemc9531f82020-08-04 15:37:08 -050087
Fathi Boudra422bf772019-12-02 11:10:16 +020088# Without coherent memory
89clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd USE_COHERENT_MEM=0
90
91# Using PSCI extended State ID format rather than the original format
92clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd PSCI_EXTENDED_STATE_ID=1 \
93 ARM_RECOM_STATE_ID_ENC=1
94
95# Alternative boot flows (This changes some of the platform initialisation code)
96clean_build $fvp_common_flags EL3_PAYLOAD=0x80000000
97clean_build $fvp_common_flags PRELOADED_BL33_BASE=0x80000000
98
99# Using the SP804 timer instead of the Generic Timer
100clean_build $fvp_common_flags FVP_USE_SP804_TIMER=1
101
102# Using the CCN driver and multi cluster topology
103clean_build $fvp_common_flags FVP_CLUSTER_COUNT=4
104
105# PMF
106clean_build $fvp_common_flags ENABLE_PMF=1
107
108# stack protector
109clean_build $fvp_common_flags ENABLE_STACK_PROTECTOR=strong
110
111# AArch32 build
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500112clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200113 ARCH=aarch32 AARCH32_SP=sp_min \
114 RESET_TO_SP_MIN=1 PRELOADED_BL33_BASE=0x80000000
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500115clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200116 ARCH=aarch32 AARCH32_SP=sp_min
117
118# Xlat tables lib version 1 (AArch64 and AArch32)
119clean_build $fvp_common_flags ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500120clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200121 ARCH=aarch32 AARCH32_SP=sp_min ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
122
Zelalemc9531f82020-08-04 15:37:08 -0500123# SPM support based on Management Mode Interface Specification
Manish Pandeyaa9a03b2021-11-17 10:03:17 +0000124clean_build $fvp_common_flags SPM_MM=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0
Fathi Boudra422bf772019-12-02 11:10:16 +0200125
Zelalemc9531f82020-08-04 15:37:08 -0500126# SPM support with TOS(optee) as SPM sitting at S-EL1
127clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0
128
Shruti Gupta8cc89b92022-08-09 12:23:46 +0100129# SPM support with SPM at EL3 and TSP at S-EL1
130clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 CTX_INCLUDE_EL2_REGS=0 EL3_EXCEPTION_HANDLING=0 \
131 SPD=spmd SPMD_SPM_AT_SEL2=0 SPMC_AT_EL3=1 \
132 ARM_SPMC_MANIFEST_DTS=plat/arm/board/fvp/fdts/fvp_tsp_sp_manifest.dts
133
Zelalemc9531f82020-08-04 15:37:08 -0500134# SPM support with Secure hafnium as SPM sitting at S-EL2
135# SP_LAYOUT_FILE is used only during FIP creation but build won't progress
136# if we have NULL value to it, so passing a dummy string.
137clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=1 ARM_ARCH_MINOR=4 \
Max Shvetsov44d2a702021-02-18 16:41:45 +0000138 CTX_INCLUDE_EL2_REGS=1 SP_LAYOUT_FILE=dummy
Fathi Boudra422bf772019-12-02 11:10:16 +0200139
Marc Bonnici502fdaa2022-01-10 12:38:23 +0000140# SPM support with SPM sitting at EL3
141clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0 SPMC_AT_EL3=1
142
Fathi Boudra422bf772019-12-02 11:10:16 +0200143#BL2 at EL3 support
144clean_build $fvp_common_flags BL2_AT_EL3=1
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500145clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200146 ARCH=aarch32 AARCH32_SP=sp_min BL2_AT_EL3=1
147
Zelalemc9531f82020-08-04 15:37:08 -0500148# RAS Extension Support
149clean_build $fvp_common_flags EL3_EXCEPTION_HANDLING=1 \
150 FAULT_INJECTION_SUPPORT=1 HANDLE_EA_EL3_FIRST=1 RAS_EXTENSION=1 \
151 SDEI_SUPPORT=1
152
153# Hardware Assisted Coherency(DynamIQ)
154clean_build $fvp_common_flags FVP_CLUSTER_COUNT=1 FVP_MAX_CPUS_PER_CLUSTER=8 \
155 HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0
156
157# Pointer Authentication Support
158clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 \
159 ARM_ARCH_MINOR=5 EL3_EXCEPTION_HANDLING=1 BRANCH_PROTECTION=1 SDEI_SUPPORT=1 SPD=tspd TSP_NS_INTR_ASYNC_PREEMPT=1
160
161# Undefined Behaviour Sanitizer
162# Building with UBSAN SANITIZE_UB=on increases the executable size.
163# Hence it is only properly supported in bl31 with RESET_TO_BL31 enabled
164make $fvp_common_flags clean
165make $fvp_common_flags SANITIZE_UB=on RESET_TO_BL31=1 bl31
166
167# debugfs feature
168clean_build $fvp_common_flags DEBUG=1 USE_DEBUGFS=1
169
170# MPAM feature
171clean_build $fvp_common_flags ENABLE_MPAM_FOR_LOWER_ELS=1
172
173# Using GICv3.1 driver with extended PPI and SPI range
174clean_build $fvp_common_flags GIC_EXT_INTID=1
175
176# Using GICv4 features with extended PPI and SPI range
177clean_build $fvp_common_flags GIC_ENABLE_V4_EXTN=1 GIC_EXT_INTID=1
178
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100179# Measured Boot
laurenw-arm8531e702022-06-09 15:32:37 -0500180clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} MBOOT_EL_HASH_ALG=sha256 MEASURED_BOOT=1 USE_ROMLIB=1
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100181
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100182# CoT descriptors in device tree
Manish V Badarkhe81102d12020-10-05 08:02:30 +0100183clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} COT_DESC_IN_DTB=1 USE_ROMLIB=1
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100184
Manish V Badarkhe107c8e32021-08-02 19:49:32 +0100185# PSA FWU support
186clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_GPT_SUPPORT=1 PSA_FWU_SUPPORT=1 USE_ROMLIB=1
187
johpow01153c8b22021-11-03 14:38:36 -0500188# SME and HCX features
189clean_build $fvp_common_flags ENABLE_SME_FOR_NS=1 ENABLE_FEAT_HCX=1
190
Jayanth Dodderi Chidanand84da1962022-04-11 11:38:44 +0100191# Architectural Feature Detection mechanism
192clean_build $fvp_common_flags FEATURE_DETECTION=1
193
Fathi Boudra422bf772019-12-02 11:10:16 +0200194#
195# Juno platform
196# We'll use the following flags for all Juno builds.
197#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500198juno_common_flags="$(common_flags) PLAT=juno"
Fathi Boudra422bf772019-12-02 11:10:16 +0200199clean_build $juno_common_flags SPD=tspd ${ARM_TBB_OPTIONS}
200clean_build $juno_common_flags EL3_PAYLOAD=0x80000000
Madhukar Pappireddydcb31f62021-05-06 11:36:36 -0500201clean_build $juno_common_flags ENABLE_STACK_PROTECTOR=strong ARM_ETHOSN_NPU_DRIVER=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200202clean_build $juno_common_flags CSS_USE_SCMI_SDS_DRIVER=0
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500203
Leonardo Sandoval5163b562020-11-20 17:17:59 -0600204clean_build $juno_common_flags SPD=tspd ${ARM_TBB_OPTIONS} ARM_CRYPTOCELL_INTEG=1 CCSBROM_LIB_PATH=${CRYPTOCELL_LIB_PATH} KEY_SIZE=2048
Fathi Boudra422bf772019-12-02 11:10:16 +0200205
206#
207# System Guidance for Infrastructure platform SGI575
Zelalemc9531f82020-08-04 15:37:08 -0500208# Enable build config with RAS_EXTENSION to cover more files
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500209make $(common_flags) PLAT=sgi575 ${ARM_TBB_OPTIONS} EL3_EXCEPTION_HANDLING=1 FAULT_INJECTION_SUPPORT=1 \
Manish Pandeyaa9a03b2021-11-17 10:03:17 +0000210 HANDLE_EA_EL3_FIRST=1 RAS_EXTENSION=1 SDEI_SUPPORT=1 SPM_MM=1 ENABLE_SVE_FOR_NS=0 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200211
212#
Vijayenthiran Subramaniam2a47a6d2020-07-22 14:16:58 +0530213# System Guidance for Infrastructure platform RD-N1-Edge-Dual
Fathi Boudra422bf772019-12-02 11:10:16 +0200214#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500215make $(common_flags) PLAT=rdn1edge CSS_SGI_CHIP_COUNT=2 ${ARM_TBB_OPTIONS} all
Fathi Boudra422bf772019-12-02 11:10:16 +0200216
217#
218# System Guidance for Infrastructure platform RD-E1Edge
219#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500220make $(common_flags) PLAT=rde1edge ${ARM_TBB_OPTIONS} CSS_SGI_CHIP_COUNT=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500221
222#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530223# Reference Design platform RD-V1
Zelalemc9531f82020-08-04 15:37:08 -0500224#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530225make $(common_flags) PLAT=rdv1 ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500226
227#
Aditya Angadi61c54762021-01-04 09:30:52 +0530228# Reference Design platform RD-V1-MC
Zelalemc9531f82020-08-04 15:37:08 -0500229#
Aditya Angadi61c54762021-01-04 09:30:52 +0530230make $(common_flags) PLAT=rdv1mc ${ARM_TBB_OPTIONS} CSS_SGI_CHIP_COUNT=4 all
Zelalemc9531f82020-08-04 15:37:08 -0500231
232#
Vijayenthiran Subramaniama66de332020-11-23 14:20:14 +0530233# Reference Design Platform RD-N2
234#
235make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} all
236
237#
Zelalemc9531f82020-08-04 15:37:08 -0500238# Neoverse N1 SDP platform
239#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500240make $(common_flags) PLAT=n1sdp ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500241
242#
243# FVP VE platform
244#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500245make $(common_flags) PLAT=fvp_ve AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500246 CROSS_COMPILE=arm-none-eabi- ARM_ARCH_MAJOR=7 \
247 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
248 FVP_HW_CONFIG_DTS=fdts/fvp-ve-Cortex-A5x1.dts all
249
250#
251# A5 DesignStart Platform
252#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500253make $(common_flags) PLAT=a5ds AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500254 ARM_ARCH_MAJOR=7 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
255 CROSS_COMPILE=arm-none-eabi- FVP_HW_CONFIG_DTS=fdts/a5ds.dts
256
257#
258# Corstone700 Platform
259#
260
261corstone700_common_flags="CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500262 $(common_flags) \
Zelalemc9531f82020-08-04 15:37:08 -0500263 PLAT=corstone700 \
264 ARCH=aarch32 \
265 RESET_TO_SP_MIN=1 \
266 AARCH32_SP=sp_min \
267 ARM_LINUX_KERNEL_AS_BL33=0 \
268 ARM_PRELOADED_DTB_BASE=0x80400000 \
269 ENABLE_PIE=1 \
Zelalemc9531f82020-08-04 15:37:08 -0500270 ENABLE_STACK_PROTECTOR=all \
271 all"
272
273echo "Info: Building Corstone700 FVP ..."
274
275make TARGET_PLATFORM=fvp ${corstone700_common_flags}
276
277echo "Info: Building Corstone700 FPGA ..."
278
279make TARGET_PLATFORM=fpga ${corstone700_common_flags}
280
281#
282# Arm internal FPGA port
283#
Andre Przywara13361b62022-04-26 11:16:55 +0100284make PLAT=arm_fpga $(common_flags release) \
285 FPGA_PRELOADED_DTB_BASE=0x88000000 PRELOADED_BL33_BASE=0x82080000 all
Zelalemc9531f82020-08-04 15:37:08 -0500286
287#
Usama Arifcba711d2021-08-04 15:53:42 +0100288# Total Compute platforms
Zelalemc9531f82020-08-04 15:37:08 -0500289#
Usama Arifcba711d2021-08-04 15:53:42 +0100290make $(common_flags) PLAT=tc TARGET_PLATFORM=0 ${ARM_TBB_OPTIONS} all
291make $(common_flags) PLAT=tc TARGET_PLATFORM=1 ${ARM_TBB_OPTIONS} all
Rupinderjit Singh385f17d2022-07-18 20:28:10 +0100292make $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} all
Fathi Boudra422bf772019-12-02 11:10:16 +0200293
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530294#
295# Morello platform
296#
Chandni Cherukuricbd45962021-12-12 13:37:33 +0530297clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=fvp ${ARM_TBB_OPTIONS}
298clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=soc ${ARM_TBB_OPTIONS}
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530299
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100300#
Vishnu Banavath2cb72b32022-01-20 14:27:55 +0000301# corstone1000 Platform
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100302#
303
304make $(common_flags) \
Vishnu Banavath2cb72b32022-01-20 14:27:55 +0000305 PLAT=corstone1000 \
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100306 SPD=spmd \
307 TARGET_PLATFORM=fpga \
308 ENABLE_STACK_PROTECTOR=strong \
309 ENABLE_PIE=1 \
310 BL2_AT_EL3=1 \
311 SPMD_SPM_AT_SEL2=0 \
312 ${ARM_TBB_OPTIONS} \
313 CREATE_KEYS=1 \
314 COT=tbbr \
315 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
316 bl2 \
317 bl31
318
johpow01aac58582021-10-05 16:51:34 -0500319#
320# FVP-R platform
321#
322clean_build $(common_flags) PLAT=fvp_r ${ARM_TBB_OPTIONS} ENABLE_STACK_PROTECTOR=all
323
Fathi Boudra422bf772019-12-02 11:10:16 +0200324# Partners' platforms.
325# Enable as many features as possible.
326# We don't need to clean between each build here because we only do one build
327# per platform so we don't hit the build flags dependency problem.
Fathi Boudra422bf772019-12-02 11:10:16 +0200328
Manish Pandey9c0ee742021-07-08 09:55:59 +0100329# Platforms from Mediatek
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500330make PLAT=mt8173 $(common_flags) all
331make PLAT=mt8183 $(common_flags) all
Rex-BC Chen946cace2021-11-17 10:15:42 +0800332make PLAT=mt8186 $(common_flags) COREBOOT=1 all
Bo-Chen Chen4d63afd2022-08-30 16:34:57 +0800333make PLAT=mt8188 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500334make PLAT=mt8192 $(common_flags) COREBOOT=1 all
Manish Pandey9c0ee742021-07-08 09:55:59 +0100335make PLAT=mt8195 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500336
337# Platforms from Qualcomm
338make PLAT=sc7180 $(common_flags) COREBOOT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200339
Zelalemc9531f82020-08-04 15:37:08 -0500340make PLAT=rk3288 CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500341 $(common_flags) ARCH=aarch32 AARCH32_SP=sp_min all
Madhukar Pappireddyd491ad02020-12-03 10:37:05 -0600342make PLAT=rk3368 $(common_flags) COREBOOT=1 \
343 ENABLE_STACK_PROTECTOR=strong all
344make PLAT=rk3399 $(common_flags) COREBOOT=1 PLAT_RK_DP_HDCP=1 \
345 ENABLE_STACK_PROTECTOR=strong all
346make PLAT=rk3328 $(common_flags) COREBOOT=1 PLAT_RK_SECURE_DDR_MINILOADER=1 \
347 ENABLE_STACK_PROTECTOR=strong all
348make PLAT=px30 $(common_flags) PLAT_RK_SECURE_DDR_MINILOADER=1 \
349 ENABLE_STACK_PROTECTOR=strong all
Fathi Boudra422bf772019-12-02 11:10:16 +0200350
351# Although we do several consecutive builds for the Tegra platform below, we
352# don't need to clean between each one because the Tegra makefiles specify
353# a different build directory per SoC.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500354make PLAT=tegra TARGET_SOC=t210 $(common_flags) all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500355make PLAT=tegra TARGET_SOC=t186 $(common_flags) all
356make PLAT=tegra TARGET_SOC=t194 $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200357
358# For the Xilinx platform, artificially increase the extents of BL31 memory
359# (using the platform-specific build options ZYNQMP_ATF_MEM_{BASE,SIZE}).
360# If we keep the default values, BL31 doesn't fit when it is built with all
361# these build flags.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500362make PLAT=zynqmp $(common_flags) \
Fathi Boudra422bf772019-12-02 11:10:16 +0200363 RESET_TO_BL31=1 SPD=tspd \
Zelalem4f3633e2021-06-18 11:53:47 -0500364 SDEI_SUPPORT=1 \
Fathi Boudra422bf772019-12-02 11:10:16 +0200365 ZYNQMP_ATF_MEM_BASE=0xFFFC0000 ZYNQMP_ATF_MEM_SIZE=0x00040000 \
366 all
367
Zelalemc9531f82020-08-04 15:37:08 -0500368# Build both for silicon (default) and virtual QEMU platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500369clean_build PLAT=versal $(common_flags)
370clean_build PLAT=versal $(common_flags) VERSAL_PLATFORM=versal_virt
Zelalemc9531f82020-08-04 15:37:08 -0500371
Michal Simek0f135242022-09-20 15:24:56 +0200372# Build Xilinx Versal NET platform
373clean_build PLAT=versal_net $(common_flags)
374
Zelalemc9531f82020-08-04 15:37:08 -0500375# Platforms from Allwinner
Andre Przywara3a78c102022-04-26 11:08:54 +0100376clean_build PLAT=sun50i_a64 $(common_flags release) all
377clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_NATIVE=0 all
378clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_SCPI=0 all
379clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_AMEND_DTB=1 all
Andre Przywaracf78a512021-09-03 14:59:38 +0100380clean_build PLAT=sun50i_h6 $(common_flags) all
381clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_NATIVE=0 all
382clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_SCPI=0 all
383clean_build PLAT=sun50i_h616 $(common_flags) all
384clean_build PLAT=sun50i_r329 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500385
386# Platforms from i.MX
387make AARCH32_SP=optee ARCH=aarch32 ARM_ARCH_MAJOR=7 ARM_CORTEX_A7=yes \
388 CROSS_COMPILE=arm-none-eabi- PLAT=warp7 ${TBB_OPTIONS} \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500389 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500390make AARCH32_SP=optee ARCH=aarch32 CROSS_COMPILE=arm-none-eabi- PLAT=picopi \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500391 $(common_flags) all
Ying-Chun Liu (PaulLiu)f6528982021-11-17 17:20:00 +0800392make PLAT=imx8mm $(common_flags) NEED_BL2=yes MEASURED_BOOT=1 \
laurenw-arm8531e702022-06-09 15:32:37 -0500393 MBOOT_EL_HASH_ALG=sha256 ${TBB_OPTIONS} all
Madhukar Pappireddyc3ec06b2022-05-18 11:15:16 -0500394make PLAT=imx8mn $(common_flags) SDEI_SUPPORT=1 all
Ying-Chun Liu (PaulLiu)413e6102021-09-14 00:22:08 +0800395make PLAT=imx8mp $(common_flags) NEED_BL2=yes ${TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500396
Jacky Baib6cecc82021-06-07 09:49:46 +0800397# Due to the limited OCRAM space that can be used for TF-A, build test
398# will report failure caused by too small RAM size, so comment out the
399# build test for imx8mq in CI. It can also resolve the following ticket:
Zelalemc9531f82020-08-04 15:37:08 -0500400# https://developer.trustedfirmware.org/T626
Jacky Baib6cecc82021-06-07 09:49:46 +0800401#make PLAT=imx8mq $(common_flags release) all
Zelalemc9531f82020-08-04 15:37:08 -0500402
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500403make PLAT=imx8qm $(common_flags) all
404make PLAT=imx8qx $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500405
Olivier Deprezbac70192021-04-02 08:55:36 +0200406# Platforms for NXP Layerscape
Jiafei Pane48e56c2021-09-30 10:32:54 +0800407nxp_sb_flags="TRUSTED_BOARD_BOOT=1 CST_DIR=$(pwd) SPD=opteed"
408nxp_sb_fuse_flags="${nxp_sb_flags} FUSE_PROG=1"
409
410# Platform lx2
Olivier Deprezbac70192021-04-02 08:55:36 +0200411make PLAT=lx2160aqds $(common_flags) all
412make PLAT=lx2160ardb $(common_flags) all
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500413
414#CSF Based CoT:
Jiafei Pane48e56c2021-09-30 10:32:54 +0800415clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
416 $nxp_sb_fuse_flags DDR_PHY_BIN_PATH=$(pwd)
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500417
418#X509 Based CoT
Jiafei Pane48e56c2021-09-30 10:32:54 +0800419clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
420 $nxp_sb_flags GENERATE_COT=1 \
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500421 MBEDTLS_DIR=$(pwd)/mbedtls
422
423#BOOT_MODE=emmc and Stack protector
Jiafei Pane48e56c2021-09-30 10:32:54 +0800424clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=emmc \
425 $nxp_sb_fuse_flags ENABLE_STACK_PROTECTOR=strong
426
427# Platform ls1028ardb
428clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor
429clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc
430clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd
431
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800432# ls1028a Secure Boot
Jiafei Pane48e56c2021-09-30 10:32:54 +0800433clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor $nxp_sb_fuse_flags
434clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
435clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
Olivier Deprezbac70192021-04-02 08:55:36 +0200436
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800437# Platform ls1043ardb
438clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor
439clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand
440clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd
441
442# ls1043ardb Secure Boot
443clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
444clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
445clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
446
Jiafei Panbd0c22a2022-01-29 00:04:44 +0800447# ls1046ardb Secure Boot
448clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
449clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
450clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
451
452# ls1046afrwy Secure Boot
453clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
454clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
455
456# ls1046aqds Secure Boot
457clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
458clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
459clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
460clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
461
Jiafei Pan332cd792022-02-24 16:44:48 +0800462# ls1088ardb Secure Boot
463clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
464clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
465
466# ls1088aqds Secure Boot
467clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
468clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
469clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
470
Zelalemc9531f82020-08-04 15:37:08 -0500471# Platforms from Intel
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500472make PLAT=stratix10 $(common_flags) all
473make PLAT=agilex $(common_flags) all
Sieu Mun Tang03b57362022-03-05 01:54:59 +0800474make PLAT=n5x $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500475
476# Platforms from Broadcom
Madhukar Pappireddy97ad2582021-11-15 10:29:23 -0600477clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t \
478 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 DRIVER_I2C_ENABLE=1
479clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t-ns3 \
480 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 USE_USB=yes
Zelalemc9531f82020-08-04 15:37:08 -0500481
482# Platforms from Marvell
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500483make PLAT=a3700 $(common_flags) SCP_BL2=/dev/null CM3_SYSTEM_RESET=1 \
484 A3720_DB_PM_WAKEUP_SRC=1 HANDLE_EA_EL3_FIRST=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500485
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600486# Source files from mv-ddr-marvell repository are necessary
487# to build below four platforms
Manish Pandey7c1e7452021-11-05 12:54:15 +0000488wget https://downloads.trustedfirmware.org/tf-a/mv-ddr-marvell/mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
489tar -xzf mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600490mv mv-ddr-marvell drivers/marvell/mv_ddr
Zelalemc9531f82020-08-04 15:37:08 -0500491
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600492# These platforms from Marvell have dependency on GCC-6.2.1 toolchain
Pali Rohár8f890402021-07-19 13:48:05 +0200493make PLAT=a80x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200494 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200495make PLAT=a80x0_mcbin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200496 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200497make PLAT=a70x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200498 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200499make PLAT=a70x0_amc DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200500 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Robert Markodf3319e2021-10-20 11:01:12 +0200501make PLAT=a70x0_mochabin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
502 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200503make PLAT=a80x0_puzzle DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200504 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200505make PLAT=t9130 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200506 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500507make PLAT=t9130_cex7_eval DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
508 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500509
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600510# Removing the source files
511rm -rf drivers/marvell/mv_ddr 2> /dev/null
Zelalemc9531f82020-08-04 15:37:08 -0500512
513# Platforms from Meson
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500514make PLAT=gxbb $(common_flags) all
515make PLAT=gxl $(common_flags) all
516make PLAT=g12a $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500517
518# Platforms from Renesas
519# Renesas R-Car D3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500520clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500521 BL33=Makefile LIFEC_DBSC_PROTECT_ENABLE=0 LSI=D3 \
522 MBEDTLS_DIR=$(pwd)/mbedtls PMIC_ROHM_BD9571=0 \
523 RCAR_AVS_SETTING_ENABLE=0 SPD=none RCAR_LOSSY_ENABLE=0 \
524 RCAR_SA0_SIZE=0 RCAR_SYSTEM_SUSPEND=0 TRUSTED_BOARD_BOOT=1
525
526# Renesas R-Car H3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500527clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500528 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3 \
529 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
530 RCAR_DRAM_SPLIT=1 RCAR_GEN3_ULCB=1 SPD=opteed \
531 TRUSTED_BOARD_BOOT=1
532
533# Renesas R-Car H3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500534clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500535 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3N \
536 SPD=opteed TRUSTED_BOARD_BOOT=1
537
538# Renesas R-Car M3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500539clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500540 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3 \
541 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
542 RCAR_DRAM_SPLIT=2 RCAR_GEN3_ULCB=1 SPD=opteed \
543 TRUSTED_BOARD_BOOT=1
544
545# Renesas R-Car M3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500546clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500547 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3N \
548 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
549 RCAR_GEN3_ULCB=1 SPD=opteed TRUSTED_BOARD_BOOT=1
550
551# Renesas R-Car E3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500552clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500553 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=E3 \
554 RCAR_AVS_SETTING_ENABLE=0 RCAR_DRAM_DDR3L_MEMCONF=0 \
555 RCAR_SA0_SIZE=0 SPD=opteed TRUSTED_BOARD_BOOT=1
556
557# Renesas R-Car V3M Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500558clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500559 MBEDTLS_DIR=$(pwd)/mbedtls BL33=Makefile LSI=V3M MACHINE=eagle \
560 PMIC_ROHM_BD9571=0 RCAR_DRAM_SPLIT=0 RCAR_SYSTEM_SUSPEND=0 \
561 AVS_SETTING_ENABLE=0 SPD=none TRUSTED_BOARD_BOOT=1
562
Zelalemf4299672021-01-29 12:52:59 -0600563# Renesas HiHope RZ/G2M development kit
564clean_build PLAT=rzg $(common_flags) \
565 MBEDTLS_DIR=$(pwd)/mbedtls LSI=G2M \
566 RCAR_DRAM_SPLIT=2 RCAR_LOSSY_ENABLE=1 SPD=none
567
Zelalemc9531f82020-08-04 15:37:08 -0500568# Platforms from ST
Yann Gautiera69cf792021-09-01 11:19:01 +0200569# STM32MP1 SDMMC boot
570make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
571 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_SDMMC=1 \
572 BUILD_PLAT=build/stm32mp1-sdmmc/debug \
573 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
574
575# STM32MP1 eMMC boot
Zelalemc9531f82020-08-04 15:37:08 -0500576make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500577 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_EMMC=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200578 BUILD_PLAT=build/stm32mp1-emmc/debug \
579 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
580
581# STM32MP1 Raw NAND boot
582make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
583 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_RAW_NAND=1 \
584 BUILD_PLAT=build/stm32mp1-nand/debug \
585 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
586
587# STM32MP1 SPI NAND boot
588make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
589 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_SPI_NAND=1 \
590 BUILD_PLAT=build/stm32mp1-snand/debug \
591 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
592
593# STM32MP1 SPI NOR boot
594make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
595 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_SPI_NOR=1 \
596 BUILD_PLAT=build/stm32mp1-snor/debug \
597 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
598
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100599# STM32MP1 UART boot
600make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
601 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_UART_PROGRAMMER=1 \
602 BUILD_PLAT=build/stm32mp1-uart/debug \
603 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
604
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200605# STM32MP1 USB boot
606make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
607 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_USB_PROGRAMMER=1 \
608 BUILD_PLAT=build/stm32mp1-usb/debug \
609 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
610
Yann Gautiera69cf792021-09-01 11:19:01 +0200611# STM32MP1 SDMMC boot without FIP
612make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
613 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_SDMMC=1 \
614 BUILD_PLAT=build/stm32mp1-sdmmc-stm32image/debug \
615 STM32MP_USE_STM32IMAGE=1 \
616 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
Zelalemc9531f82020-08-04 15:37:08 -0500617
Yann Gautier773c5502022-03-10 17:24:47 +0100618# STM32MP13 SDMMC boot
619make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
620 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_SDMMC=1 \
621 BUILD_PLAT=build/stm32mp1-mp13-sdmmc/debug STM32MP13=1 \
622 ARCH=aarch32 AARCH32_SP=optee ENABLE_STACK_PROTECTOR=strong bl2
623
Zelalemc9531f82020-08-04 15:37:08 -0500624# Platforms from TI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500625make PLAT=k3 $(common_flags) all
Hari Nagalladadd89f2022-08-30 12:10:00 -0500626make PLAT=k3 TARGET_BOARD=j784s4 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500627
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500628clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS}
Zelalemc9531f82020-08-04 15:37:08 -0500629# Use GICV3 driver
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500630clean_build PLAT=qemu $(common_flags) QEMU_USE_GIC_DRIVER=QEMU_GICV3 \
Zelalemc9531f82020-08-04 15:37:08 -0500631 ENABLE_STACK_PROTECTOR=strong
632# Use encrypted FIP feature.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500633clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500634 BL32_RAM_LOCATION=tdram DECRYPTION_SUPPORT=aes_gcm ENCRYPT_BL31=1 \
635 ENCRYPT_BL32=1 FW_ENC_STATUS=0 SPD=opteed
Jens Wiklander1a9c2be2021-11-26 09:56:55 +0100636# QEMU with SPMD support
637clean_build PLAT=qemu $(common_flags) BL32=Makefile \
638 BL32_RAM_LOCATION=tdram ARM_BL31_IN_DRAM=1 \
639 SPD=spmd CTX_INCLUDE_EL2_REGS=0 SPMD_SPM_AT_SEL2=0 SPMC_OPTEE=1
Ruchika Gupta86e7f682022-04-12 10:25:46 +0530640# Measured Boot
laurenw-arm8531e702022-06-09 15:32:37 -0500641clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} MBOOT_EL_HASH_ALG=sha256 MEASURED_BOOT=1
Zelalemc9531f82020-08-04 15:37:08 -0500642
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500643clean_build PLAT=qemu_sbsa $(common_flags)
Fathi Boudra422bf772019-12-02 11:10:16 +0200644
Zelalemd86e8762020-08-21 18:24:28 -0500645# QEMU with SPM support
646clean_build PLAT=qemu_sbsa $(common_flags) BL32=Makefile SPM_MM=1 \
Manish Pandeyaa9a03b2021-11-17 10:03:17 +0000647 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0
Zelalemd86e8762020-08-21 18:24:28 -0500648
Fathi Boudra422bf772019-12-02 11:10:16 +0200649# For hikey enable PMF to include all files in the platform port
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500650make PLAT=hikey $(common_flags) ${TBB_OPTIONS} ENABLE_PMF=1 all
651make PLAT=hikey960 $(common_flags) ${TBB_OPTIONS} all
652make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200653
Zelalemc9531f82020-08-04 15:37:08 -0500654# Platforms from Socionext
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500655clean_build PLAT=uniphier $(common_flags) ${TBB_OPTIONS} SPD=tspd
656clean_build PLAT=uniphier $(common_flags) FIP_GZIP=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200657
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500658clean_build PLAT=synquacer $(common_flags) SPM_MM=1 \
Jassi Brar86080922022-06-27 14:16:34 -0500659 RESET_TO_BL31=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0 \
660 PRELOADED_BL33_BASE=0x0
Zelalemc9531f82020-08-04 15:37:08 -0500661
662# Support for SCP Message Interface protocol with platform specific drivers
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500663clean_build PLAT=synquacer $(common_flags) \
Jassi Brar86080922022-06-27 14:16:34 -0500664 RESET_TO_BL31=1 PRELOADED_BL33_BASE=0x0 SQ_USE_SCMI_DRIVER=1
Zelalemc9531f82020-08-04 15:37:08 -0500665
Jassi Brarb8c7ca02022-06-27 14:22:10 -0500666# Support for BL2 and TBBR
667clean_build PLAT=synquacer $(common_flags) \
668 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
669 SQ_USE_SCMI_DRIVER=1 SPD=opteed all
670
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500671make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200672
Zelalemc9531f82020-08-04 15:37:08 -0500673# Raspberry Pi Platforms
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500674make PLAT=rpi3 $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500675 ENABLE_STACK_PROTECTOR=strong PRELOADED_BL33_BASE=0xDEADBEEF all
Andre Przywarae917ec82021-09-03 15:01:30 +0100676clean_build PLAT=rpi4 $(common_flags) SMC_PCI_SUPPORT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200677
Zelalemc9531f82020-08-04 15:37:08 -0500678# A113D (AXG) platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500679clean_build PLAT=axg $(common_flags) SPD=opteed
680clean_build PLAT=axg $(common_flags) AML_USE_ATOS=1
Zelalemc9531f82020-08-04 15:37:08 -0500681
Stephan Gerhold141a7662021-12-07 20:42:14 +0100682# QTI MSM8916 platform
683clean_build PLAT=msm8916 $(common_flags)
684
Fathi Boudra422bf772019-12-02 11:10:16 +0200685cd ..