blob: 322b037556f7259aef4a9385db0f2f1cd67115ff [file] [log] [blame]
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -05001#!/usr/bin/env bash
Fathi Boudra422bf772019-12-02 11:10:16 +02002#
Govindraj Raja95f855c2023-03-01 13:11:42 +00003# Copyright (c) 2019-2023, Arm Limited. All rights reserved.
Fathi Boudra422bf772019-12-02 11:10:16 +02004#
5# SPDX-License-Identifier: BSD-3-Clause
6#
7
8#
9# This script builds the TF in different configs.
10# Rather than telling cov-build to build TF using a simple 'make all' command,
11# the goal here is to combine several build flags to analyse more of our source
12# code in a single 'build'. The Coverity Scan service does not have the notion
13# of separate types of build - there is just one linear sequence of builds in
14# the project history.
15#
16
17# Bail out as soon as an error is encountered.
18set -e
19
20TF_SOURCES=$1
21if [ ! -d "$TF_SOURCES" ]; then
22 echo "ERROR: '$TF_SOURCES' does not exist or is not a directory"
23 echo "Usage: $(basename "$0") <trusted-firmware-directory>"
24 exit 1
25fi
26
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050027containing_dir="$(readlink -f "$(dirname "$0")/")"
28. $containing_dir/common-def.sh
29
Fathi Boudra422bf772019-12-02 11:10:16 +020030# Get mbed TLS library code to build Trusted Firmware with Trusted Board Boot
31# support. The version of mbed TLS to use here must be the same as when
32# building TF in the usual context.
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050033if [ ! -d "$MBED_TLS_DIR" ]; then
34 git clone -q --depth 1 -b "$MBED_TLS_SOURCES_TAG" "$MBED_TLS_URL_REPO" "$MBED_TLS_DIR"
Fathi Boudra422bf772019-12-02 11:10:16 +020035fi
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050036
Fathi Boudra422bf772019-12-02 11:10:16 +020037cd "$TF_SOURCES"
38
39# Clean TF source dir to make sure we don't analyse temporary files.
40make distclean
41
42#
43# Build TF in different configurations to get as much coverage as possible
44#
45
Fathi Boudra422bf772019-12-02 11:10:16 +020046#
47# FVP platform
48# We'll use the following flags for all FVP builds.
49#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050050fvp_common_flags="$(common_flags) PLAT=fvp"
Fathi Boudra422bf772019-12-02 11:10:16 +020051
52# Try all possible SPDs.
53clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd
54clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd TSP_INIT_ASYNC=1 \
55 TSP_NS_INTR_ASYNC_PREEMPT=1
Manish V Badarkhe48ed0bf2023-06-28 09:33:16 +010056clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +020057clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tlkd
Manish V Badarkhee7528ff2023-07-01 10:20:05 +010058clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=pncd SPD_PNCD_NS_IRQ=126 \
59 SPD_PNCD_S_IRQ=15 FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +020060
Zelalemc9531f82020-08-04 15:37:08 -050061# Dualroot chain of trust.
62clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tspd COT=dualroot
63
laurenw-armf48e9d22022-04-22 11:30:13 -050064# FEAT_RME with CCA chain of trust.
Sandrine Bailleuxe30bd0c2022-08-31 14:49:17 +020065#
66# Note that we override PLAT_RSS_NOT_SUPPORTED build flag (which defaults to 1
67# on the Base AEM FVP) just to analyse the RSS communication driver code through
68# Coverity. In reality, RSS is not supported on FVP right now (or on any other
69# upstream platform, for that matter) so the resulting firmware would not be
70# functional.
Manish V Badarkhe21402bb2023-03-18 12:39:33 +000071clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} USE_ROMLIB=1 \
Sandrine Bailleuxe30bd0c2022-08-31 14:49:17 +020072 ENABLE_RME=1 MEASURED_BOOT=1 PLAT_RSS_NOT_SUPPORTED=0
laurenw-armf48e9d22022-04-22 11:30:13 -050073
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050074clean_build $fvp_common_flags SPD=trusty
75clean_build $fvp_common_flags SPD=trusty TRUSTY_SPD_WITH_GENERIC_SERVICES=1
Fathi Boudra422bf772019-12-02 11:10:16 +020076
Sona Mathewff9c2a72023-05-10 21:18:01 -050077# ERRATA ABI
78clean_build $fvp_common_flags ERRATA_ABI_SUPPORT=1
79
Fathi Boudra422bf772019-12-02 11:10:16 +020080# SDEI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050081clean_build $fvp_common_flags SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Fathi Boudra422bf772019-12-02 11:10:16 +020082
Zelalemc9531f82020-08-04 15:37:08 -050083# SDEI with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050084clean_build $fvp_common_flags SDEI_IN_FCONF=1 SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Zelalemc9531f82020-08-04 15:37:08 -050085
Zelalem4f3633e2021-06-18 11:53:47 -050086# PCI Service
87clean_build $fvp_common_flags SMC_PCI_SUPPORT=1
88
Zelalemc9531f82020-08-04 15:37:08 -050089# Secure interrupt descriptors with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050090clean_build $fvp_common_flags SEC_INT_DESC_IN_FCONF=1
Zelalemc9531f82020-08-04 15:37:08 -050091
Fathi Boudra422bf772019-12-02 11:10:16 +020092# Without coherent memory
93clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd USE_COHERENT_MEM=0
94
95# Using PSCI extended State ID format rather than the original format
96clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd PSCI_EXTENDED_STATE_ID=1 \
97 ARM_RECOM_STATE_ID_ENC=1
98
99# Alternative boot flows (This changes some of the platform initialisation code)
Elizabeth Ho4cdb2f42023-07-11 12:27:14 +0100100clean_build $fvp_common_flags EL3_PAYLOAD_BASE=0x80000000
Fathi Boudra422bf772019-12-02 11:10:16 +0200101clean_build $fvp_common_flags PRELOADED_BL33_BASE=0x80000000
102
103# Using the SP804 timer instead of the Generic Timer
104clean_build $fvp_common_flags FVP_USE_SP804_TIMER=1
105
106# Using the CCN driver and multi cluster topology
107clean_build $fvp_common_flags FVP_CLUSTER_COUNT=4
108
109# PMF
110clean_build $fvp_common_flags ENABLE_PMF=1
111
112# stack protector
113clean_build $fvp_common_flags ENABLE_STACK_PROTECTOR=strong
114
115# AArch32 build
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500116clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200117 ARCH=aarch32 AARCH32_SP=sp_min \
118 RESET_TO_SP_MIN=1 PRELOADED_BL33_BASE=0x80000000
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500119clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200120 ARCH=aarch32 AARCH32_SP=sp_min
121
122# Xlat tables lib version 1 (AArch64 and AArch32)
123clean_build $fvp_common_flags ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500124clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200125 ARCH=aarch32 AARCH32_SP=sp_min ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
126
Zelalemc9531f82020-08-04 15:37:08 -0500127# SPM support based on Management Mode Interface Specification
Manish Pandeyaa9a03b2021-11-17 10:03:17 +0000128clean_build $fvp_common_flags SPM_MM=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0
Fathi Boudra422bf772019-12-02 11:10:16 +0200129
Zelalemc9531f82020-08-04 15:37:08 -0500130# SPM support with TOS(optee) as SPM sitting at S-EL1
131clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0
132
Shruti Gupta8cc89b92022-08-09 12:23:46 +0100133# SPM support with SPM at EL3 and TSP at S-EL1
134clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 CTX_INCLUDE_EL2_REGS=0 EL3_EXCEPTION_HANDLING=0 \
135 SPD=spmd SPMD_SPM_AT_SEL2=0 SPMC_AT_EL3=1 \
136 ARM_SPMC_MANIFEST_DTS=plat/arm/board/fvp/fdts/fvp_tsp_sp_manifest.dts
137
Zelalemc9531f82020-08-04 15:37:08 -0500138# SPM support with Secure hafnium as SPM sitting at S-EL2
139# SP_LAYOUT_FILE is used only during FIP creation but build won't progress
140# if we have NULL value to it, so passing a dummy string.
141clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=1 ARM_ARCH_MINOR=4 \
Max Shvetsov44d2a702021-02-18 16:41:45 +0000142 CTX_INCLUDE_EL2_REGS=1 SP_LAYOUT_FILE=dummy
Fathi Boudra422bf772019-12-02 11:10:16 +0200143
Marc Bonnici502fdaa2022-01-10 12:38:23 +0000144# SPM support with SPM sitting at EL3
145clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0 SPMC_AT_EL3=1
146
Fathi Boudra422bf772019-12-02 11:10:16 +0200147#BL2 at EL3 support
Maksims Svecovs7a0da522023-03-06 16:28:27 +0000148clean_build $fvp_common_flags RESET_TO_BL2=1
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500149clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Maksims Svecovs7a0da522023-03-06 16:28:27 +0000150 ARCH=aarch32 AARCH32_SP=sp_min RESET_TO_BL2=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200151
Zelalemc9531f82020-08-04 15:37:08 -0500152# RAS Extension Support
Manish Pandeyc1fa25b2023-02-16 17:35:36 +0000153clean_build $fvp_common_flags EL3_EXCEPTION_HANDLING=1 ENABLE_FEAT_RAS=1 \
154 RAS_FFH_SUPPORT=1 FAULT_INJECTION_SUPPORT=1 HANDLE_EA_EL3_FIRST_NS=1 \
Manish Pandey010e9b42023-04-24 15:49:27 +0100155 SDEI_SUPPORT=1 PLATFORM_TEST_RAS_FFH=1
Zelalemc9531f82020-08-04 15:37:08 -0500156
Manish Pandeyfd4c6b72023-04-24 10:29:52 +0100157# EA handled in EL3 first
158clean_build $fvp_common_flags HANDLE_EA_EL3_FIRST_NS=1 PLATFORM_TEST_EA_FFH=1
159
Zelalemc9531f82020-08-04 15:37:08 -0500160# Hardware Assisted Coherency(DynamIQ)
161clean_build $fvp_common_flags FVP_CLUSTER_COUNT=1 FVP_MAX_CPUS_PER_CLUSTER=8 \
162 HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0
163
164# Pointer Authentication Support
165clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 \
166 ARM_ARCH_MINOR=5 EL3_EXCEPTION_HANDLING=1 BRANCH_PROTECTION=1 SDEI_SUPPORT=1 SPD=tspd TSP_NS_INTR_ASYNC_PREEMPT=1
167
168# Undefined Behaviour Sanitizer
169# Building with UBSAN SANITIZE_UB=on increases the executable size.
170# Hence it is only properly supported in bl31 with RESET_TO_BL31 enabled
171make $fvp_common_flags clean
172make $fvp_common_flags SANITIZE_UB=on RESET_TO_BL31=1 bl31
173
174# debugfs feature
175clean_build $fvp_common_flags DEBUG=1 USE_DEBUGFS=1
176
177# MPAM feature
178clean_build $fvp_common_flags ENABLE_MPAM_FOR_LOWER_ELS=1
179
180# Using GICv3.1 driver with extended PPI and SPI range
181clean_build $fvp_common_flags GIC_EXT_INTID=1
182
183# Using GICv4 features with extended PPI and SPI range
184clean_build $fvp_common_flags GIC_ENABLE_V4_EXTN=1 GIC_EXT_INTID=1
185
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100186# Measured Boot
laurenw-arm8531e702022-06-09 15:32:37 -0500187clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} MBOOT_EL_HASH_ALG=sha256 MEASURED_BOOT=1 USE_ROMLIB=1
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100188
Manish V Badarkhef43e3f52022-06-21 20:37:25 +0100189# DRTM
190clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} TPM_HASH_ALG=sha256 DRTM_SUPPORT=1 USE_ROMLIB=1
191
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100192# CoT descriptors in device tree
Manish V Badarkhe81102d12020-10-05 08:02:30 +0100193clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} COT_DESC_IN_DTB=1 USE_ROMLIB=1
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100194
Chris Kayf4789fe2023-06-12 15:52:28 +0100195# PSA FWU support
196clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_GPT_SUPPORT=1 PSA_FWU_SUPPORT=1 USE_ROMLIB=1 FVP_TRUSTED_SRAM_SIZE=384
Manish V Badarkhe107c8e32021-08-02 19:49:32 +0100197
johpow01153c8b22021-11-03 14:38:36 -0500198# SME and HCX features
199clean_build $fvp_common_flags ENABLE_SME_FOR_NS=1 ENABLE_FEAT_HCX=1
200
Jayanth Dodderi Chidanand41edd012023-01-12 14:50:34 +0000201# SME2
202clean_build $fvp_common_flags ENABLE_SME2_FOR_NS=1 ENABLE_SME_FOR_NS=1 ENABLE_FEAT_HCX=1
203
Jayanth Dodderi Chidanand84da1962022-04-11 11:38:44 +0100204# Architectural Feature Detection mechanism
205clean_build $fvp_common_flags FEATURE_DETECTION=1
206
Manish Pandeye3561fd2023-01-05 10:46:25 +0000207# RNG trap feature
208clean_build $fvp_common_flags ENABLE_FEAT_RNG=1 ENABLE_FEAT_RNG_TRAP=1
209
Chris Kayf4789fe2023-06-12 15:52:28 +0100210# OPTEE_ALLOW_SMC_LOAD feature
211clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed OPTEE_ALLOW_SMC_LOAD=1 PLAT_XLAT_TABLES_DYNAMIC=1 FVP_TRUSTED_SRAM_SIZE=384
Jeffrey Kardatzke09e18e22023-01-25 12:24:13 -0800212
Fathi Boudra422bf772019-12-02 11:10:16 +0200213#
214# Juno platform
215# We'll use the following flags for all Juno builds.
216#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500217juno_common_flags="$(common_flags) PLAT=juno"
Fathi Boudra422bf772019-12-02 11:10:16 +0200218clean_build $juno_common_flags SPD=tspd ${ARM_TBB_OPTIONS}
Elizabeth Ho4cdb2f42023-07-11 12:27:14 +0100219clean_build $juno_common_flags EL3_PAYLOAD_BASE=0x80000000
Madhukar Pappireddydcb31f62021-05-06 11:36:36 -0500220clean_build $juno_common_flags ENABLE_STACK_PROTECTOR=strong ARM_ETHOSN_NPU_DRIVER=1
Mikael Olssoncd8c7822023-02-28 17:30:44 +0100221clean_build $juno_common_flags ${ARM_TBB_OPTIONS} ENABLE_STACK_PROTECTOR=strong ARM_ETHOSN_NPU_DRIVER=1 ARM_ETHOSN_NPU_TZMP1=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200222clean_build $juno_common_flags CSS_USE_SCMI_SDS_DRIVER=0
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500223
Leonardo Sandoval5163b562020-11-20 17:17:59 -0600224clean_build $juno_common_flags SPD=tspd ${ARM_TBB_OPTIONS} ARM_CRYPTOCELL_INTEG=1 CCSBROM_LIB_PATH=${CRYPTOCELL_LIB_PATH} KEY_SIZE=2048
Fathi Boudra422bf772019-12-02 11:10:16 +0200225
Jayanth Dodderi Chidanand055394a2022-10-19 09:20:20 +0100226# TRNG Service
227clean_build $juno_common_flags TRNG_SUPPORT=1
228
Fathi Boudra422bf772019-12-02 11:10:16 +0200229#
Fathi Boudra422bf772019-12-02 11:10:16 +0200230# System Guidance for Infrastructure platform RD-E1Edge
231#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500232make $(common_flags) PLAT=rde1edge ${ARM_TBB_OPTIONS} CSS_SGI_CHIP_COUNT=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500233
234#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530235# Reference Design platform RD-V1
Zelalemc9531f82020-08-04 15:37:08 -0500236#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530237make $(common_flags) PLAT=rdv1 ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500238
239#
Aditya Angadi61c54762021-01-04 09:30:52 +0530240# Reference Design platform RD-V1-MC
Zelalemc9531f82020-08-04 15:37:08 -0500241#
Aditya Angadi61c54762021-01-04 09:30:52 +0530242make $(common_flags) PLAT=rdv1mc ${ARM_TBB_OPTIONS} CSS_SGI_CHIP_COUNT=4 all
Zelalemc9531f82020-08-04 15:37:08 -0500243
244#
Vijayenthiran Subramaniama66de332020-11-23 14:20:14 +0530245# Reference Design Platform RD-N2
246#
247make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} all
Omkar Anand Kulkarnif6e268e2023-06-21 20:32:22 +0530248# RAS Extension Support
249make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} ENABLE_FEAT_RAS=1 \
250 RAS_FFH_SUPPORT=1 HANDLE_EA_EL3_FIRST_NS=1 SDEI_SUPPORT=1 SPM_MM=1 all
Vijayenthiran Subramaniama66de332020-11-23 14:20:14 +0530251
252#
Zelalemc9531f82020-08-04 15:37:08 -0500253# Neoverse N1 SDP platform
254#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500255make $(common_flags) PLAT=n1sdp ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500256
257#
258# FVP VE platform
259#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500260make $(common_flags) PLAT=fvp_ve AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500261 CROSS_COMPILE=arm-none-eabi- ARM_ARCH_MAJOR=7 \
262 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
263 FVP_HW_CONFIG_DTS=fdts/fvp-ve-Cortex-A5x1.dts all
264
265#
266# A5 DesignStart Platform
267#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500268make $(common_flags) PLAT=a5ds AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500269 ARM_ARCH_MAJOR=7 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
270 CROSS_COMPILE=arm-none-eabi- FVP_HW_CONFIG_DTS=fdts/a5ds.dts
271
272#
273# Corstone700 Platform
274#
275
276corstone700_common_flags="CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500277 $(common_flags) \
Zelalemc9531f82020-08-04 15:37:08 -0500278 PLAT=corstone700 \
279 ARCH=aarch32 \
280 RESET_TO_SP_MIN=1 \
281 AARCH32_SP=sp_min \
282 ARM_LINUX_KERNEL_AS_BL33=0 \
283 ARM_PRELOADED_DTB_BASE=0x80400000 \
284 ENABLE_PIE=1 \
Zelalemc9531f82020-08-04 15:37:08 -0500285 ENABLE_STACK_PROTECTOR=all \
286 all"
287
288echo "Info: Building Corstone700 FVP ..."
289
290make TARGET_PLATFORM=fvp ${corstone700_common_flags}
291
292echo "Info: Building Corstone700 FPGA ..."
293
294make TARGET_PLATFORM=fpga ${corstone700_common_flags}
295
296#
297# Arm internal FPGA port
298#
Andre Przywara13361b62022-04-26 11:16:55 +0100299make PLAT=arm_fpga $(common_flags release) \
300 FPGA_PRELOADED_DTB_BASE=0x88000000 PRELOADED_BL33_BASE=0x82080000 all
Zelalemc9531f82020-08-04 15:37:08 -0500301
302#
Usama Arifcba711d2021-08-04 15:53:42 +0100303# Total Compute platforms
Zelalemc9531f82020-08-04 15:37:08 -0500304#
Usama Arifcba711d2021-08-04 15:53:42 +0100305make $(common_flags) PLAT=tc TARGET_PLATFORM=1 ${ARM_TBB_OPTIONS} all
Tamas Banaf5a6632022-09-21 16:02:39 +0200306make $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} MEASURED_BOOT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200307
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530308#
309# Morello platform
310#
Chandni Cherukuricbd45962021-12-12 13:37:33 +0530311clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=fvp ${ARM_TBB_OPTIONS}
312clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=soc ${ARM_TBB_OPTIONS}
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530313
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100314#
Vishnu Banavath2cb72b32022-01-20 14:27:55 +0000315# corstone1000 Platform
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100316#
317
318make $(common_flags) \
Vishnu Banavath2cb72b32022-01-20 14:27:55 +0000319 PLAT=corstone1000 \
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100320 SPD=spmd \
321 TARGET_PLATFORM=fpga \
322 ENABLE_STACK_PROTECTOR=strong \
323 ENABLE_PIE=1 \
Maksims Svecovs7a0da522023-03-06 16:28:27 +0000324 RESET_TO_BL2=1 \
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100325 SPMD_SPM_AT_SEL2=0 \
326 ${ARM_TBB_OPTIONS} \
327 CREATE_KEYS=1 \
328 COT=tbbr \
329 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
330 bl2 \
331 bl31
332
johpow01aac58582021-10-05 16:51:34 -0500333#
334# FVP-R platform
335#
336clean_build $(common_flags) PLAT=fvp_r ${ARM_TBB_OPTIONS} ENABLE_STACK_PROTECTOR=all
337
Fathi Boudra422bf772019-12-02 11:10:16 +0200338# Partners' platforms.
339# Enable as many features as possible.
340# We don't need to clean between each build here because we only do one build
341# per platform so we don't hit the build flags dependency problem.
Fathi Boudra422bf772019-12-02 11:10:16 +0200342
Manish Pandey9c0ee742021-07-08 09:55:59 +0100343# Platforms from Mediatek
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500344make PLAT=mt8173 $(common_flags) all
345make PLAT=mt8183 $(common_flags) all
Rex-BC Chen946cace2021-11-17 10:15:42 +0800346make PLAT=mt8186 $(common_flags) COREBOOT=1 all
Bo-Chen Chen4d63afd2022-08-30 16:34:57 +0800347make PLAT=mt8188 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500348make PLAT=mt8192 $(common_flags) COREBOOT=1 all
Manish Pandey9c0ee742021-07-08 09:55:59 +0100349make PLAT=mt8195 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500350
351# Platforms from Qualcomm
352make PLAT=sc7180 $(common_flags) COREBOOT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200353
Zelalemc9531f82020-08-04 15:37:08 -0500354make PLAT=rk3288 CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500355 $(common_flags) ARCH=aarch32 AARCH32_SP=sp_min all
Madhukar Pappireddyd491ad02020-12-03 10:37:05 -0600356make PLAT=rk3368 $(common_flags) COREBOOT=1 \
357 ENABLE_STACK_PROTECTOR=strong all
358make PLAT=rk3399 $(common_flags) COREBOOT=1 PLAT_RK_DP_HDCP=1 \
359 ENABLE_STACK_PROTECTOR=strong all
360make PLAT=rk3328 $(common_flags) COREBOOT=1 PLAT_RK_SECURE_DDR_MINILOADER=1 \
361 ENABLE_STACK_PROTECTOR=strong all
362make PLAT=px30 $(common_flags) PLAT_RK_SECURE_DDR_MINILOADER=1 \
363 ENABLE_STACK_PROTECTOR=strong all
Fathi Boudra422bf772019-12-02 11:10:16 +0200364
365# Although we do several consecutive builds for the Tegra platform below, we
366# don't need to clean between each one because the Tegra makefiles specify
367# a different build directory per SoC.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500368make PLAT=tegra TARGET_SOC=t210 $(common_flags) all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500369make PLAT=tegra TARGET_SOC=t186 $(common_flags) all
370make PLAT=tegra TARGET_SOC=t194 $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200371
372# For the Xilinx platform, artificially increase the extents of BL31 memory
373# (using the platform-specific build options ZYNQMP_ATF_MEM_{BASE,SIZE}).
374# If we keep the default values, BL31 doesn't fit when it is built with all
375# these build flags.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500376make PLAT=zynqmp $(common_flags) \
Fathi Boudra422bf772019-12-02 11:10:16 +0200377 RESET_TO_BL31=1 SPD=tspd \
Zelalem4f3633e2021-06-18 11:53:47 -0500378 SDEI_SUPPORT=1 \
Fathi Boudra422bf772019-12-02 11:10:16 +0200379 ZYNQMP_ATF_MEM_BASE=0xFFFC0000 ZYNQMP_ATF_MEM_SIZE=0x00040000 \
380 all
381
Zelalemc9531f82020-08-04 15:37:08 -0500382# Build both for silicon (default) and virtual QEMU platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500383clean_build PLAT=versal $(common_flags)
384clean_build PLAT=versal $(common_flags) VERSAL_PLATFORM=versal_virt
Zelalemc9531f82020-08-04 15:37:08 -0500385
Michal Simek0f135242022-09-20 15:24:56 +0200386# Build Xilinx Versal NET platform
387clean_build PLAT=versal_net $(common_flags)
388
Jayanth Dodderi Chidanand0a2dd1e2022-10-27 11:17:37 +0100389# Build Xilinx Versal NET without Platform Management support
390clean_build PLAT=versal_net $(common_flags) TFA_NO_PM=1
391
Zelalemc9531f82020-08-04 15:37:08 -0500392# Platforms from Allwinner
Andre Przywara3a78c102022-04-26 11:08:54 +0100393clean_build PLAT=sun50i_a64 $(common_flags release) all
394clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_NATIVE=0 all
395clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_SCPI=0 all
396clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_AMEND_DTB=1 all
Andre Przywaracf78a512021-09-03 14:59:38 +0100397clean_build PLAT=sun50i_h6 $(common_flags) all
398clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_NATIVE=0 all
399clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_SCPI=0 all
400clean_build PLAT=sun50i_h616 $(common_flags) all
401clean_build PLAT=sun50i_r329 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500402
403# Platforms from i.MX
404make AARCH32_SP=optee ARCH=aarch32 ARM_ARCH_MAJOR=7 ARM_CORTEX_A7=yes \
405 CROSS_COMPILE=arm-none-eabi- PLAT=warp7 ${TBB_OPTIONS} \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500406 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500407make AARCH32_SP=optee ARCH=aarch32 CROSS_COMPILE=arm-none-eabi- PLAT=picopi \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500408 $(common_flags) all
Ying-Chun Liu (PaulLiu)f6528982021-11-17 17:20:00 +0800409make PLAT=imx8mm $(common_flags) NEED_BL2=yes MEASURED_BOOT=1 \
laurenw-arm8531e702022-06-09 15:32:37 -0500410 MBOOT_EL_HASH_ALG=sha256 ${TBB_OPTIONS} all
Madhukar Pappireddyc3ec06b2022-05-18 11:15:16 -0500411make PLAT=imx8mn $(common_flags) SDEI_SUPPORT=1 all
Ying-Chun Liu (PaulLiu)413e6102021-09-14 00:22:08 +0800412make PLAT=imx8mp $(common_flags) NEED_BL2=yes ${TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500413
Jacky Baib6cecc82021-06-07 09:49:46 +0800414# Due to the limited OCRAM space that can be used for TF-A, build test
415# will report failure caused by too small RAM size, so comment out the
416# build test for imx8mq in CI. It can also resolve the following ticket:
Zelalemc9531f82020-08-04 15:37:08 -0500417# https://developer.trustedfirmware.org/T626
Jacky Baib6cecc82021-06-07 09:49:46 +0800418#make PLAT=imx8mq $(common_flags release) all
Zelalemc9531f82020-08-04 15:37:08 -0500419
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500420make PLAT=imx8qm $(common_flags) all
421make PLAT=imx8qx $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500422
Jacky Bai87091a62023-06-21 16:25:12 +0800423make PLAT=imx93 $(common_flags) all
424
Olivier Deprezbac70192021-04-02 08:55:36 +0200425# Platforms for NXP Layerscape
Jiafei Pane48e56c2021-09-30 10:32:54 +0800426nxp_sb_flags="TRUSTED_BOARD_BOOT=1 CST_DIR=$(pwd) SPD=opteed"
427nxp_sb_fuse_flags="${nxp_sb_flags} FUSE_PROG=1"
428
429# Platform lx2
Olivier Deprezbac70192021-04-02 08:55:36 +0200430make PLAT=lx2160aqds $(common_flags) all
431make PLAT=lx2160ardb $(common_flags) all
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500432
433#CSF Based CoT:
Jiafei Pane48e56c2021-09-30 10:32:54 +0800434clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
435 $nxp_sb_fuse_flags DDR_PHY_BIN_PATH=$(pwd)
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500436
437#X509 Based CoT
Jiafei Pane48e56c2021-09-30 10:32:54 +0800438clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
439 $nxp_sb_flags GENERATE_COT=1 \
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500440 MBEDTLS_DIR=$(pwd)/mbedtls
441
442#BOOT_MODE=emmc and Stack protector
Jiafei Pane48e56c2021-09-30 10:32:54 +0800443clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=emmc \
444 $nxp_sb_fuse_flags ENABLE_STACK_PROTECTOR=strong
445
446# Platform ls1028ardb
447clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor
448clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc
449clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd
450
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800451# ls1028a Secure Boot
Jiafei Pane48e56c2021-09-30 10:32:54 +0800452clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor $nxp_sb_fuse_flags
453clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
454clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
Olivier Deprezbac70192021-04-02 08:55:36 +0200455
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800456# Platform ls1043ardb
457clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor
458clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand
459clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd
460
461# ls1043ardb Secure Boot
462clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
463clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
464clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
465
Jiafei Panbd0c22a2022-01-29 00:04:44 +0800466# ls1046ardb Secure Boot
467clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
468clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
469clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
470
471# ls1046afrwy Secure Boot
472clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
473clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
474
475# ls1046aqds Secure Boot
476clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
477clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
478clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
479clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
480
Jiafei Pan332cd792022-02-24 16:44:48 +0800481# ls1088ardb Secure Boot
482clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
483clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
484
485# ls1088aqds Secure Boot
486clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
487clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
488clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
489
Zelalemc9531f82020-08-04 15:37:08 -0500490# Platforms from Intel
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500491make PLAT=stratix10 $(common_flags) all
492make PLAT=agilex $(common_flags) all
Sieu Mun Tang9081bac2023-05-29 18:08:24 +0800493make PLAT=agilex5 $(common_flags) all
Sieu Mun Tang03b57362022-03-05 01:54:59 +0800494make PLAT=n5x $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500495
496# Platforms from Broadcom
Madhukar Pappireddy97ad2582021-11-15 10:29:23 -0600497clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t \
498 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 DRIVER_I2C_ENABLE=1
499clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t-ns3 \
500 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 USE_USB=yes
Zelalemc9531f82020-08-04 15:37:08 -0500501
502# Platforms from Marvell
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500503make PLAT=a3700 $(common_flags) SCP_BL2=/dev/null CM3_SYSTEM_RESET=1 \
Manish Pandey9ef33c52022-10-25 16:41:49 +0100504 A3720_DB_PM_WAKEUP_SRC=1 HANDLE_EA_EL3_FIRST_NS=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500505
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600506# Source files from mv-ddr-marvell repository are necessary
507# to build below four platforms
Manish Pandey7c1e7452021-11-05 12:54:15 +0000508wget https://downloads.trustedfirmware.org/tf-a/mv-ddr-marvell/mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
509tar -xzf mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600510mv mv-ddr-marvell drivers/marvell/mv_ddr
Zelalemc9531f82020-08-04 15:37:08 -0500511
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600512# These platforms from Marvell have dependency on GCC-6.2.1 toolchain
Pali Rohár8f890402021-07-19 13:48:05 +0200513make PLAT=a80x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200514 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200515make PLAT=a80x0_mcbin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200516 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200517make PLAT=a70x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200518 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200519make PLAT=a70x0_amc DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200520 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Robert Markodf3319e2021-10-20 11:01:12 +0200521make PLAT=a70x0_mochabin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
522 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200523make PLAT=a80x0_puzzle DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200524 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200525make PLAT=t9130 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200526 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500527make PLAT=t9130_cex7_eval DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
528 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500529
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600530# Removing the source files
531rm -rf drivers/marvell/mv_ddr 2> /dev/null
Zelalemc9531f82020-08-04 15:37:08 -0500532
533# Platforms from Meson
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500534make PLAT=gxbb $(common_flags) all
535make PLAT=gxl $(common_flags) all
536make PLAT=g12a $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500537
538# Platforms from Renesas
539# Renesas R-Car D3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500540clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500541 BL33=Makefile LIFEC_DBSC_PROTECT_ENABLE=0 LSI=D3 \
542 MBEDTLS_DIR=$(pwd)/mbedtls PMIC_ROHM_BD9571=0 \
543 RCAR_AVS_SETTING_ENABLE=0 SPD=none RCAR_LOSSY_ENABLE=0 \
544 RCAR_SA0_SIZE=0 RCAR_SYSTEM_SUSPEND=0 TRUSTED_BOARD_BOOT=1
545
546# Renesas R-Car H3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500547clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500548 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3 \
549 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
550 RCAR_DRAM_SPLIT=1 RCAR_GEN3_ULCB=1 SPD=opteed \
551 TRUSTED_BOARD_BOOT=1
552
553# Renesas R-Car H3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500554clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500555 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3N \
556 SPD=opteed TRUSTED_BOARD_BOOT=1
557
558# Renesas R-Car M3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500559clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500560 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3 \
561 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
562 RCAR_DRAM_SPLIT=2 RCAR_GEN3_ULCB=1 SPD=opteed \
563 TRUSTED_BOARD_BOOT=1
564
565# Renesas R-Car M3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500566clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500567 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3N \
568 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
569 RCAR_GEN3_ULCB=1 SPD=opteed TRUSTED_BOARD_BOOT=1
570
571# Renesas R-Car E3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500572clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500573 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=E3 \
574 RCAR_AVS_SETTING_ENABLE=0 RCAR_DRAM_DDR3L_MEMCONF=0 \
575 RCAR_SA0_SIZE=0 SPD=opteed TRUSTED_BOARD_BOOT=1
576
577# Renesas R-Car V3M Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500578clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500579 MBEDTLS_DIR=$(pwd)/mbedtls BL33=Makefile LSI=V3M MACHINE=eagle \
580 PMIC_ROHM_BD9571=0 RCAR_DRAM_SPLIT=0 RCAR_SYSTEM_SUSPEND=0 \
581 AVS_SETTING_ENABLE=0 SPD=none TRUSTED_BOARD_BOOT=1
582
Zelalemf4299672021-01-29 12:52:59 -0600583# Renesas HiHope RZ/G2M development kit
584clean_build PLAT=rzg $(common_flags) \
585 MBEDTLS_DIR=$(pwd)/mbedtls LSI=G2M \
586 RCAR_DRAM_SPLIT=2 RCAR_LOSSY_ENABLE=1 SPD=none
587
Zelalemc9531f82020-08-04 15:37:08 -0500588# Platforms from ST
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100589stm32mp1_common_flags="$(common_flags) \
590 ARCH=aarch32 \
591 ARM_ARCH_MAJOR=7 \
592 CROSS_COMPILE=arm-none-eabi- \
593 ENABLE_STACK_PROTECTOR=strong \
594 PLAT=stm32mp1"
595
Yann Gautiera69cf792021-09-01 11:19:01 +0200596# STM32MP1 SDMMC boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000597make ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200598 BUILD_PLAT=build/stm32mp1-sdmmc/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100599 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200600
601# STM32MP1 eMMC boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000602make ${stm32mp1_common_flags} STM32MP_EMMC=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200603 BUILD_PLAT=build/stm32mp1-emmc/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100604 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200605
606# STM32MP1 Raw NAND boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000607make ${stm32mp1_common_flags} STM32MP_RAW_NAND=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200608 BUILD_PLAT=build/stm32mp1-nand/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100609 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200610
611# STM32MP1 SPI NAND boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000612make ${stm32mp1_common_flags} STM32MP_SPI_NAND=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200613 BUILD_PLAT=build/stm32mp1-snand/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100614 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200615
616# STM32MP1 SPI NOR boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000617make ${stm32mp1_common_flags} STM32MP_SPI_NOR=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200618 BUILD_PLAT=build/stm32mp1-snor/debug \
Govindraj Raja95f855c2023-03-01 13:11:42 +0000619 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200620
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100621# STM32MP1 UART boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000622make ${stm32mp1_common_flags} STM32MP_UART_PROGRAMMER=1 \
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100623 BUILD_PLAT=build/stm32mp1-uart/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100624 AARCH32_SP=sp_min bl2 bl32
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100625
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200626# STM32MP1 USB boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000627make ${stm32mp1_common_flags} STM32MP_USB_PROGRAMMER=1 \
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200628 BUILD_PLAT=build/stm32mp1-usb/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100629 AARCH32_SP=sp_min bl2 bl32
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200630
Lionel Debieve8f464c02022-10-13 09:25:45 +0200631# STM32MP1 TBBR
Govindraj Raja95f855c2023-03-01 13:11:42 +0000632make ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
Yann Gautier741e8492022-11-14 19:04:27 +0100633 BUILD_PLAT=build/stm32mp1-sdmmc-tbbr/debug \
Lionel Debieve8f464c02022-10-13 09:25:45 +0200634 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100635 AARCH32_SP=sp_min bl2 bl32
Lionel Debieve8f464c02022-10-13 09:25:45 +0200636
Govindraj Raja95f855c2023-03-01 13:11:42 +0000637stm32mp13_common_flags="${stm32mp1_common_flags} \
638 AARCH32_SP=optee \
639 STM32MP13=1"
640
Yann Gautier773c5502022-03-10 17:24:47 +0100641# STM32MP13 SDMMC boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000642make ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100643 BUILD_PLAT=build/stm32mp1-mp13-sdmmc/debug bl2
Yann Gautier773c5502022-03-10 17:24:47 +0100644
Lionel Debieve8f464c02022-10-13 09:25:45 +0200645# STM32MP13 TBBR
Govindraj Raja95f855c2023-03-01 13:11:42 +0000646make ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Lionel Debieve8f464c02022-10-13 09:25:45 +0200647 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100648 BUILD_PLAT=build/stm32mp1-mp13-sdmmc-tbbr/debug bl2
Lionel Debieve8f464c02022-10-13 09:25:45 +0200649
Yann Gautiera66e5012022-12-13 13:52:35 +0100650# STM32MP13 TBBR DECRYPTION AES GCM
Govindraj Raja95f855c2023-03-01 13:11:42 +0000651make ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Yann Gautiera66e5012022-12-13 13:52:35 +0100652 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
653 DECRYPTION_SUPPORT=aes_gcm ENCRYPT_BL32=1 \
654 BUILD_PLAT=build/stm32mp1-mp13-sdmmc-tbbr-dec/debug bl2
655
Zelalemc9531f82020-08-04 15:37:08 -0500656# Platforms from TI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500657make PLAT=k3 $(common_flags) all
Hari Nagalladadd89f2022-08-30 12:10:00 -0500658make PLAT=k3 TARGET_BOARD=j784s4 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500659
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500660clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS}
Zelalemc9531f82020-08-04 15:37:08 -0500661# Use GICV3 driver
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500662clean_build PLAT=qemu $(common_flags) QEMU_USE_GIC_DRIVER=QEMU_GICV3 \
Zelalemc9531f82020-08-04 15:37:08 -0500663 ENABLE_STACK_PROTECTOR=strong
Dongjiu Geng72819ee2023-06-16 18:48:57 +0800664# Use GICV3 driver with SDEI support
665clean_build PLAT=qemu $(common_flags) QEMU_USE_GIC_DRIVER=QEMU_GICV3 \
666 ENABLE_STACK_PROTECTOR=strong SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Zelalemc9531f82020-08-04 15:37:08 -0500667# Use encrypted FIP feature.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500668clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500669 BL32_RAM_LOCATION=tdram DECRYPTION_SUPPORT=aes_gcm ENCRYPT_BL31=1 \
670 ENCRYPT_BL32=1 FW_ENC_STATUS=0 SPD=opteed
Jens Wiklander1a9c2be2021-11-26 09:56:55 +0100671# QEMU with SPMD support
672clean_build PLAT=qemu $(common_flags) BL32=Makefile \
673 BL32_RAM_LOCATION=tdram ARM_BL31_IN_DRAM=1 \
674 SPD=spmd CTX_INCLUDE_EL2_REGS=0 SPMD_SPM_AT_SEL2=0 SPMC_OPTEE=1
Ruchika Gupta86e7f682022-04-12 10:25:46 +0530675# Measured Boot
laurenw-arm8531e702022-06-09 15:32:37 -0500676clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} MBOOT_EL_HASH_ALG=sha256 MEASURED_BOOT=1
Zelalemc9531f82020-08-04 15:37:08 -0500677
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500678clean_build PLAT=qemu_sbsa $(common_flags)
Fathi Boudra422bf772019-12-02 11:10:16 +0200679
Zelalemd86e8762020-08-21 18:24:28 -0500680# QEMU with SPM support
681clean_build PLAT=qemu_sbsa $(common_flags) BL32=Makefile SPM_MM=1 \
Paul Sokolovskycf9fe862023-01-02 16:22:21 +0300682 EL3_EXCEPTION_HANDLING=1 ENABLE_SME_FOR_NS=0 ENABLE_SVE_FOR_NS=0
Zelalemd86e8762020-08-21 18:24:28 -0500683
Fathi Boudra422bf772019-12-02 11:10:16 +0200684# For hikey enable PMF to include all files in the platform port
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500685make PLAT=hikey $(common_flags) ${TBB_OPTIONS} ENABLE_PMF=1 all
686make PLAT=hikey960 $(common_flags) ${TBB_OPTIONS} all
Lukas Haneld0752392022-10-13 11:13:19 +0200687make PLAT=hikey960 $(common_flags) ${TBB_OPTIONS} SPD=spmd SPMC_AT_EL3=1 \
688 SPMD_SPM_AT_SEL2=0 BL32=optee PLAT_SP_MANIFEST_DTS=foo NEED_FDT=no all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500689make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200690
Zelalemc9531f82020-08-04 15:37:08 -0500691# Platforms from Socionext
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500692clean_build PLAT=uniphier $(common_flags) ${TBB_OPTIONS} SPD=tspd
693clean_build PLAT=uniphier $(common_flags) FIP_GZIP=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200694
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500695clean_build PLAT=synquacer $(common_flags) SPM_MM=1 \
Jassi Brar86080922022-06-27 14:16:34 -0500696 RESET_TO_BL31=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0 \
697 PRELOADED_BL33_BASE=0x0
Zelalemc9531f82020-08-04 15:37:08 -0500698
699# Support for SCP Message Interface protocol with platform specific drivers
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500700clean_build PLAT=synquacer $(common_flags) \
Jassi Brar86080922022-06-27 14:16:34 -0500701 RESET_TO_BL31=1 PRELOADED_BL33_BASE=0x0 SQ_USE_SCMI_DRIVER=1
Zelalemc9531f82020-08-04 15:37:08 -0500702
Jassi Brarb8c7ca02022-06-27 14:22:10 -0500703# Support for BL2 and TBBR
704clean_build PLAT=synquacer $(common_flags) \
705 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
706 SQ_USE_SCMI_DRIVER=1 SPD=opteed all
707
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500708make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200709
Zelalemc9531f82020-08-04 15:37:08 -0500710# Raspberry Pi Platforms
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500711make PLAT=rpi3 $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500712 ENABLE_STACK_PROTECTOR=strong PRELOADED_BL33_BASE=0xDEADBEEF all
Andre Przywarae917ec82021-09-03 15:01:30 +0100713clean_build PLAT=rpi4 $(common_flags) SMC_PCI_SUPPORT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200714
Zelalemc9531f82020-08-04 15:37:08 -0500715# A113D (AXG) platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500716clean_build PLAT=axg $(common_flags) SPD=opteed
717clean_build PLAT=axg $(common_flags) AML_USE_ATOS=1
Zelalemc9531f82020-08-04 15:37:08 -0500718
Stephan Gerhold141a7662021-12-07 20:42:14 +0100719# QTI MSM8916 platform
720clean_build PLAT=msm8916 $(common_flags)
Manish V Badarkhec540e622023-06-28 17:56:40 +0100721clean_build PLAT=msm8916 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
722 ARCH=aarch32 AARCH32_SP=sp_min
Stephan Gerhold998f0d62023-04-17 16:22:52 +0200723clean_build PLAT=msm8916 $(common_flags) SPD=tspd
Stephan Gerhold141a7662021-12-07 20:42:14 +0100724
Chia-Wei Wang7dcb0d02023-06-09 09:52:52 +0800725# Platforms from Aspeed
726clean_build PLAT=ast2700 $(common_flags) SPD=opteed
727
Fathi Boudra422bf772019-12-02 11:10:16 +0200728cd ..