blob: 42ae5a8a966d597030e31ed184d5a0ecfeb6d9e5 [file] [log] [blame]
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -05001#!/usr/bin/env bash
Fathi Boudra422bf772019-12-02 11:10:16 +02002#
Govindraj Raja95f855c2023-03-01 13:11:42 +00003# Copyright (c) 2019-2023, Arm Limited. All rights reserved.
Fathi Boudra422bf772019-12-02 11:10:16 +02004#
5# SPDX-License-Identifier: BSD-3-Clause
6#
7
8#
9# This script builds the TF in different configs.
10# Rather than telling cov-build to build TF using a simple 'make all' command,
11# the goal here is to combine several build flags to analyse more of our source
12# code in a single 'build'. The Coverity Scan service does not have the notion
13# of separate types of build - there is just one linear sequence of builds in
14# the project history.
15#
16
17# Bail out as soon as an error is encountered.
18set -e
19
20TF_SOURCES=$1
21if [ ! -d "$TF_SOURCES" ]; then
22 echo "ERROR: '$TF_SOURCES' does not exist or is not a directory"
23 echo "Usage: $(basename "$0") <trusted-firmware-directory>"
24 exit 1
25fi
26
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050027containing_dir="$(readlink -f "$(dirname "$0")/")"
28. $containing_dir/common-def.sh
29
Fathi Boudra422bf772019-12-02 11:10:16 +020030# Get mbed TLS library code to build Trusted Firmware with Trusted Board Boot
31# support. The version of mbed TLS to use here must be the same as when
32# building TF in the usual context.
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050033if [ ! -d "$MBED_TLS_DIR" ]; then
34 git clone -q --depth 1 -b "$MBED_TLS_SOURCES_TAG" "$MBED_TLS_URL_REPO" "$MBED_TLS_DIR"
Fathi Boudra422bf772019-12-02 11:10:16 +020035fi
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050036
Fathi Boudra422bf772019-12-02 11:10:16 +020037cd "$TF_SOURCES"
38
39# Clean TF source dir to make sure we don't analyse temporary files.
40make distclean
41
42#
43# Build TF in different configurations to get as much coverage as possible
44#
45
Fathi Boudra422bf772019-12-02 11:10:16 +020046#
47# FVP platform
48# We'll use the following flags for all FVP builds.
49#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050050fvp_common_flags="$(common_flags) PLAT=fvp"
Fathi Boudra422bf772019-12-02 11:10:16 +020051
52# Try all possible SPDs.
Chris Kayab29d432023-08-10 13:06:18 +000053clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram \
54 SPD=tspd FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +020055clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd TSP_INIT_ASYNC=1 \
56 TSP_NS_INTR_ASYNC_PREEMPT=1
Manish V Badarkhe48ed0bf2023-06-28 09:33:16 +010057clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed FVP_TRUSTED_SRAM_SIZE=384
Elizabeth Ho1a04df12023-07-27 16:06:24 +010058clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tlkd FVP_TRUSTED_SRAM_SIZE=384
Manish V Badarkhee7528ff2023-07-01 10:20:05 +010059clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=pncd SPD_PNCD_NS_IRQ=126 \
60 SPD_PNCD_S_IRQ=15 FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +020061
Zelalemc9531f82020-08-04 15:37:08 -050062# Dualroot chain of trust.
63clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tspd COT=dualroot
64
laurenw-armf48e9d22022-04-22 11:30:13 -050065# FEAT_RME with CCA chain of trust.
Sandrine Bailleuxe30bd0c2022-08-31 14:49:17 +020066#
67# Note that we override PLAT_RSS_NOT_SUPPORTED build flag (which defaults to 1
68# on the Base AEM FVP) just to analyse the RSS communication driver code through
69# Coverity. In reality, RSS is not supported on FVP right now (or on any other
70# upstream platform, for that matter) so the resulting firmware would not be
71# functional.
Manish V Badarkhece14ffc2023-07-27 09:28:23 +010072clean_build $fvp_common_flags USE_ROMLIB=1 MEASURED_BOOT=1 \
73 PLAT_RSS_NOT_SUPPORTED=0
laurenw-armf48e9d22022-04-22 11:30:13 -050074
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050075clean_build $fvp_common_flags SPD=trusty
76clean_build $fvp_common_flags SPD=trusty TRUSTY_SPD_WITH_GENERIC_SERVICES=1
Fathi Boudra422bf772019-12-02 11:10:16 +020077
Sona Mathewff9c2a72023-05-10 21:18:01 -050078# ERRATA ABI
79clean_build $fvp_common_flags ERRATA_ABI_SUPPORT=1
80
Fathi Boudra422bf772019-12-02 11:10:16 +020081# SDEI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050082clean_build $fvp_common_flags SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Fathi Boudra422bf772019-12-02 11:10:16 +020083
Zelalemc9531f82020-08-04 15:37:08 -050084# SDEI with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050085clean_build $fvp_common_flags SDEI_IN_FCONF=1 SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Zelalemc9531f82020-08-04 15:37:08 -050086
Zelalem4f3633e2021-06-18 11:53:47 -050087# PCI Service
88clean_build $fvp_common_flags SMC_PCI_SUPPORT=1
89
Zelalemc9531f82020-08-04 15:37:08 -050090# Secure interrupt descriptors with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050091clean_build $fvp_common_flags SEC_INT_DESC_IN_FCONF=1
Zelalemc9531f82020-08-04 15:37:08 -050092
Fathi Boudra422bf772019-12-02 11:10:16 +020093# Without coherent memory
94clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd USE_COHERENT_MEM=0
95
96# Using PSCI extended State ID format rather than the original format
97clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd PSCI_EXTENDED_STATE_ID=1 \
98 ARM_RECOM_STATE_ID_ENC=1
99
100# Alternative boot flows (This changes some of the platform initialisation code)
Elizabeth Ho4cdb2f42023-07-11 12:27:14 +0100101clean_build $fvp_common_flags EL3_PAYLOAD_BASE=0x80000000
Fathi Boudra422bf772019-12-02 11:10:16 +0200102clean_build $fvp_common_flags PRELOADED_BL33_BASE=0x80000000
103
104# Using the SP804 timer instead of the Generic Timer
105clean_build $fvp_common_flags FVP_USE_SP804_TIMER=1
106
107# Using the CCN driver and multi cluster topology
108clean_build $fvp_common_flags FVP_CLUSTER_COUNT=4
109
110# PMF
111clean_build $fvp_common_flags ENABLE_PMF=1
112
113# stack protector
114clean_build $fvp_common_flags ENABLE_STACK_PROTECTOR=strong
115
116# AArch32 build
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500117clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200118 ARCH=aarch32 AARCH32_SP=sp_min \
119 RESET_TO_SP_MIN=1 PRELOADED_BL33_BASE=0x80000000
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500120clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200121 ARCH=aarch32 AARCH32_SP=sp_min
122
123# Xlat tables lib version 1 (AArch64 and AArch32)
124clean_build $fvp_common_flags ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500125clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200126 ARCH=aarch32 AARCH32_SP=sp_min ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
127
Zelalemc9531f82020-08-04 15:37:08 -0500128# SPM support based on Management Mode Interface Specification
Manish Pandeyaa9a03b2021-11-17 10:03:17 +0000129clean_build $fvp_common_flags SPM_MM=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0
Fathi Boudra422bf772019-12-02 11:10:16 +0200130
Zelalemc9531f82020-08-04 15:37:08 -0500131# SPM support with TOS(optee) as SPM sitting at S-EL1
132clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0
133
Shruti Gupta8cc89b92022-08-09 12:23:46 +0100134# SPM support with SPM at EL3 and TSP at S-EL1
135clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 CTX_INCLUDE_EL2_REGS=0 EL3_EXCEPTION_HANDLING=0 \
136 SPD=spmd SPMD_SPM_AT_SEL2=0 SPMC_AT_EL3=1 \
137 ARM_SPMC_MANIFEST_DTS=plat/arm/board/fvp/fdts/fvp_tsp_sp_manifest.dts
138
Zelalemc9531f82020-08-04 15:37:08 -0500139# SPM support with Secure hafnium as SPM sitting at S-EL2
140# SP_LAYOUT_FILE is used only during FIP creation but build won't progress
141# if we have NULL value to it, so passing a dummy string.
142clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=1 ARM_ARCH_MINOR=4 \
Max Shvetsov44d2a702021-02-18 16:41:45 +0000143 CTX_INCLUDE_EL2_REGS=1 SP_LAYOUT_FILE=dummy
Fathi Boudra422bf772019-12-02 11:10:16 +0200144
Marc Bonnici502fdaa2022-01-10 12:38:23 +0000145# SPM support with SPM sitting at EL3
146clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0 SPMC_AT_EL3=1
147
Fathi Boudra422bf772019-12-02 11:10:16 +0200148#BL2 at EL3 support
Maksims Svecovs7a0da522023-03-06 16:28:27 +0000149clean_build $fvp_common_flags RESET_TO_BL2=1
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500150clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Maksims Svecovs7a0da522023-03-06 16:28:27 +0000151 ARCH=aarch32 AARCH32_SP=sp_min RESET_TO_BL2=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200152
Zelalemc9531f82020-08-04 15:37:08 -0500153# RAS Extension Support
Manish Pandeyc1fa25b2023-02-16 17:35:36 +0000154clean_build $fvp_common_flags EL3_EXCEPTION_HANDLING=1 ENABLE_FEAT_RAS=1 \
155 RAS_FFH_SUPPORT=1 FAULT_INJECTION_SUPPORT=1 HANDLE_EA_EL3_FIRST_NS=1 \
Manish Pandey010e9b42023-04-24 15:49:27 +0100156 SDEI_SUPPORT=1 PLATFORM_TEST_RAS_FFH=1
Zelalemc9531f82020-08-04 15:37:08 -0500157
Manish Pandeyfd4c6b72023-04-24 10:29:52 +0100158# EA handled in EL3 first
159clean_build $fvp_common_flags HANDLE_EA_EL3_FIRST_NS=1 PLATFORM_TEST_EA_FFH=1
160
Zelalemc9531f82020-08-04 15:37:08 -0500161# Hardware Assisted Coherency(DynamIQ)
162clean_build $fvp_common_flags FVP_CLUSTER_COUNT=1 FVP_MAX_CPUS_PER_CLUSTER=8 \
163 HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0
164
165# Pointer Authentication Support
166clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 \
167 ARM_ARCH_MINOR=5 EL3_EXCEPTION_HANDLING=1 BRANCH_PROTECTION=1 SDEI_SUPPORT=1 SPD=tspd TSP_NS_INTR_ASYNC_PREEMPT=1
168
169# Undefined Behaviour Sanitizer
170# Building with UBSAN SANITIZE_UB=on increases the executable size.
171# Hence it is only properly supported in bl31 with RESET_TO_BL31 enabled
172make $fvp_common_flags clean
173make $fvp_common_flags SANITIZE_UB=on RESET_TO_BL31=1 bl31
174
175# debugfs feature
176clean_build $fvp_common_flags DEBUG=1 USE_DEBUGFS=1
177
178# MPAM feature
179clean_build $fvp_common_flags ENABLE_MPAM_FOR_LOWER_ELS=1
180
181# Using GICv3.1 driver with extended PPI and SPI range
182clean_build $fvp_common_flags GIC_EXT_INTID=1
183
184# Using GICv4 features with extended PPI and SPI range
185clean_build $fvp_common_flags GIC_ENABLE_V4_EXTN=1 GIC_EXT_INTID=1
186
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100187# Measured Boot
laurenw-arm8531e702022-06-09 15:32:37 -0500188clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} MBOOT_EL_HASH_ALG=sha256 MEASURED_BOOT=1 USE_ROMLIB=1
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100189
Manish V Badarkhef43e3f52022-06-21 20:37:25 +0100190# DRTM
191clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} TPM_HASH_ALG=sha256 DRTM_SUPPORT=1 USE_ROMLIB=1
192
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100193# CoT descriptors in device tree
Manish V Badarkhe81102d12020-10-05 08:02:30 +0100194clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} COT_DESC_IN_DTB=1 USE_ROMLIB=1
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100195
Chris Kayf4789fe2023-06-12 15:52:28 +0100196# PSA FWU support
197clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_GPT_SUPPORT=1 PSA_FWU_SUPPORT=1 USE_ROMLIB=1 FVP_TRUSTED_SRAM_SIZE=384
Manish V Badarkhe107c8e32021-08-02 19:49:32 +0100198
johpow01153c8b22021-11-03 14:38:36 -0500199# SME and HCX features
200clean_build $fvp_common_flags ENABLE_SME_FOR_NS=1 ENABLE_FEAT_HCX=1
201
Jayanth Dodderi Chidanand41edd012023-01-12 14:50:34 +0000202# SME2
203clean_build $fvp_common_flags ENABLE_SME2_FOR_NS=1 ENABLE_SME_FOR_NS=1 ENABLE_FEAT_HCX=1
204
Jayanth Dodderi Chidanand84da1962022-04-11 11:38:44 +0100205# Architectural Feature Detection mechanism
206clean_build $fvp_common_flags FEATURE_DETECTION=1
207
Manish Pandeye3561fd2023-01-05 10:46:25 +0000208# RNG trap feature
209clean_build $fvp_common_flags ENABLE_FEAT_RNG=1 ENABLE_FEAT_RNG_TRAP=1
210
Chris Kayf4789fe2023-06-12 15:52:28 +0100211# OPTEE_ALLOW_SMC_LOAD feature
212clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed OPTEE_ALLOW_SMC_LOAD=1 PLAT_XLAT_TABLES_DYNAMIC=1 FVP_TRUSTED_SRAM_SIZE=384
Jeffrey Kardatzke09e18e22023-01-25 12:24:13 -0800213
Fathi Boudra422bf772019-12-02 11:10:16 +0200214#
215# Juno platform
216# We'll use the following flags for all Juno builds.
217#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500218juno_common_flags="$(common_flags) PLAT=juno"
Fathi Boudra422bf772019-12-02 11:10:16 +0200219clean_build $juno_common_flags SPD=tspd ${ARM_TBB_OPTIONS}
Elizabeth Ho4cdb2f42023-07-11 12:27:14 +0100220clean_build $juno_common_flags EL3_PAYLOAD_BASE=0x80000000
Madhukar Pappireddydcb31f62021-05-06 11:36:36 -0500221clean_build $juno_common_flags ENABLE_STACK_PROTECTOR=strong ARM_ETHOSN_NPU_DRIVER=1
Mikael Olssoncd8c7822023-02-28 17:30:44 +0100222clean_build $juno_common_flags ${ARM_TBB_OPTIONS} ENABLE_STACK_PROTECTOR=strong ARM_ETHOSN_NPU_DRIVER=1 ARM_ETHOSN_NPU_TZMP1=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200223clean_build $juno_common_flags CSS_USE_SCMI_SDS_DRIVER=0
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500224
Leonardo Sandoval5163b562020-11-20 17:17:59 -0600225clean_build $juno_common_flags SPD=tspd ${ARM_TBB_OPTIONS} ARM_CRYPTOCELL_INTEG=1 CCSBROM_LIB_PATH=${CRYPTOCELL_LIB_PATH} KEY_SIZE=2048
Fathi Boudra422bf772019-12-02 11:10:16 +0200226
Jayanth Dodderi Chidanand055394a2022-10-19 09:20:20 +0100227# TRNG Service
228clean_build $juno_common_flags TRNG_SUPPORT=1
229
Fathi Boudra422bf772019-12-02 11:10:16 +0200230#
Fathi Boudra422bf772019-12-02 11:10:16 +0200231# System Guidance for Infrastructure platform RD-E1Edge
232#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500233make $(common_flags) PLAT=rde1edge ${ARM_TBB_OPTIONS} CSS_SGI_CHIP_COUNT=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500234
235#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530236# Reference Design platform RD-V1
Zelalemc9531f82020-08-04 15:37:08 -0500237#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530238make $(common_flags) PLAT=rdv1 ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500239
240#
Aditya Angadi61c54762021-01-04 09:30:52 +0530241# Reference Design platform RD-V1-MC
Zelalemc9531f82020-08-04 15:37:08 -0500242#
Aditya Angadi61c54762021-01-04 09:30:52 +0530243make $(common_flags) PLAT=rdv1mc ${ARM_TBB_OPTIONS} CSS_SGI_CHIP_COUNT=4 all
Zelalemc9531f82020-08-04 15:37:08 -0500244
245#
Vijayenthiran Subramaniama66de332020-11-23 14:20:14 +0530246# Reference Design Platform RD-N2
247#
248make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} all
Omkar Anand Kulkarnif6e268e2023-06-21 20:32:22 +0530249# RAS Extension Support
250make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} ENABLE_FEAT_RAS=1 \
251 RAS_FFH_SUPPORT=1 HANDLE_EA_EL3_FIRST_NS=1 SDEI_SUPPORT=1 SPM_MM=1 all
Vijayenthiran Subramaniama66de332020-11-23 14:20:14 +0530252
253#
Zelalemc9531f82020-08-04 15:37:08 -0500254# Neoverse N1 SDP platform
255#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500256make $(common_flags) PLAT=n1sdp ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500257
258#
259# FVP VE platform
260#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500261make $(common_flags) PLAT=fvp_ve AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500262 CROSS_COMPILE=arm-none-eabi- ARM_ARCH_MAJOR=7 \
263 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
264 FVP_HW_CONFIG_DTS=fdts/fvp-ve-Cortex-A5x1.dts all
265
266#
267# A5 DesignStart Platform
268#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500269make $(common_flags) PLAT=a5ds AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500270 ARM_ARCH_MAJOR=7 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
271 CROSS_COMPILE=arm-none-eabi- FVP_HW_CONFIG_DTS=fdts/a5ds.dts
272
273#
274# Corstone700 Platform
275#
276
277corstone700_common_flags="CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500278 $(common_flags) \
Zelalemc9531f82020-08-04 15:37:08 -0500279 PLAT=corstone700 \
280 ARCH=aarch32 \
281 RESET_TO_SP_MIN=1 \
282 AARCH32_SP=sp_min \
283 ARM_LINUX_KERNEL_AS_BL33=0 \
284 ARM_PRELOADED_DTB_BASE=0x80400000 \
285 ENABLE_PIE=1 \
Zelalemc9531f82020-08-04 15:37:08 -0500286 ENABLE_STACK_PROTECTOR=all \
287 all"
288
289echo "Info: Building Corstone700 FVP ..."
290
291make TARGET_PLATFORM=fvp ${corstone700_common_flags}
292
293echo "Info: Building Corstone700 FPGA ..."
294
295make TARGET_PLATFORM=fpga ${corstone700_common_flags}
296
297#
298# Arm internal FPGA port
299#
Andre Przywara13361b62022-04-26 11:16:55 +0100300make PLAT=arm_fpga $(common_flags release) \
301 FPGA_PRELOADED_DTB_BASE=0x88000000 PRELOADED_BL33_BASE=0x82080000 all
Zelalemc9531f82020-08-04 15:37:08 -0500302
303#
Usama Arifcba711d2021-08-04 15:53:42 +0100304# Total Compute platforms
Zelalemc9531f82020-08-04 15:37:08 -0500305#
laurenw-arm915f70a2023-07-14 16:20:49 -0500306clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=1 ${ARM_TBB_OPTIONS}
307clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} MEASURED_BOOT=1
308clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} PLATFORM_TEST=rss-rotpk
309clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} PLATFORM_TEST=rss-nv-counters
Fathi Boudra422bf772019-12-02 11:10:16 +0200310
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530311#
312# Morello platform
313#
Chandni Cherukuricbd45962021-12-12 13:37:33 +0530314clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=fvp ${ARM_TBB_OPTIONS}
315clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=soc ${ARM_TBB_OPTIONS}
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530316
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100317#
Vishnu Banavath2cb72b32022-01-20 14:27:55 +0000318# corstone1000 Platform
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100319#
320
321make $(common_flags) \
Vishnu Banavath2cb72b32022-01-20 14:27:55 +0000322 PLAT=corstone1000 \
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100323 SPD=spmd \
324 TARGET_PLATFORM=fpga \
325 ENABLE_STACK_PROTECTOR=strong \
326 ENABLE_PIE=1 \
Maksims Svecovs7a0da522023-03-06 16:28:27 +0000327 RESET_TO_BL2=1 \
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100328 SPMD_SPM_AT_SEL2=0 \
329 ${ARM_TBB_OPTIONS} \
330 CREATE_KEYS=1 \
331 COT=tbbr \
332 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
333 bl2 \
334 bl31
335
johpow01aac58582021-10-05 16:51:34 -0500336#
337# FVP-R platform
338#
339clean_build $(common_flags) PLAT=fvp_r ${ARM_TBB_OPTIONS} ENABLE_STACK_PROTECTOR=all
340
Fathi Boudra422bf772019-12-02 11:10:16 +0200341# Partners' platforms.
342# Enable as many features as possible.
343# We don't need to clean between each build here because we only do one build
344# per platform so we don't hit the build flags dependency problem.
Fathi Boudra422bf772019-12-02 11:10:16 +0200345
Manish Pandey9c0ee742021-07-08 09:55:59 +0100346# Platforms from Mediatek
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500347make PLAT=mt8173 $(common_flags) all
348make PLAT=mt8183 $(common_flags) all
Rex-BC Chen946cace2021-11-17 10:15:42 +0800349make PLAT=mt8186 $(common_flags) COREBOOT=1 all
Bo-Chen Chen4d63afd2022-08-30 16:34:57 +0800350make PLAT=mt8188 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500351make PLAT=mt8192 $(common_flags) COREBOOT=1 all
Manish Pandey9c0ee742021-07-08 09:55:59 +0100352make PLAT=mt8195 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500353
354# Platforms from Qualcomm
355make PLAT=sc7180 $(common_flags) COREBOOT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200356
Zelalemc9531f82020-08-04 15:37:08 -0500357make PLAT=rk3288 CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500358 $(common_flags) ARCH=aarch32 AARCH32_SP=sp_min all
Madhukar Pappireddyd491ad02020-12-03 10:37:05 -0600359make PLAT=rk3368 $(common_flags) COREBOOT=1 \
360 ENABLE_STACK_PROTECTOR=strong all
361make PLAT=rk3399 $(common_flags) COREBOOT=1 PLAT_RK_DP_HDCP=1 \
362 ENABLE_STACK_PROTECTOR=strong all
363make PLAT=rk3328 $(common_flags) COREBOOT=1 PLAT_RK_SECURE_DDR_MINILOADER=1 \
364 ENABLE_STACK_PROTECTOR=strong all
365make PLAT=px30 $(common_flags) PLAT_RK_SECURE_DDR_MINILOADER=1 \
366 ENABLE_STACK_PROTECTOR=strong all
Fathi Boudra422bf772019-12-02 11:10:16 +0200367
368# Although we do several consecutive builds for the Tegra platform below, we
369# don't need to clean between each one because the Tegra makefiles specify
370# a different build directory per SoC.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500371make PLAT=tegra TARGET_SOC=t210 $(common_flags) all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500372make PLAT=tegra TARGET_SOC=t186 $(common_flags) all
373make PLAT=tegra TARGET_SOC=t194 $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200374
375# For the Xilinx platform, artificially increase the extents of BL31 memory
376# (using the platform-specific build options ZYNQMP_ATF_MEM_{BASE,SIZE}).
377# If we keep the default values, BL31 doesn't fit when it is built with all
378# these build flags.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500379make PLAT=zynqmp $(common_flags) \
Fathi Boudra422bf772019-12-02 11:10:16 +0200380 RESET_TO_BL31=1 SPD=tspd \
Zelalem4f3633e2021-06-18 11:53:47 -0500381 SDEI_SUPPORT=1 \
Fathi Boudra422bf772019-12-02 11:10:16 +0200382 ZYNQMP_ATF_MEM_BASE=0xFFFC0000 ZYNQMP_ATF_MEM_SIZE=0x00040000 \
383 all
384
Zelalemc9531f82020-08-04 15:37:08 -0500385# Build both for silicon (default) and virtual QEMU platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500386clean_build PLAT=versal $(common_flags)
387clean_build PLAT=versal $(common_flags) VERSAL_PLATFORM=versal_virt
Zelalemc9531f82020-08-04 15:37:08 -0500388
Michal Simek0f135242022-09-20 15:24:56 +0200389# Build Xilinx Versal NET platform
390clean_build PLAT=versal_net $(common_flags)
391
Jayanth Dodderi Chidanand0a2dd1e2022-10-27 11:17:37 +0100392# Build Xilinx Versal NET without Platform Management support
393clean_build PLAT=versal_net $(common_flags) TFA_NO_PM=1
394
Zelalemc9531f82020-08-04 15:37:08 -0500395# Platforms from Allwinner
Andre Przywara3a78c102022-04-26 11:08:54 +0100396clean_build PLAT=sun50i_a64 $(common_flags release) all
397clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_NATIVE=0 all
398clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_SCPI=0 all
399clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_AMEND_DTB=1 all
Andre Przywaracf78a512021-09-03 14:59:38 +0100400clean_build PLAT=sun50i_h6 $(common_flags) all
401clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_NATIVE=0 all
402clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_SCPI=0 all
403clean_build PLAT=sun50i_h616 $(common_flags) all
404clean_build PLAT=sun50i_r329 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500405
406# Platforms from i.MX
407make AARCH32_SP=optee ARCH=aarch32 ARM_ARCH_MAJOR=7 ARM_CORTEX_A7=yes \
408 CROSS_COMPILE=arm-none-eabi- PLAT=warp7 ${TBB_OPTIONS} \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500409 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500410make AARCH32_SP=optee ARCH=aarch32 CROSS_COMPILE=arm-none-eabi- PLAT=picopi \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500411 $(common_flags) all
Ying-Chun Liu (PaulLiu)f6528982021-11-17 17:20:00 +0800412make PLAT=imx8mm $(common_flags) NEED_BL2=yes MEASURED_BOOT=1 \
laurenw-arm8531e702022-06-09 15:32:37 -0500413 MBOOT_EL_HASH_ALG=sha256 ${TBB_OPTIONS} all
Madhukar Pappireddyc3ec06b2022-05-18 11:15:16 -0500414make PLAT=imx8mn $(common_flags) SDEI_SUPPORT=1 all
Ying-Chun Liu (PaulLiu)413e6102021-09-14 00:22:08 +0800415make PLAT=imx8mp $(common_flags) NEED_BL2=yes ${TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500416
Jacky Baib6cecc82021-06-07 09:49:46 +0800417# Due to the limited OCRAM space that can be used for TF-A, build test
418# will report failure caused by too small RAM size, so comment out the
419# build test for imx8mq in CI. It can also resolve the following ticket:
Zelalemc9531f82020-08-04 15:37:08 -0500420# https://developer.trustedfirmware.org/T626
Jacky Baib6cecc82021-06-07 09:49:46 +0800421#make PLAT=imx8mq $(common_flags release) all
Zelalemc9531f82020-08-04 15:37:08 -0500422
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500423make PLAT=imx8qm $(common_flags) all
424make PLAT=imx8qx $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500425
Jacky Bai87091a62023-06-21 16:25:12 +0800426make PLAT=imx93 $(common_flags) all
427
Olivier Deprezbac70192021-04-02 08:55:36 +0200428# Platforms for NXP Layerscape
Jiafei Pane48e56c2021-09-30 10:32:54 +0800429nxp_sb_flags="TRUSTED_BOARD_BOOT=1 CST_DIR=$(pwd) SPD=opteed"
430nxp_sb_fuse_flags="${nxp_sb_flags} FUSE_PROG=1"
431
432# Platform lx2
Olivier Deprezbac70192021-04-02 08:55:36 +0200433make PLAT=lx2160aqds $(common_flags) all
434make PLAT=lx2160ardb $(common_flags) all
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500435
436#CSF Based CoT:
Jiafei Pane48e56c2021-09-30 10:32:54 +0800437clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
438 $nxp_sb_fuse_flags DDR_PHY_BIN_PATH=$(pwd)
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500439
440#X509 Based CoT
Jiafei Pane48e56c2021-09-30 10:32:54 +0800441clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
442 $nxp_sb_flags GENERATE_COT=1 \
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500443 MBEDTLS_DIR=$(pwd)/mbedtls
444
445#BOOT_MODE=emmc and Stack protector
Jiafei Pane48e56c2021-09-30 10:32:54 +0800446clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=emmc \
447 $nxp_sb_fuse_flags ENABLE_STACK_PROTECTOR=strong
448
449# Platform ls1028ardb
450clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor
451clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc
452clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd
453
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800454# ls1028a Secure Boot
Jiafei Pane48e56c2021-09-30 10:32:54 +0800455clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor $nxp_sb_fuse_flags
456clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
457clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
Olivier Deprezbac70192021-04-02 08:55:36 +0200458
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800459# Platform ls1043ardb
460clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor
461clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand
462clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd
463
464# ls1043ardb Secure Boot
465clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
466clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
467clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
468
Jiafei Panbd0c22a2022-01-29 00:04:44 +0800469# ls1046ardb Secure Boot
470clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
471clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
472clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
473
474# ls1046afrwy Secure Boot
475clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
476clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
477
478# ls1046aqds Secure Boot
479clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
480clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
481clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
482clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
483
Jiafei Pan332cd792022-02-24 16:44:48 +0800484# ls1088ardb Secure Boot
485clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
486clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
487
488# ls1088aqds Secure Boot
489clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
490clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
491clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
492
Zelalemc9531f82020-08-04 15:37:08 -0500493# Platforms from Intel
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500494make PLAT=stratix10 $(common_flags) all
495make PLAT=agilex $(common_flags) all
Sieu Mun Tang9081bac2023-05-29 18:08:24 +0800496make PLAT=agilex5 $(common_flags) all
Sieu Mun Tang03b57362022-03-05 01:54:59 +0800497make PLAT=n5x $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500498
499# Platforms from Broadcom
Madhukar Pappireddy97ad2582021-11-15 10:29:23 -0600500clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t \
501 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 DRIVER_I2C_ENABLE=1
502clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t-ns3 \
503 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 USE_USB=yes
Zelalemc9531f82020-08-04 15:37:08 -0500504
505# Platforms from Marvell
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500506make PLAT=a3700 $(common_flags) SCP_BL2=/dev/null CM3_SYSTEM_RESET=1 \
Manish Pandey9ef33c52022-10-25 16:41:49 +0100507 A3720_DB_PM_WAKEUP_SRC=1 HANDLE_EA_EL3_FIRST_NS=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500508
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600509# Source files from mv-ddr-marvell repository are necessary
510# to build below four platforms
Manish Pandey7c1e7452021-11-05 12:54:15 +0000511wget https://downloads.trustedfirmware.org/tf-a/mv-ddr-marvell/mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
512tar -xzf mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600513mv mv-ddr-marvell drivers/marvell/mv_ddr
Zelalemc9531f82020-08-04 15:37:08 -0500514
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600515# These platforms from Marvell have dependency on GCC-6.2.1 toolchain
Pali Rohár8f890402021-07-19 13:48:05 +0200516make PLAT=a80x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200517 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200518make PLAT=a80x0_mcbin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200519 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200520make PLAT=a70x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200521 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200522make PLAT=a70x0_amc DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200523 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Robert Markodf3319e2021-10-20 11:01:12 +0200524make PLAT=a70x0_mochabin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
525 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200526make PLAT=a80x0_puzzle DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200527 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200528make PLAT=t9130 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200529 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500530make PLAT=t9130_cex7_eval DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
531 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500532
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600533# Removing the source files
534rm -rf drivers/marvell/mv_ddr 2> /dev/null
Zelalemc9531f82020-08-04 15:37:08 -0500535
536# Platforms from Meson
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500537make PLAT=gxbb $(common_flags) all
538make PLAT=gxl $(common_flags) all
539make PLAT=g12a $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500540
541# Platforms from Renesas
542# Renesas R-Car D3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500543clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500544 BL33=Makefile LIFEC_DBSC_PROTECT_ENABLE=0 LSI=D3 \
545 MBEDTLS_DIR=$(pwd)/mbedtls PMIC_ROHM_BD9571=0 \
546 RCAR_AVS_SETTING_ENABLE=0 SPD=none RCAR_LOSSY_ENABLE=0 \
547 RCAR_SA0_SIZE=0 RCAR_SYSTEM_SUSPEND=0 TRUSTED_BOARD_BOOT=1
548
549# Renesas R-Car H3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500550clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500551 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3 \
552 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
553 RCAR_DRAM_SPLIT=1 RCAR_GEN3_ULCB=1 SPD=opteed \
554 TRUSTED_BOARD_BOOT=1
555
556# Renesas R-Car H3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500557clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500558 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3N \
559 SPD=opteed TRUSTED_BOARD_BOOT=1
560
561# Renesas R-Car M3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500562clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500563 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3 \
564 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
565 RCAR_DRAM_SPLIT=2 RCAR_GEN3_ULCB=1 SPD=opteed \
566 TRUSTED_BOARD_BOOT=1
567
568# Renesas R-Car M3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500569clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500570 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3N \
571 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
572 RCAR_GEN3_ULCB=1 SPD=opteed TRUSTED_BOARD_BOOT=1
573
574# Renesas R-Car E3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500575clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500576 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=E3 \
577 RCAR_AVS_SETTING_ENABLE=0 RCAR_DRAM_DDR3L_MEMCONF=0 \
578 RCAR_SA0_SIZE=0 SPD=opteed TRUSTED_BOARD_BOOT=1
579
580# Renesas R-Car V3M Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500581clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500582 MBEDTLS_DIR=$(pwd)/mbedtls BL33=Makefile LSI=V3M MACHINE=eagle \
583 PMIC_ROHM_BD9571=0 RCAR_DRAM_SPLIT=0 RCAR_SYSTEM_SUSPEND=0 \
584 AVS_SETTING_ENABLE=0 SPD=none TRUSTED_BOARD_BOOT=1
585
Zelalemf4299672021-01-29 12:52:59 -0600586# Renesas HiHope RZ/G2M development kit
587clean_build PLAT=rzg $(common_flags) \
588 MBEDTLS_DIR=$(pwd)/mbedtls LSI=G2M \
589 RCAR_DRAM_SPLIT=2 RCAR_LOSSY_ENABLE=1 SPD=none
590
Zelalemc9531f82020-08-04 15:37:08 -0500591# Platforms from ST
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100592stm32mp1_common_flags="$(common_flags) \
593 ARCH=aarch32 \
594 ARM_ARCH_MAJOR=7 \
595 CROSS_COMPILE=arm-none-eabi- \
596 ENABLE_STACK_PROTECTOR=strong \
597 PLAT=stm32mp1"
598
Yann Gautiera69cf792021-09-01 11:19:01 +0200599# STM32MP1 SDMMC boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000600make ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200601 BUILD_PLAT=build/stm32mp1-sdmmc/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100602 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200603
604# STM32MP1 eMMC boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000605make ${stm32mp1_common_flags} STM32MP_EMMC=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200606 BUILD_PLAT=build/stm32mp1-emmc/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100607 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200608
609# STM32MP1 Raw NAND boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000610make ${stm32mp1_common_flags} STM32MP_RAW_NAND=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200611 BUILD_PLAT=build/stm32mp1-nand/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100612 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200613
614# STM32MP1 SPI NAND boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000615make ${stm32mp1_common_flags} STM32MP_SPI_NAND=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200616 BUILD_PLAT=build/stm32mp1-snand/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100617 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200618
619# STM32MP1 SPI NOR boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000620make ${stm32mp1_common_flags} STM32MP_SPI_NOR=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200621 BUILD_PLAT=build/stm32mp1-snor/debug \
Govindraj Raja95f855c2023-03-01 13:11:42 +0000622 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200623
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100624# STM32MP1 UART boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000625make ${stm32mp1_common_flags} STM32MP_UART_PROGRAMMER=1 \
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100626 BUILD_PLAT=build/stm32mp1-uart/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100627 AARCH32_SP=sp_min bl2 bl32
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100628
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200629# STM32MP1 USB boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000630make ${stm32mp1_common_flags} STM32MP_USB_PROGRAMMER=1 \
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200631 BUILD_PLAT=build/stm32mp1-usb/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100632 AARCH32_SP=sp_min bl2 bl32
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200633
Lionel Debieve8f464c02022-10-13 09:25:45 +0200634# STM32MP1 TBBR
Govindraj Raja95f855c2023-03-01 13:11:42 +0000635make ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
Yann Gautier741e8492022-11-14 19:04:27 +0100636 BUILD_PLAT=build/stm32mp1-sdmmc-tbbr/debug \
Lionel Debieve8f464c02022-10-13 09:25:45 +0200637 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100638 AARCH32_SP=sp_min bl2 bl32
Lionel Debieve8f464c02022-10-13 09:25:45 +0200639
Govindraj Raja95f855c2023-03-01 13:11:42 +0000640stm32mp13_common_flags="${stm32mp1_common_flags} \
641 AARCH32_SP=optee \
642 STM32MP13=1"
643
Yann Gautier773c5502022-03-10 17:24:47 +0100644# STM32MP13 SDMMC boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000645make ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100646 BUILD_PLAT=build/stm32mp1-mp13-sdmmc/debug bl2
Yann Gautier773c5502022-03-10 17:24:47 +0100647
Lionel Debieve8f464c02022-10-13 09:25:45 +0200648# STM32MP13 TBBR
Govindraj Raja95f855c2023-03-01 13:11:42 +0000649make ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Lionel Debieve8f464c02022-10-13 09:25:45 +0200650 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100651 BUILD_PLAT=build/stm32mp1-mp13-sdmmc-tbbr/debug bl2
Lionel Debieve8f464c02022-10-13 09:25:45 +0200652
Yann Gautiera66e5012022-12-13 13:52:35 +0100653# STM32MP13 TBBR DECRYPTION AES GCM
Govindraj Raja95f855c2023-03-01 13:11:42 +0000654make ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Yann Gautiera66e5012022-12-13 13:52:35 +0100655 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
656 DECRYPTION_SUPPORT=aes_gcm ENCRYPT_BL32=1 \
657 BUILD_PLAT=build/stm32mp1-mp13-sdmmc-tbbr-dec/debug bl2
658
Zelalemc9531f82020-08-04 15:37:08 -0500659# Platforms from TI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500660make PLAT=k3 $(common_flags) all
Hari Nagalladadd89f2022-08-30 12:10:00 -0500661make PLAT=k3 TARGET_BOARD=j784s4 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500662
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500663clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS}
Zelalemc9531f82020-08-04 15:37:08 -0500664# Use GICV3 driver
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500665clean_build PLAT=qemu $(common_flags) QEMU_USE_GIC_DRIVER=QEMU_GICV3 \
Zelalemc9531f82020-08-04 15:37:08 -0500666 ENABLE_STACK_PROTECTOR=strong
Dongjiu Geng72819ee2023-06-16 18:48:57 +0800667# Use GICV3 driver with SDEI support
668clean_build PLAT=qemu $(common_flags) QEMU_USE_GIC_DRIVER=QEMU_GICV3 \
669 ENABLE_STACK_PROTECTOR=strong SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Zelalemc9531f82020-08-04 15:37:08 -0500670# Use encrypted FIP feature.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500671clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500672 BL32_RAM_LOCATION=tdram DECRYPTION_SUPPORT=aes_gcm ENCRYPT_BL31=1 \
673 ENCRYPT_BL32=1 FW_ENC_STATUS=0 SPD=opteed
Jens Wiklander1a9c2be2021-11-26 09:56:55 +0100674# QEMU with SPMD support
675clean_build PLAT=qemu $(common_flags) BL32=Makefile \
676 BL32_RAM_LOCATION=tdram ARM_BL31_IN_DRAM=1 \
677 SPD=spmd CTX_INCLUDE_EL2_REGS=0 SPMD_SPM_AT_SEL2=0 SPMC_OPTEE=1
Ruchika Gupta86e7f682022-04-12 10:25:46 +0530678# Measured Boot
laurenw-arm8531e702022-06-09 15:32:37 -0500679clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} MBOOT_EL_HASH_ALG=sha256 MEASURED_BOOT=1
Zelalemc9531f82020-08-04 15:37:08 -0500680
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500681clean_build PLAT=qemu_sbsa $(common_flags)
Fathi Boudra422bf772019-12-02 11:10:16 +0200682
Zelalemd86e8762020-08-21 18:24:28 -0500683# QEMU with SPM support
684clean_build PLAT=qemu_sbsa $(common_flags) BL32=Makefile SPM_MM=1 \
Paul Sokolovskycf9fe862023-01-02 16:22:21 +0300685 EL3_EXCEPTION_HANDLING=1 ENABLE_SME_FOR_NS=0 ENABLE_SVE_FOR_NS=0
Zelalemd86e8762020-08-21 18:24:28 -0500686
Fathi Boudra422bf772019-12-02 11:10:16 +0200687# For hikey enable PMF to include all files in the platform port
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500688make PLAT=hikey $(common_flags) ${TBB_OPTIONS} ENABLE_PMF=1 all
689make PLAT=hikey960 $(common_flags) ${TBB_OPTIONS} all
Lukas Haneld0752392022-10-13 11:13:19 +0200690make PLAT=hikey960 $(common_flags) ${TBB_OPTIONS} SPD=spmd SPMC_AT_EL3=1 \
691 SPMD_SPM_AT_SEL2=0 BL32=optee PLAT_SP_MANIFEST_DTS=foo NEED_FDT=no all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500692make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200693
Zelalemc9531f82020-08-04 15:37:08 -0500694# Platforms from Socionext
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500695clean_build PLAT=uniphier $(common_flags) ${TBB_OPTIONS} SPD=tspd
696clean_build PLAT=uniphier $(common_flags) FIP_GZIP=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200697
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500698clean_build PLAT=synquacer $(common_flags) SPM_MM=1 \
Jassi Brar86080922022-06-27 14:16:34 -0500699 RESET_TO_BL31=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0 \
700 PRELOADED_BL33_BASE=0x0
Zelalemc9531f82020-08-04 15:37:08 -0500701
702# Support for SCP Message Interface protocol with platform specific drivers
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500703clean_build PLAT=synquacer $(common_flags) \
Jassi Brar86080922022-06-27 14:16:34 -0500704 RESET_TO_BL31=1 PRELOADED_BL33_BASE=0x0 SQ_USE_SCMI_DRIVER=1
Zelalemc9531f82020-08-04 15:37:08 -0500705
Jassi Brarb8c7ca02022-06-27 14:22:10 -0500706# Support for BL2 and TBBR
707clean_build PLAT=synquacer $(common_flags) \
708 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
709 SQ_USE_SCMI_DRIVER=1 SPD=opteed all
710
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500711make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200712
Zelalemc9531f82020-08-04 15:37:08 -0500713# Raspberry Pi Platforms
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500714make PLAT=rpi3 $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500715 ENABLE_STACK_PROTECTOR=strong PRELOADED_BL33_BASE=0xDEADBEEF all
Andre Przywarae917ec82021-09-03 15:01:30 +0100716clean_build PLAT=rpi4 $(common_flags) SMC_PCI_SUPPORT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200717
Zelalemc9531f82020-08-04 15:37:08 -0500718# A113D (AXG) platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500719clean_build PLAT=axg $(common_flags) SPD=opteed
720clean_build PLAT=axg $(common_flags) AML_USE_ATOS=1
Zelalemc9531f82020-08-04 15:37:08 -0500721
Stephan Gerhold141a7662021-12-07 20:42:14 +0100722# QTI MSM8916 platform
Stephan Gerhold3b3976f2023-04-17 16:27:11 +0200723clean_build PLAT=mdm9607 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
724 ARCH=aarch32 AARCH32_SP=sp_min
725clean_build PLAT=msm8909 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
726 ARCH=aarch32 AARCH32_SP=sp_min
Stephan Gerhold141a7662021-12-07 20:42:14 +0100727clean_build PLAT=msm8916 $(common_flags)
Manish V Badarkhec540e622023-06-28 17:56:40 +0100728clean_build PLAT=msm8916 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
729 ARCH=aarch32 AARCH32_SP=sp_min
Stephan Gerhold998f0d62023-04-17 16:22:52 +0200730clean_build PLAT=msm8916 $(common_flags) SPD=tspd
Stephan Gerhold3b3976f2023-04-17 16:27:11 +0200731clean_build PLAT=msm8939 $(common_flags)
732clean_build PLAT=msm8939 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
733 ARCH=aarch32 AARCH32_SP=sp_min
734clean_build PLAT=msm8939 $(common_flags) SPD=tspd
Stephan Gerhold141a7662021-12-07 20:42:14 +0100735
Chia-Wei Wang7dcb0d02023-06-09 09:52:52 +0800736# Platforms from Aspeed
737clean_build PLAT=ast2700 $(common_flags) SPD=opteed
738
rutigl@gmail.com86cfcf92023-03-21 10:10:11 +0200739# Nuvoton npcm845x platform
740make PLAT=npcm845x $(common_flags) all SPD=opteed
741
Fathi Boudra422bf772019-12-02 11:10:16 +0200742cd ..