blob: 14ccf63d81c5d94bca7f33be2bc6b6c93fedb9c0 [file] [log] [blame]
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -05001#!/usr/bin/env bash
Fathi Boudra422bf772019-12-02 11:10:16 +02002#
Govindraj Raja95f855c2023-03-01 13:11:42 +00003# Copyright (c) 2019-2023, Arm Limited. All rights reserved.
Fathi Boudra422bf772019-12-02 11:10:16 +02004#
5# SPDX-License-Identifier: BSD-3-Clause
6#
7
8#
9# This script builds the TF in different configs.
10# Rather than telling cov-build to build TF using a simple 'make all' command,
11# the goal here is to combine several build flags to analyse more of our source
12# code in a single 'build'. The Coverity Scan service does not have the notion
13# of separate types of build - there is just one linear sequence of builds in
14# the project history.
15#
16
Harrison Mutaiee958c12023-09-06 12:16:21 +010017set -E
18trap 'rc=$?; error_count=$((error_count+1));' ERR INT
Fathi Boudra422bf772019-12-02 11:10:16 +020019
20TF_SOURCES=$1
21if [ ! -d "$TF_SOURCES" ]; then
22 echo "ERROR: '$TF_SOURCES' does not exist or is not a directory"
23 echo "Usage: $(basename "$0") <trusted-firmware-directory>"
24 exit 1
25fi
26
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050027containing_dir="$(readlink -f "$(dirname "$0")/")"
28. $containing_dir/common-def.sh
29
Fathi Boudra422bf772019-12-02 11:10:16 +020030# Get mbed TLS library code to build Trusted Firmware with Trusted Board Boot
31# support. The version of mbed TLS to use here must be the same as when
32# building TF in the usual context.
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050033if [ ! -d "$MBED_TLS_DIR" ]; then
34 git clone -q --depth 1 -b "$MBED_TLS_SOURCES_TAG" "$MBED_TLS_URL_REPO" "$MBED_TLS_DIR"
Fathi Boudra422bf772019-12-02 11:10:16 +020035fi
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050036
Manish V Badarkhe58a88f02023-11-06 21:42:11 +000037# Get TF-M tests and extras repo for TC build with tf-m test suite.
38if [ ! -d "$TF_M_TESTS_DIR" ]; then
39 git clone "$TF_M_TESTS_URL_REPO" "$TF_M_TESTS_DIR"
40 cd "$TF_M_TESTS_DIR"
41 git checkout master
42fi
43
44cd "$TF_SOURCES"
45
46if [ ! -d "$TF_M_EXTRAS_DIR" ]; then
47 git clone "$TF_M_EXTRAS_URL_REPO" "$TF_M_EXTRAS_DIR"
48 cd "$TF_M_EXTRAS_DIR"
49 git checkout master
50fi
51
Fathi Boudra422bf772019-12-02 11:10:16 +020052cd "$TF_SOURCES"
53
54# Clean TF source dir to make sure we don't analyse temporary files.
55make distclean
56
57#
58# Build TF in different configurations to get as much coverage as possible
59#
60
Fathi Boudra422bf772019-12-02 11:10:16 +020061#
62# FVP platform
63# We'll use the following flags for all FVP builds.
64#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050065fvp_common_flags="$(common_flags) PLAT=fvp"
Fathi Boudra422bf772019-12-02 11:10:16 +020066
67# Try all possible SPDs.
Chris Kayab29d432023-08-10 13:06:18 +000068clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram \
69 SPD=tspd FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +020070clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd TSP_INIT_ASYNC=1 \
Sona Mathew40e5be92023-08-10 16:31:45 -050071 TSP_NS_INTR_ASYNC_PREEMPT=1 FVP_TRUSTED_SRAM_SIZE=384
Manish V Badarkhe48ed0bf2023-06-28 09:33:16 +010072clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed FVP_TRUSTED_SRAM_SIZE=384
Elizabeth Ho1a04df12023-07-27 16:06:24 +010073clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tlkd FVP_TRUSTED_SRAM_SIZE=384
Manish V Badarkhee7528ff2023-07-01 10:20:05 +010074clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=pncd SPD_PNCD_NS_IRQ=126 \
75 SPD_PNCD_S_IRQ=15 FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +020076
Zelalemc9531f82020-08-04 15:37:08 -050077# Dualroot chain of trust.
78clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tspd COT=dualroot
79
laurenw-armf48e9d22022-04-22 11:30:13 -050080# FEAT_RME with CCA chain of trust.
Sandrine Bailleuxe30bd0c2022-08-31 14:49:17 +020081#
82# Note that we override PLAT_RSS_NOT_SUPPORTED build flag (which defaults to 1
83# on the Base AEM FVP) just to analyse the RSS communication driver code through
84# Coverity. In reality, RSS is not supported on FVP right now (or on any other
85# upstream platform, for that matter) so the resulting firmware would not be
86# functional.
Manish V Badarkhe5304aaf2023-08-18 14:38:20 +010087clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} USE_ROMLIB=1 \
88 ENABLE_RME=1 MEASURED_BOOT=1 PLAT_RSS_NOT_SUPPORTED=0
89
90# FVP RSS supported build without CCA enabled.
91clean_build $fvp_common_flags USE_ROMLIB=1 MEASURED_BOOT=1 MBEDTLS_DIR=$(pwd)/mbedtls \
Manish V Badarkhece14ffc2023-07-27 09:28:23 +010092 PLAT_RSS_NOT_SUPPORTED=0
laurenw-armf48e9d22022-04-22 11:30:13 -050093
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050094clean_build $fvp_common_flags SPD=trusty
95clean_build $fvp_common_flags SPD=trusty TRUSTY_SPD_WITH_GENERIC_SERVICES=1
Fathi Boudra422bf772019-12-02 11:10:16 +020096
Sona Mathewff9c2a72023-05-10 21:18:01 -050097# ERRATA ABI
98clean_build $fvp_common_flags ERRATA_ABI_SUPPORT=1
99
Fathi Boudra422bf772019-12-02 11:10:16 +0200100# SDEI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500101clean_build $fvp_common_flags SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200102
Zelalemc9531f82020-08-04 15:37:08 -0500103# SDEI with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500104clean_build $fvp_common_flags SDEI_IN_FCONF=1 SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Zelalemc9531f82020-08-04 15:37:08 -0500105
Zelalem4f3633e2021-06-18 11:53:47 -0500106# PCI Service
107clean_build $fvp_common_flags SMC_PCI_SUPPORT=1
108
Zelalemc9531f82020-08-04 15:37:08 -0500109# Secure interrupt descriptors with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500110clean_build $fvp_common_flags SEC_INT_DESC_IN_FCONF=1
Zelalemc9531f82020-08-04 15:37:08 -0500111
Fathi Boudra422bf772019-12-02 11:10:16 +0200112# Without coherent memory
Sona Mathewa06f62d2023-08-24 16:34:13 -0500113clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd \
114 USE_COHERENT_MEM=0 FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +0200115
116# Using PSCI extended State ID format rather than the original format
Sona Mathewa06f62d2023-08-24 16:34:13 -0500117clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd \
118 PSCI_EXTENDED_STATE_ID=1 ARM_RECOM_STATE_ID_ENC=1 FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +0200119
120# Alternative boot flows (This changes some of the platform initialisation code)
Elizabeth Ho4cdb2f42023-07-11 12:27:14 +0100121clean_build $fvp_common_flags EL3_PAYLOAD_BASE=0x80000000
Fathi Boudra422bf772019-12-02 11:10:16 +0200122clean_build $fvp_common_flags PRELOADED_BL33_BASE=0x80000000
123
124# Using the SP804 timer instead of the Generic Timer
125clean_build $fvp_common_flags FVP_USE_SP804_TIMER=1
126
127# Using the CCN driver and multi cluster topology
128clean_build $fvp_common_flags FVP_CLUSTER_COUNT=4
129
130# PMF
131clean_build $fvp_common_flags ENABLE_PMF=1
132
133# stack protector
134clean_build $fvp_common_flags ENABLE_STACK_PROTECTOR=strong
135
136# AArch32 build
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500137clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200138 ARCH=aarch32 AARCH32_SP=sp_min \
139 RESET_TO_SP_MIN=1 PRELOADED_BL33_BASE=0x80000000
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500140clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200141 ARCH=aarch32 AARCH32_SP=sp_min
142
143# Xlat tables lib version 1 (AArch64 and AArch32)
144clean_build $fvp_common_flags ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500145clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200146 ARCH=aarch32 AARCH32_SP=sp_min ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
147
Zelalemc9531f82020-08-04 15:37:08 -0500148# SPM support based on Management Mode Interface Specification
Manish Pandeyaa9a03b2021-11-17 10:03:17 +0000149clean_build $fvp_common_flags SPM_MM=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0
Fathi Boudra422bf772019-12-02 11:10:16 +0200150
Zelalemc9531f82020-08-04 15:37:08 -0500151# SPM support with TOS(optee) as SPM sitting at S-EL1
152clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0
153
Shruti Gupta8cc89b92022-08-09 12:23:46 +0100154# SPM support with SPM at EL3 and TSP at S-EL1
155clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 CTX_INCLUDE_EL2_REGS=0 EL3_EXCEPTION_HANDLING=0 \
156 SPD=spmd SPMD_SPM_AT_SEL2=0 SPMC_AT_EL3=1 \
157 ARM_SPMC_MANIFEST_DTS=plat/arm/board/fvp/fdts/fvp_tsp_sp_manifest.dts
158
Zelalemc9531f82020-08-04 15:37:08 -0500159# SPM support with Secure hafnium as SPM sitting at S-EL2
160# SP_LAYOUT_FILE is used only during FIP creation but build won't progress
161# if we have NULL value to it, so passing a dummy string.
162clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=1 ARM_ARCH_MINOR=4 \
Max Shvetsov44d2a702021-02-18 16:41:45 +0000163 CTX_INCLUDE_EL2_REGS=1 SP_LAYOUT_FILE=dummy
Fathi Boudra422bf772019-12-02 11:10:16 +0200164
J-Alves85ba07b2023-07-12 14:37:45 +0100165# SPM support with logical partitions in the SPMD.
166clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=1 ARM_ARCH_MINOR=4 \
167 CTX_INCLUDE_EL2_REGS=1 SP_LAYOUT_FILE=dummy ENABLE_SPMD_LP=1
168
Marc Bonnici502fdaa2022-01-10 12:38:23 +0000169# SPM support with SPM sitting at EL3
170clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0 SPMC_AT_EL3=1
171
Harrison Mutaib352c0e2023-08-11 18:27:57 +0100172# Firmware Handoff framework support
173clean_build $fvp_common_flags TRANSFER_LIST=1
174
Fathi Boudra422bf772019-12-02 11:10:16 +0200175#BL2 at EL3 support
Harrison Mutaic3c8cfc2023-09-05 12:03:03 +0100176clean_build $fvp_common_flags RESET_TO_BL2=1 FVP_TRUSTED_SRAM_SIZE=384
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500177clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Maksims Svecovs7a0da522023-03-06 16:28:27 +0000178 ARCH=aarch32 AARCH32_SP=sp_min RESET_TO_BL2=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200179
Zelalemc9531f82020-08-04 15:37:08 -0500180# RAS Extension Support
Manish Pandeyc1fa25b2023-02-16 17:35:36 +0000181clean_build $fvp_common_flags EL3_EXCEPTION_HANDLING=1 ENABLE_FEAT_RAS=1 \
Manish Pandeyf3816802023-10-11 17:13:58 +0100182 FAULT_INJECTION_SUPPORT=1 HANDLE_EA_EL3_FIRST_NS=1 \
Manish Pandey010e9b42023-04-24 15:49:27 +0100183 SDEI_SUPPORT=1 PLATFORM_TEST_RAS_FFH=1
Zelalemc9531f82020-08-04 15:37:08 -0500184
Manish Pandeyfd4c6b72023-04-24 10:29:52 +0100185# EA handled in EL3 first
186clean_build $fvp_common_flags HANDLE_EA_EL3_FIRST_NS=1 PLATFORM_TEST_EA_FFH=1
187
Zelalemc9531f82020-08-04 15:37:08 -0500188# Hardware Assisted Coherency(DynamIQ)
189clean_build $fvp_common_flags FVP_CLUSTER_COUNT=1 FVP_MAX_CPUS_PER_CLUSTER=8 \
190 HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0
191
192# Pointer Authentication Support
193clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 \
Sona Mathewa06f62d2023-08-24 16:34:13 -0500194 ARM_ARCH_MINOR=5 EL3_EXCEPTION_HANDLING=1 BRANCH_PROTECTION=1 SDEI_SUPPORT=1 SPD=tspd \
Sona Mathew08c17962023-08-28 09:36:17 -0500195 TSP_NS_INTR_ASYNC_PREEMPT=1 FVP_TRUSTED_SRAM_SIZE=384
Zelalemc9531f82020-08-04 15:37:08 -0500196
197# Undefined Behaviour Sanitizer
198# Building with UBSAN SANITIZE_UB=on increases the executable size.
199# Hence it is only properly supported in bl31 with RESET_TO_BL31 enabled
200make $fvp_common_flags clean
Manish V Badarkhe4e79cab2023-09-07 10:07:58 +0100201make $fvp_common_flags SANITIZE_UB=on RESET_TO_BL31=1 FVP_TRUSTED_SRAM_SIZE=384 bl31
Zelalemc9531f82020-08-04 15:37:08 -0500202
203# debugfs feature
204clean_build $fvp_common_flags DEBUG=1 USE_DEBUGFS=1
205
206# MPAM feature
Arvind Ram Prakashbd4e43a2023-10-02 11:12:34 -0500207clean_build $fvp_common_flags ENABLE_FEAT_MPAM=1
Zelalemc9531f82020-08-04 15:37:08 -0500208
209# Using GICv3.1 driver with extended PPI and SPI range
210clean_build $fvp_common_flags GIC_EXT_INTID=1
211
212# Using GICv4 features with extended PPI and SPI range
213clean_build $fvp_common_flags GIC_ENABLE_V4_EXTN=1 GIC_EXT_INTID=1
214
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100215# Measured Boot
laurenw-arm8531e702022-06-09 15:32:37 -0500216clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} MBOOT_EL_HASH_ALG=sha256 MEASURED_BOOT=1 USE_ROMLIB=1
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100217
Manish V Badarkhef43e3f52022-06-21 20:37:25 +0100218# DRTM
219clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} TPM_HASH_ALG=sha256 DRTM_SUPPORT=1 USE_ROMLIB=1
220
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100221# CoT descriptors in device tree
Manish V Badarkhe81102d12020-10-05 08:02:30 +0100222clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} COT_DESC_IN_DTB=1 USE_ROMLIB=1
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100223
Chris Kayf4789fe2023-06-12 15:52:28 +0100224# PSA FWU support
225clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_GPT_SUPPORT=1 PSA_FWU_SUPPORT=1 USE_ROMLIB=1 FVP_TRUSTED_SRAM_SIZE=384
Manish V Badarkhe107c8e32021-08-02 19:49:32 +0100226
Manish V Badarkhe92616ae2023-09-18 10:06:00 +0100227# PSA Crypto support
228clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} PSA_CRYPTO=1 FVP_TRUSTED_SRAM_SIZE=384
229
johpow01153c8b22021-11-03 14:38:36 -0500230# SME and HCX features
231clean_build $fvp_common_flags ENABLE_SME_FOR_NS=1 ENABLE_FEAT_HCX=1
232
Jayanth Dodderi Chidanand41edd012023-01-12 14:50:34 +0000233# SME2
234clean_build $fvp_common_flags ENABLE_SME2_FOR_NS=1 ENABLE_SME_FOR_NS=1 ENABLE_FEAT_HCX=1
235
Jayanth Dodderi Chidanand84da1962022-04-11 11:38:44 +0100236# Architectural Feature Detection mechanism
237clean_build $fvp_common_flags FEATURE_DETECTION=1
238
Manish Pandeye3561fd2023-01-05 10:46:25 +0000239# RNG trap feature
240clean_build $fvp_common_flags ENABLE_FEAT_RNG=1 ENABLE_FEAT_RNG_TRAP=1
241
Chris Kayf4789fe2023-06-12 15:52:28 +0100242# OPTEE_ALLOW_SMC_LOAD feature
243clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed OPTEE_ALLOW_SMC_LOAD=1 PLAT_XLAT_TABLES_DYNAMIC=1 FVP_TRUSTED_SRAM_SIZE=384
Jeffrey Kardatzke09e18e22023-01-25 12:24:13 -0800244
Fathi Boudra422bf772019-12-02 11:10:16 +0200245#
246# Juno platform
247# We'll use the following flags for all Juno builds.
248#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500249juno_common_flags="$(common_flags) PLAT=juno"
Fathi Boudra422bf772019-12-02 11:10:16 +0200250clean_build $juno_common_flags SPD=tspd ${ARM_TBB_OPTIONS}
Elizabeth Ho4cdb2f42023-07-11 12:27:14 +0100251clean_build $juno_common_flags EL3_PAYLOAD_BASE=0x80000000
Manish V Badarkhe05626442023-09-12 09:54:50 +0100252clean_build $juno_common_flags ENABLE_STACK_PROTECTOR=strong ETHOSN_NPU_DRIVER=1
253clean_build $juno_common_flags ${ARM_TBB_OPTIONS} ENABLE_STACK_PROTECTOR=strong ETHOSN_NPU_DRIVER=1 ETHOSN_NPU_TZMP1=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200254clean_build $juno_common_flags CSS_USE_SCMI_SDS_DRIVER=0
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500255
Jayanth Dodderi Chidanand055394a2022-10-19 09:20:20 +0100256# TRNG Service
257clean_build $juno_common_flags TRNG_SUPPORT=1
258
Fathi Boudra422bf772019-12-02 11:10:16 +0200259#
Fathi Boudra422bf772019-12-02 11:10:16 +0200260# System Guidance for Infrastructure platform RD-E1Edge
261#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500262make $(common_flags) PLAT=rde1edge ${ARM_TBB_OPTIONS} CSS_SGI_CHIP_COUNT=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500263
264#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530265# Reference Design platform RD-V1
Zelalemc9531f82020-08-04 15:37:08 -0500266#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530267make $(common_flags) PLAT=rdv1 ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500268
269#
Aditya Angadi61c54762021-01-04 09:30:52 +0530270# Reference Design platform RD-V1-MC
Zelalemc9531f82020-08-04 15:37:08 -0500271#
Aditya Angadi61c54762021-01-04 09:30:52 +0530272make $(common_flags) PLAT=rdv1mc ${ARM_TBB_OPTIONS} CSS_SGI_CHIP_COUNT=4 all
Zelalemc9531f82020-08-04 15:37:08 -0500273
274#
Vijayenthiran Subramaniama66de332020-11-23 14:20:14 +0530275# Reference Design Platform RD-N2
276#
277make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} all
Omkar Anand Kulkarnif6e268e2023-06-21 20:32:22 +0530278# RAS Extension Support
279make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} ENABLE_FEAT_RAS=1 \
Manish Pandeyf3816802023-10-11 17:13:58 +0100280 HANDLE_EA_EL3_FIRST_NS=1 SDEI_SUPPORT=1 SPM_MM=1 all
281
Nishant Sharmabd7092e2023-10-11 09:17:13 +0100282# SPMC At EL3 Support
283make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} SPMC_AT_EL3=1 SPD=spmd \
284 SPMD_SPM_AT_SEL2=0 BL32=1 SPMC_AT_EL3_SEL0_SP=1 EL3_EXCEPTION_HANDLING=1 \
285 PLAT_RO_XLAT_TABLES=1 all
Vijayenthiran Subramaniama66de332020-11-23 14:20:14 +0530286
287#
Zelalemc9531f82020-08-04 15:37:08 -0500288# Neoverse N1 SDP platform
289#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500290make $(common_flags) PLAT=n1sdp ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500291
292#
293# FVP VE platform
294#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500295make $(common_flags) PLAT=fvp_ve AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500296 CROSS_COMPILE=arm-none-eabi- ARM_ARCH_MAJOR=7 \
297 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
298 FVP_HW_CONFIG_DTS=fdts/fvp-ve-Cortex-A5x1.dts all
299
300#
301# A5 DesignStart Platform
302#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500303make $(common_flags) PLAT=a5ds AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500304 ARM_ARCH_MAJOR=7 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
305 CROSS_COMPILE=arm-none-eabi- FVP_HW_CONFIG_DTS=fdts/a5ds.dts
306
307#
308# Corstone700 Platform
309#
310
311corstone700_common_flags="CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500312 $(common_flags) \
Zelalemc9531f82020-08-04 15:37:08 -0500313 PLAT=corstone700 \
314 ARCH=aarch32 \
315 RESET_TO_SP_MIN=1 \
316 AARCH32_SP=sp_min \
317 ARM_LINUX_KERNEL_AS_BL33=0 \
318 ARM_PRELOADED_DTB_BASE=0x80400000 \
319 ENABLE_PIE=1 \
Zelalemc9531f82020-08-04 15:37:08 -0500320 ENABLE_STACK_PROTECTOR=all \
321 all"
322
323echo "Info: Building Corstone700 FVP ..."
324
325make TARGET_PLATFORM=fvp ${corstone700_common_flags}
326
327echo "Info: Building Corstone700 FPGA ..."
328
329make TARGET_PLATFORM=fpga ${corstone700_common_flags}
330
331#
332# Arm internal FPGA port
333#
Andre Przywara13361b62022-04-26 11:16:55 +0100334make PLAT=arm_fpga $(common_flags release) \
335 FPGA_PRELOADED_DTB_BASE=0x88000000 PRELOADED_BL33_BASE=0x82080000 all
Zelalemc9531f82020-08-04 15:37:08 -0500336
337#
Usama Arifcba711d2021-08-04 15:53:42 +0100338# Total Compute platforms
Zelalemc9531f82020-08-04 15:37:08 -0500339#
laurenw-arm915f70a2023-07-14 16:20:49 -0500340clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=1 ${ARM_TBB_OPTIONS}
341clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} MEASURED_BOOT=1
342clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} PLATFORM_TEST=rss-rotpk
343clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} PLATFORM_TEST=rss-nv-counters
Manish V Badarkhe58a88f02023-11-06 21:42:11 +0000344clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} PLATFORM_TEST=tfm-testsuite \
345 MEASURED_BOOT=1 TF_M_TESTS_PATH=$(pwd)/tf-m-tests TF_M_EXTRAS_PATH=$(pwd)/tf-m-extras
Fathi Boudra422bf772019-12-02 11:10:16 +0200346
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530347#
348# Morello platform
349#
Chandni Cherukuricbd45962021-12-12 13:37:33 +0530350clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=fvp ${ARM_TBB_OPTIONS}
351clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=soc ${ARM_TBB_OPTIONS}
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530352
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100353#
Vishnu Banavath2cb72b32022-01-20 14:27:55 +0000354# corstone1000 Platform
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100355#
356
357make $(common_flags) \
Vishnu Banavath2cb72b32022-01-20 14:27:55 +0000358 PLAT=corstone1000 \
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100359 SPD=spmd \
360 TARGET_PLATFORM=fpga \
361 ENABLE_STACK_PROTECTOR=strong \
362 ENABLE_PIE=1 \
Maksims Svecovs7a0da522023-03-06 16:28:27 +0000363 RESET_TO_BL2=1 \
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100364 SPMD_SPM_AT_SEL2=0 \
365 ${ARM_TBB_OPTIONS} \
366 CREATE_KEYS=1 \
367 COT=tbbr \
368 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
369 bl2 \
370 bl31
371
johpow01aac58582021-10-05 16:51:34 -0500372#
373# FVP-R platform
374#
375clean_build $(common_flags) PLAT=fvp_r ${ARM_TBB_OPTIONS} ENABLE_STACK_PROTECTOR=all
376
Fathi Boudra422bf772019-12-02 11:10:16 +0200377# Partners' platforms.
378# Enable as many features as possible.
379# We don't need to clean between each build here because we only do one build
380# per platform so we don't hit the build flags dependency problem.
Fathi Boudra422bf772019-12-02 11:10:16 +0200381
Manish Pandey9c0ee742021-07-08 09:55:59 +0100382# Platforms from Mediatek
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500383make PLAT=mt8173 $(common_flags) all
384make PLAT=mt8183 $(common_flags) all
Rex-BC Chen946cace2021-11-17 10:15:42 +0800385make PLAT=mt8186 $(common_flags) COREBOOT=1 all
Bo-Chen Chen4d63afd2022-08-30 16:34:57 +0800386make PLAT=mt8188 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500387make PLAT=mt8192 $(common_flags) COREBOOT=1 all
Manish Pandey9c0ee742021-07-08 09:55:59 +0100388make PLAT=mt8195 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500389
390# Platforms from Qualcomm
391make PLAT=sc7180 $(common_flags) COREBOOT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200392
Zelalemc9531f82020-08-04 15:37:08 -0500393make PLAT=rk3288 CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500394 $(common_flags) ARCH=aarch32 AARCH32_SP=sp_min all
Madhukar Pappireddyd491ad02020-12-03 10:37:05 -0600395make PLAT=rk3368 $(common_flags) COREBOOT=1 \
396 ENABLE_STACK_PROTECTOR=strong all
397make PLAT=rk3399 $(common_flags) COREBOOT=1 PLAT_RK_DP_HDCP=1 \
398 ENABLE_STACK_PROTECTOR=strong all
399make PLAT=rk3328 $(common_flags) COREBOOT=1 PLAT_RK_SECURE_DDR_MINILOADER=1 \
400 ENABLE_STACK_PROTECTOR=strong all
401make PLAT=px30 $(common_flags) PLAT_RK_SECURE_DDR_MINILOADER=1 \
402 ENABLE_STACK_PROTECTOR=strong all
Fathi Boudra422bf772019-12-02 11:10:16 +0200403
404# Although we do several consecutive builds for the Tegra platform below, we
405# don't need to clean between each one because the Tegra makefiles specify
406# a different build directory per SoC.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500407make PLAT=tegra TARGET_SOC=t210 $(common_flags) all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500408make PLAT=tegra TARGET_SOC=t186 $(common_flags) all
409make PLAT=tegra TARGET_SOC=t194 $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200410
411# For the Xilinx platform, artificially increase the extents of BL31 memory
412# (using the platform-specific build options ZYNQMP_ATF_MEM_{BASE,SIZE}).
413# If we keep the default values, BL31 doesn't fit when it is built with all
414# these build flags.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500415make PLAT=zynqmp $(common_flags) \
Fathi Boudra422bf772019-12-02 11:10:16 +0200416 RESET_TO_BL31=1 SPD=tspd \
Zelalem4f3633e2021-06-18 11:53:47 -0500417 SDEI_SUPPORT=1 \
Fathi Boudra422bf772019-12-02 11:10:16 +0200418 ZYNQMP_ATF_MEM_BASE=0xFFFC0000 ZYNQMP_ATF_MEM_SIZE=0x00040000 \
419 all
420
Zelalemc9531f82020-08-04 15:37:08 -0500421# Build both for silicon (default) and virtual QEMU platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500422clean_build PLAT=versal $(common_flags)
423clean_build PLAT=versal $(common_flags) VERSAL_PLATFORM=versal_virt
Zelalemc9531f82020-08-04 15:37:08 -0500424
Michal Simek0f135242022-09-20 15:24:56 +0200425# Build Xilinx Versal NET platform
426clean_build PLAT=versal_net $(common_flags)
427
Jayanth Dodderi Chidanand0a2dd1e2022-10-27 11:17:37 +0100428# Build Xilinx Versal NET without Platform Management support
429clean_build PLAT=versal_net $(common_flags) TFA_NO_PM=1
430
Zelalemc9531f82020-08-04 15:37:08 -0500431# Platforms from Allwinner
Andre Przywara3a78c102022-04-26 11:08:54 +0100432clean_build PLAT=sun50i_a64 $(common_flags release) all
433clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_NATIVE=0 all
434clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_SCPI=0 all
435clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_AMEND_DTB=1 all
Andre Przywaracf78a512021-09-03 14:59:38 +0100436clean_build PLAT=sun50i_h6 $(common_flags) all
437clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_NATIVE=0 all
438clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_SCPI=0 all
439clean_build PLAT=sun50i_h616 $(common_flags) all
440clean_build PLAT=sun50i_r329 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500441
442# Platforms from i.MX
443make AARCH32_SP=optee ARCH=aarch32 ARM_ARCH_MAJOR=7 ARM_CORTEX_A7=yes \
444 CROSS_COMPILE=arm-none-eabi- PLAT=warp7 ${TBB_OPTIONS} \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500445 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500446make AARCH32_SP=optee ARCH=aarch32 CROSS_COMPILE=arm-none-eabi- PLAT=picopi \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500447 $(common_flags) all
Ying-Chun Liu (PaulLiu)f6528982021-11-17 17:20:00 +0800448make PLAT=imx8mm $(common_flags) NEED_BL2=yes MEASURED_BOOT=1 \
laurenw-arm8531e702022-06-09 15:32:37 -0500449 MBOOT_EL_HASH_ALG=sha256 ${TBB_OPTIONS} all
Madhukar Pappireddyc3ec06b2022-05-18 11:15:16 -0500450make PLAT=imx8mn $(common_flags) SDEI_SUPPORT=1 all
Ying-Chun Liu (PaulLiu)413e6102021-09-14 00:22:08 +0800451make PLAT=imx8mp $(common_flags) NEED_BL2=yes ${TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500452
Jacky Baib6cecc82021-06-07 09:49:46 +0800453# Due to the limited OCRAM space that can be used for TF-A, build test
454# will report failure caused by too small RAM size, so comment out the
455# build test for imx8mq in CI. It can also resolve the following ticket:
Zelalemc9531f82020-08-04 15:37:08 -0500456# https://developer.trustedfirmware.org/T626
Jacky Baib6cecc82021-06-07 09:49:46 +0800457#make PLAT=imx8mq $(common_flags release) all
Zelalemc9531f82020-08-04 15:37:08 -0500458
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500459make PLAT=imx8qm $(common_flags) all
460make PLAT=imx8qx $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500461
Jacky Bai87091a62023-06-21 16:25:12 +0800462make PLAT=imx93 $(common_flags) all
463
Olivier Deprezbac70192021-04-02 08:55:36 +0200464# Platforms for NXP Layerscape
Jiafei Pane48e56c2021-09-30 10:32:54 +0800465nxp_sb_flags="TRUSTED_BOARD_BOOT=1 CST_DIR=$(pwd) SPD=opteed"
466nxp_sb_fuse_flags="${nxp_sb_flags} FUSE_PROG=1"
467
468# Platform lx2
Olivier Deprezbac70192021-04-02 08:55:36 +0200469make PLAT=lx2160aqds $(common_flags) all
470make PLAT=lx2160ardb $(common_flags) all
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500471
472#CSF Based CoT:
Jiafei Pane48e56c2021-09-30 10:32:54 +0800473clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
474 $nxp_sb_fuse_flags DDR_PHY_BIN_PATH=$(pwd)
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500475
476#X509 Based CoT
Jiafei Pane48e56c2021-09-30 10:32:54 +0800477clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
478 $nxp_sb_flags GENERATE_COT=1 \
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500479 MBEDTLS_DIR=$(pwd)/mbedtls
480
481#BOOT_MODE=emmc and Stack protector
Jiafei Pane48e56c2021-09-30 10:32:54 +0800482clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=emmc \
483 $nxp_sb_fuse_flags ENABLE_STACK_PROTECTOR=strong
484
485# Platform ls1028ardb
486clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor
487clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc
488clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd
489
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800490# ls1028a Secure Boot
Jiafei Pane48e56c2021-09-30 10:32:54 +0800491clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor $nxp_sb_fuse_flags
492clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
493clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
Olivier Deprezbac70192021-04-02 08:55:36 +0200494
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800495# Platform ls1043ardb
496clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor
497clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand
498clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd
499
500# ls1043ardb Secure Boot
501clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
502clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
503clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
504
Jiafei Panbd0c22a2022-01-29 00:04:44 +0800505# ls1046ardb Secure Boot
506clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
507clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
508clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
509
510# ls1046afrwy Secure Boot
511clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
512clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
513
514# ls1046aqds Secure Boot
515clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
516clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
517clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
518clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
519
Jiafei Pan332cd792022-02-24 16:44:48 +0800520# ls1088ardb Secure Boot
521clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
522clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
523
524# ls1088aqds Secure Boot
525clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
526clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
527clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
528
Zelalemc9531f82020-08-04 15:37:08 -0500529# Platforms from Intel
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500530make PLAT=stratix10 $(common_flags) all
531make PLAT=agilex $(common_flags) all
Sieu Mun Tang9081bac2023-05-29 18:08:24 +0800532make PLAT=agilex5 $(common_flags) all
Sieu Mun Tang03b57362022-03-05 01:54:59 +0800533make PLAT=n5x $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500534
535# Platforms from Broadcom
Madhukar Pappireddy97ad2582021-11-15 10:29:23 -0600536clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t \
537 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 DRIVER_I2C_ENABLE=1
538clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t-ns3 \
539 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 USE_USB=yes
Zelalemc9531f82020-08-04 15:37:08 -0500540
541# Platforms from Marvell
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500542make PLAT=a3700 $(common_flags) SCP_BL2=/dev/null CM3_SYSTEM_RESET=1 \
Manish Pandey9ef33c52022-10-25 16:41:49 +0100543 A3720_DB_PM_WAKEUP_SRC=1 HANDLE_EA_EL3_FIRST_NS=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500544
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600545# Source files from mv-ddr-marvell repository are necessary
546# to build below four platforms
Manish Pandey7c1e7452021-11-05 12:54:15 +0000547wget https://downloads.trustedfirmware.org/tf-a/mv-ddr-marvell/mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
548tar -xzf mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600549mv mv-ddr-marvell drivers/marvell/mv_ddr
Zelalemc9531f82020-08-04 15:37:08 -0500550
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600551# These platforms from Marvell have dependency on GCC-6.2.1 toolchain
Pali Rohár8f890402021-07-19 13:48:05 +0200552make PLAT=a80x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200553 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200554make PLAT=a80x0_mcbin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200555 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200556make PLAT=a70x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200557 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200558make PLAT=a70x0_amc DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200559 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Robert Markodf3319e2021-10-20 11:01:12 +0200560make PLAT=a70x0_mochabin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
561 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200562make PLAT=a80x0_puzzle DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200563 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200564make PLAT=t9130 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200565 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500566make PLAT=t9130_cex7_eval DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
567 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500568
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600569# Removing the source files
570rm -rf drivers/marvell/mv_ddr 2> /dev/null
Zelalemc9531f82020-08-04 15:37:08 -0500571
572# Platforms from Meson
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500573make PLAT=gxbb $(common_flags) all
574make PLAT=gxl $(common_flags) all
575make PLAT=g12a $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500576
577# Platforms from Renesas
578# Renesas R-Car D3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500579clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500580 BL33=Makefile LIFEC_DBSC_PROTECT_ENABLE=0 LSI=D3 \
581 MBEDTLS_DIR=$(pwd)/mbedtls PMIC_ROHM_BD9571=0 \
582 RCAR_AVS_SETTING_ENABLE=0 SPD=none RCAR_LOSSY_ENABLE=0 \
583 RCAR_SA0_SIZE=0 RCAR_SYSTEM_SUSPEND=0 TRUSTED_BOARD_BOOT=1
584
585# Renesas R-Car H3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500586clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500587 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3 \
588 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
589 RCAR_DRAM_SPLIT=1 RCAR_GEN3_ULCB=1 SPD=opteed \
590 TRUSTED_BOARD_BOOT=1
591
592# Renesas R-Car H3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500593clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500594 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3N \
595 SPD=opteed TRUSTED_BOARD_BOOT=1
596
597# Renesas R-Car M3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500598clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500599 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3 \
600 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
601 RCAR_DRAM_SPLIT=2 RCAR_GEN3_ULCB=1 SPD=opteed \
602 TRUSTED_BOARD_BOOT=1
603
604# Renesas R-Car M3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500605clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500606 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3N \
607 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
608 RCAR_GEN3_ULCB=1 SPD=opteed TRUSTED_BOARD_BOOT=1
609
610# Renesas R-Car E3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500611clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500612 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=E3 \
613 RCAR_AVS_SETTING_ENABLE=0 RCAR_DRAM_DDR3L_MEMCONF=0 \
614 RCAR_SA0_SIZE=0 SPD=opteed TRUSTED_BOARD_BOOT=1
615
616# Renesas R-Car V3M Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500617clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500618 MBEDTLS_DIR=$(pwd)/mbedtls BL33=Makefile LSI=V3M MACHINE=eagle \
619 PMIC_ROHM_BD9571=0 RCAR_DRAM_SPLIT=0 RCAR_SYSTEM_SUSPEND=0 \
620 AVS_SETTING_ENABLE=0 SPD=none TRUSTED_BOARD_BOOT=1
621
Zelalemf4299672021-01-29 12:52:59 -0600622# Renesas HiHope RZ/G2M development kit
623clean_build PLAT=rzg $(common_flags) \
624 MBEDTLS_DIR=$(pwd)/mbedtls LSI=G2M \
625 RCAR_DRAM_SPLIT=2 RCAR_LOSSY_ENABLE=1 SPD=none
626
Zelalemc9531f82020-08-04 15:37:08 -0500627# Platforms from ST
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100628stm32mp1_common_flags="$(common_flags) \
629 ARCH=aarch32 \
630 ARM_ARCH_MAJOR=7 \
631 CROSS_COMPILE=arm-none-eabi- \
632 ENABLE_STACK_PROTECTOR=strong \
633 PLAT=stm32mp1"
634
Yann Gautiera69cf792021-09-01 11:19:01 +0200635# STM32MP1 SDMMC boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000636make ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200637 BUILD_PLAT=build/stm32mp1-sdmmc/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100638 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200639
Yann Gautier15c45392023-08-21 11:03:33 +0200640# STM32MP1 SDMMC boot BL2 without AARCH32_SP
641make ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
642 BUILD_PLAT=build/stm32mp1-sdmmc/debug \
643 bl2
644
Yann Gautiera69cf792021-09-01 11:19:01 +0200645# STM32MP1 eMMC boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000646make ${stm32mp1_common_flags} STM32MP_EMMC=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200647 BUILD_PLAT=build/stm32mp1-emmc/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100648 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200649
650# STM32MP1 Raw NAND boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000651make ${stm32mp1_common_flags} STM32MP_RAW_NAND=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200652 BUILD_PLAT=build/stm32mp1-nand/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100653 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200654
655# STM32MP1 SPI NAND boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000656make ${stm32mp1_common_flags} STM32MP_SPI_NAND=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200657 BUILD_PLAT=build/stm32mp1-snand/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100658 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200659
660# STM32MP1 SPI NOR boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000661make ${stm32mp1_common_flags} STM32MP_SPI_NOR=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200662 BUILD_PLAT=build/stm32mp1-snor/debug \
Govindraj Raja95f855c2023-03-01 13:11:42 +0000663 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200664
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100665# STM32MP1 UART boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000666make ${stm32mp1_common_flags} STM32MP_UART_PROGRAMMER=1 \
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100667 BUILD_PLAT=build/stm32mp1-uart/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100668 AARCH32_SP=sp_min bl2 bl32
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100669
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200670# STM32MP1 USB boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000671make ${stm32mp1_common_flags} STM32MP_USB_PROGRAMMER=1 \
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200672 BUILD_PLAT=build/stm32mp1-usb/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100673 AARCH32_SP=sp_min bl2 bl32
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200674
Lionel Debieve8f464c02022-10-13 09:25:45 +0200675# STM32MP1 TBBR
Govindraj Raja95f855c2023-03-01 13:11:42 +0000676make ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
Yann Gautier741e8492022-11-14 19:04:27 +0100677 BUILD_PLAT=build/stm32mp1-sdmmc-tbbr/debug \
Lionel Debieve8f464c02022-10-13 09:25:45 +0200678 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100679 AARCH32_SP=sp_min bl2 bl32
Lionel Debieve8f464c02022-10-13 09:25:45 +0200680
Govindraj Raja95f855c2023-03-01 13:11:42 +0000681stm32mp13_common_flags="${stm32mp1_common_flags} \
682 AARCH32_SP=optee \
683 STM32MP13=1"
684
Yann Gautier773c5502022-03-10 17:24:47 +0100685# STM32MP13 SDMMC boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000686make ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100687 BUILD_PLAT=build/stm32mp1-mp13-sdmmc/debug bl2
Yann Gautier773c5502022-03-10 17:24:47 +0100688
Lionel Debieve8f464c02022-10-13 09:25:45 +0200689# STM32MP13 TBBR
Govindraj Raja95f855c2023-03-01 13:11:42 +0000690make ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Lionel Debieve8f464c02022-10-13 09:25:45 +0200691 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100692 BUILD_PLAT=build/stm32mp1-mp13-sdmmc-tbbr/debug bl2
Lionel Debieve8f464c02022-10-13 09:25:45 +0200693
Yann Gautiera66e5012022-12-13 13:52:35 +0100694# STM32MP13 TBBR DECRYPTION AES GCM
Govindraj Raja95f855c2023-03-01 13:11:42 +0000695make ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Yann Gautiera66e5012022-12-13 13:52:35 +0100696 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
697 DECRYPTION_SUPPORT=aes_gcm ENCRYPT_BL32=1 \
698 BUILD_PLAT=build/stm32mp1-mp13-sdmmc-tbbr-dec/debug bl2
699
Yann Gautiere9da1e22023-08-11 14:50:04 +0200700stm32mp2_common_flags="$(common_flags) \
701 ARCH=aarch64 \
702 CROSS_COMPILE=aarch64-none-elf- \
703 PLAT=stm32mp2"
704
705# STM32MP25 SDMMC boot
706make ${stm32mp2_common_flags} STM32MP_SDMMC=1 \
707 SPD=opteed STM32MP_DDR4_TYPE=1 \
708 BUILD_PLAT=build/stm32mp2-mp25-sdmmc/debug
709
Zelalemc9531f82020-08-04 15:37:08 -0500710# Platforms from TI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500711make PLAT=k3 $(common_flags) all
Hari Nagalladadd89f2022-08-30 12:10:00 -0500712make PLAT=k3 TARGET_BOARD=j784s4 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500713
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500714clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS}
Zelalemc9531f82020-08-04 15:37:08 -0500715# Use GICV3 driver
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500716clean_build PLAT=qemu $(common_flags) QEMU_USE_GIC_DRIVER=QEMU_GICV3 \
Zelalemc9531f82020-08-04 15:37:08 -0500717 ENABLE_STACK_PROTECTOR=strong
Dongjiu Geng72819ee2023-06-16 18:48:57 +0800718# Use GICV3 driver with SDEI support
719clean_build PLAT=qemu $(common_flags) QEMU_USE_GIC_DRIVER=QEMU_GICV3 \
720 ENABLE_STACK_PROTECTOR=strong SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Zelalemc9531f82020-08-04 15:37:08 -0500721# Use encrypted FIP feature.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500722clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500723 BL32_RAM_LOCATION=tdram DECRYPTION_SUPPORT=aes_gcm ENCRYPT_BL31=1 \
724 ENCRYPT_BL32=1 FW_ENC_STATUS=0 SPD=opteed
Jens Wiklander1a9c2be2021-11-26 09:56:55 +0100725# QEMU with SPMD support
726clean_build PLAT=qemu $(common_flags) BL32=Makefile \
727 BL32_RAM_LOCATION=tdram ARM_BL31_IN_DRAM=1 \
728 SPD=spmd CTX_INCLUDE_EL2_REGS=0 SPMD_SPM_AT_SEL2=0 SPMC_OPTEE=1
Ruchika Gupta86e7f682022-04-12 10:25:46 +0530729# Measured Boot
laurenw-arm8531e702022-06-09 15:32:37 -0500730clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} MBOOT_EL_HASH_ALG=sha256 MEASURED_BOOT=1
Raymond Mao7681ba02023-08-10 14:05:44 -0700731# Transfer List
732clean_build PLAT=qemu $(common_flags) TRANSFER_LIST=1
Zelalemc9531f82020-08-04 15:37:08 -0500733
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500734clean_build PLAT=qemu_sbsa $(common_flags)
Fathi Boudra422bf772019-12-02 11:10:16 +0200735
Zelalemd86e8762020-08-21 18:24:28 -0500736# QEMU with SPM support
737clean_build PLAT=qemu_sbsa $(common_flags) BL32=Makefile SPM_MM=1 \
Paul Sokolovskycf9fe862023-01-02 16:22:21 +0300738 EL3_EXCEPTION_HANDLING=1 ENABLE_SME_FOR_NS=0 ENABLE_SVE_FOR_NS=0
Zelalemd86e8762020-08-21 18:24:28 -0500739
Fathi Boudra422bf772019-12-02 11:10:16 +0200740# For hikey enable PMF to include all files in the platform port
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500741make PLAT=hikey $(common_flags) ${TBB_OPTIONS} ENABLE_PMF=1 all
742make PLAT=hikey960 $(common_flags) ${TBB_OPTIONS} all
Lukas Haneld0752392022-10-13 11:13:19 +0200743make PLAT=hikey960 $(common_flags) ${TBB_OPTIONS} SPD=spmd SPMC_AT_EL3=1 \
744 SPMD_SPM_AT_SEL2=0 BL32=optee PLAT_SP_MANIFEST_DTS=foo NEED_FDT=no all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500745make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200746
Zelalemc9531f82020-08-04 15:37:08 -0500747# Platforms from Socionext
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500748clean_build PLAT=uniphier $(common_flags) ${TBB_OPTIONS} SPD=tspd
749clean_build PLAT=uniphier $(common_flags) FIP_GZIP=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200750
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500751clean_build PLAT=synquacer $(common_flags) SPM_MM=1 \
Jassi Brar86080922022-06-27 14:16:34 -0500752 RESET_TO_BL31=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0 \
753 PRELOADED_BL33_BASE=0x0
Zelalemc9531f82020-08-04 15:37:08 -0500754
755# Support for SCP Message Interface protocol with platform specific drivers
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500756clean_build PLAT=synquacer $(common_flags) \
Jassi Brar86080922022-06-27 14:16:34 -0500757 RESET_TO_BL31=1 PRELOADED_BL33_BASE=0x0 SQ_USE_SCMI_DRIVER=1
Zelalemc9531f82020-08-04 15:37:08 -0500758
Jassi Brarb8c7ca02022-06-27 14:22:10 -0500759# Support for BL2 and TBBR
760clean_build PLAT=synquacer $(common_flags) \
761 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
762 SQ_USE_SCMI_DRIVER=1 SPD=opteed all
763
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500764make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200765
Zelalemc9531f82020-08-04 15:37:08 -0500766# Raspberry Pi Platforms
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500767make PLAT=rpi3 $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500768 ENABLE_STACK_PROTECTOR=strong PRELOADED_BL33_BASE=0xDEADBEEF all
Andre Przywarae917ec82021-09-03 15:01:30 +0100769clean_build PLAT=rpi4 $(common_flags) SMC_PCI_SUPPORT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200770
Zelalemc9531f82020-08-04 15:37:08 -0500771# A113D (AXG) platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500772clean_build PLAT=axg $(common_flags) SPD=opteed
773clean_build PLAT=axg $(common_flags) AML_USE_ATOS=1
Zelalemc9531f82020-08-04 15:37:08 -0500774
Stephan Gerhold141a7662021-12-07 20:42:14 +0100775# QTI MSM8916 platform
Stephan Gerhold3b3976f2023-04-17 16:27:11 +0200776clean_build PLAT=mdm9607 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
777 ARCH=aarch32 AARCH32_SP=sp_min
778clean_build PLAT=msm8909 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
779 ARCH=aarch32 AARCH32_SP=sp_min
Stephan Gerhold141a7662021-12-07 20:42:14 +0100780clean_build PLAT=msm8916 $(common_flags)
Manish V Badarkhec540e622023-06-28 17:56:40 +0100781clean_build PLAT=msm8916 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
782 ARCH=aarch32 AARCH32_SP=sp_min
Stephan Gerhold998f0d62023-04-17 16:22:52 +0200783clean_build PLAT=msm8916 $(common_flags) SPD=tspd
Stephan Gerhold3b3976f2023-04-17 16:27:11 +0200784clean_build PLAT=msm8939 $(common_flags)
785clean_build PLAT=msm8939 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
786 ARCH=aarch32 AARCH32_SP=sp_min
787clean_build PLAT=msm8939 $(common_flags) SPD=tspd
Stephan Gerhold141a7662021-12-07 20:42:14 +0100788
Chia-Wei Wang7dcb0d02023-06-09 09:52:52 +0800789# Platforms from Aspeed
790clean_build PLAT=ast2700 $(common_flags) SPD=opteed
791
rutigl@gmail.com86cfcf92023-03-21 10:10:11 +0200792# Nuvoton npcm845x platform
793make PLAT=npcm845x $(common_flags) all SPD=opteed
794
Harrison Mutaiee958c12023-09-06 12:16:21 +0100795if [[ "$rc" -gt 0 ]]; then
796 echo "ERROR: tc-cov-make failed with $error_count failures"
797 exit $rc
798fi
799
Fathi Boudra422bf772019-12-02 11:10:16 +0200800cd ..