blob: 04f6a18aee07fbd699fed824b837715cc1f76bf0 [file] [log] [blame]
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -05001#!/usr/bin/env bash
Fathi Boudra422bf772019-12-02 11:10:16 +02002#
Manish V Badarkhe107c8e32021-08-02 19:49:32 +01003# Copyright (c) 2019-2021, Arm Limited. All rights reserved.
Fathi Boudra422bf772019-12-02 11:10:16 +02004#
5# SPDX-License-Identifier: BSD-3-Clause
6#
7
8#
9# This script builds the TF in different configs.
10# Rather than telling cov-build to build TF using a simple 'make all' command,
11# the goal here is to combine several build flags to analyse more of our source
12# code in a single 'build'. The Coverity Scan service does not have the notion
13# of separate types of build - there is just one linear sequence of builds in
14# the project history.
15#
16
17# Bail out as soon as an error is encountered.
18set -e
19
20TF_SOURCES=$1
21if [ ! -d "$TF_SOURCES" ]; then
22 echo "ERROR: '$TF_SOURCES' does not exist or is not a directory"
23 echo "Usage: $(basename "$0") <trusted-firmware-directory>"
24 exit 1
25fi
26
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050027containing_dir="$(readlink -f "$(dirname "$0")/")"
28. $containing_dir/common-def.sh
29
Fathi Boudra422bf772019-12-02 11:10:16 +020030# Get mbed TLS library code to build Trusted Firmware with Trusted Board Boot
31# support. The version of mbed TLS to use here must be the same as when
32# building TF in the usual context.
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050033if [ ! -d "$MBED_TLS_DIR" ]; then
34 git clone -q --depth 1 -b "$MBED_TLS_SOURCES_TAG" "$MBED_TLS_URL_REPO" "$MBED_TLS_DIR"
Fathi Boudra422bf772019-12-02 11:10:16 +020035fi
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050036
Fathi Boudra422bf772019-12-02 11:10:16 +020037cd "$TF_SOURCES"
38
39# Clean TF source dir to make sure we don't analyse temporary files.
40make distclean
41
42#
43# Build TF in different configurations to get as much coverage as possible
44#
45
Fathi Boudra422bf772019-12-02 11:10:16 +020046#
47# FVP platform
48# We'll use the following flags for all FVP builds.
49#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050050fvp_common_flags="$(common_flags) PLAT=fvp"
Fathi Boudra422bf772019-12-02 11:10:16 +020051
52# Try all possible SPDs.
53clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd
54clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd TSP_INIT_ASYNC=1 \
55 TSP_NS_INTR_ASYNC_PREEMPT=1
56clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed
57clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tlkd
58
Zelalemc9531f82020-08-04 15:37:08 -050059# Dualroot chain of trust.
60clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tspd COT=dualroot
61
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050062clean_build $fvp_common_flags SPD=trusty
63clean_build $fvp_common_flags SPD=trusty TRUSTY_SPD_WITH_GENERIC_SERVICES=1
Fathi Boudra422bf772019-12-02 11:10:16 +020064
65# SDEI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050066clean_build $fvp_common_flags SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Fathi Boudra422bf772019-12-02 11:10:16 +020067
Zelalemc9531f82020-08-04 15:37:08 -050068# SDEI with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050069clean_build $fvp_common_flags SDEI_IN_FCONF=1 SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Zelalemc9531f82020-08-04 15:37:08 -050070
Zelalem4f3633e2021-06-18 11:53:47 -050071# PCI Service
72clean_build $fvp_common_flags SMC_PCI_SUPPORT=1
73
Zelalemc9531f82020-08-04 15:37:08 -050074# Secure interrupt descriptors with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050075clean_build $fvp_common_flags SEC_INT_DESC_IN_FCONF=1
Zelalemc9531f82020-08-04 15:37:08 -050076
Fathi Boudra422bf772019-12-02 11:10:16 +020077# Without coherent memory
78clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd USE_COHERENT_MEM=0
79
80# Using PSCI extended State ID format rather than the original format
81clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd PSCI_EXTENDED_STATE_ID=1 \
82 ARM_RECOM_STATE_ID_ENC=1
83
84# Alternative boot flows (This changes some of the platform initialisation code)
85clean_build $fvp_common_flags EL3_PAYLOAD=0x80000000
86clean_build $fvp_common_flags PRELOADED_BL33_BASE=0x80000000
87
88# Using the SP804 timer instead of the Generic Timer
89clean_build $fvp_common_flags FVP_USE_SP804_TIMER=1
90
91# Using the CCN driver and multi cluster topology
92clean_build $fvp_common_flags FVP_CLUSTER_COUNT=4
93
94# PMF
95clean_build $fvp_common_flags ENABLE_PMF=1
96
97# stack protector
98clean_build $fvp_common_flags ENABLE_STACK_PROTECTOR=strong
99
100# AArch32 build
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500101clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200102 ARCH=aarch32 AARCH32_SP=sp_min \
103 RESET_TO_SP_MIN=1 PRELOADED_BL33_BASE=0x80000000
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500104clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200105 ARCH=aarch32 AARCH32_SP=sp_min
106
107# Xlat tables lib version 1 (AArch64 and AArch32)
108clean_build $fvp_common_flags ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500109clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200110 ARCH=aarch32 AARCH32_SP=sp_min ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
111
Zelalemc9531f82020-08-04 15:37:08 -0500112# SPM support based on Management Mode Interface Specification
113clean_build $fvp_common_flags SPM_MM=1 EL3_EXCEPTION_HANDLING=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200114
Zelalemc9531f82020-08-04 15:37:08 -0500115# SPM support with TOS(optee) as SPM sitting at S-EL1
116clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0
117
118# SPM support with Secure hafnium as SPM sitting at S-EL2
119# SP_LAYOUT_FILE is used only during FIP creation but build won't progress
120# if we have NULL value to it, so passing a dummy string.
121clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=1 ARM_ARCH_MINOR=4 \
Max Shvetsov44d2a702021-02-18 16:41:45 +0000122 CTX_INCLUDE_EL2_REGS=1 SP_LAYOUT_FILE=dummy
Fathi Boudra422bf772019-12-02 11:10:16 +0200123
124#BL2 at EL3 support
125clean_build $fvp_common_flags BL2_AT_EL3=1
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500126clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200127 ARCH=aarch32 AARCH32_SP=sp_min BL2_AT_EL3=1
128
Zelalemc9531f82020-08-04 15:37:08 -0500129# RAS Extension Support
130clean_build $fvp_common_flags EL3_EXCEPTION_HANDLING=1 \
131 FAULT_INJECTION_SUPPORT=1 HANDLE_EA_EL3_FIRST=1 RAS_EXTENSION=1 \
132 SDEI_SUPPORT=1
133
134# Hardware Assisted Coherency(DynamIQ)
135clean_build $fvp_common_flags FVP_CLUSTER_COUNT=1 FVP_MAX_CPUS_PER_CLUSTER=8 \
136 HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0
137
138# Pointer Authentication Support
139clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 \
140 ARM_ARCH_MINOR=5 EL3_EXCEPTION_HANDLING=1 BRANCH_PROTECTION=1 SDEI_SUPPORT=1 SPD=tspd TSP_NS_INTR_ASYNC_PREEMPT=1
141
142# Undefined Behaviour Sanitizer
143# Building with UBSAN SANITIZE_UB=on increases the executable size.
144# Hence it is only properly supported in bl31 with RESET_TO_BL31 enabled
145make $fvp_common_flags clean
146make $fvp_common_flags SANITIZE_UB=on RESET_TO_BL31=1 bl31
147
148# debugfs feature
149clean_build $fvp_common_flags DEBUG=1 USE_DEBUGFS=1
150
151# MPAM feature
152clean_build $fvp_common_flags ENABLE_MPAM_FOR_LOWER_ELS=1
153
154# Using GICv3.1 driver with extended PPI and SPI range
155clean_build $fvp_common_flags GIC_EXT_INTID=1
156
157# Using GICv4 features with extended PPI and SPI range
158clean_build $fvp_common_flags GIC_ENABLE_V4_EXTN=1 GIC_EXT_INTID=1
159
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100160# Measured Boot
161clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} MEASURED_BOOT=1
162
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100163# CoT descriptors in device tree
Manish V Badarkhe81102d12020-10-05 08:02:30 +0100164clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} COT_DESC_IN_DTB=1 USE_ROMLIB=1
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100165
Manish V Badarkhe107c8e32021-08-02 19:49:32 +0100166# PSA FWU support
167clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_GPT_SUPPORT=1 PSA_FWU_SUPPORT=1 USE_ROMLIB=1
168
Fathi Boudra422bf772019-12-02 11:10:16 +0200169#
170# Juno platform
171# We'll use the following flags for all Juno builds.
172#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500173juno_common_flags="$(common_flags) PLAT=juno"
Fathi Boudra422bf772019-12-02 11:10:16 +0200174clean_build $juno_common_flags SPD=tspd ${ARM_TBB_OPTIONS}
175clean_build $juno_common_flags EL3_PAYLOAD=0x80000000
Madhukar Pappireddydcb31f62021-05-06 11:36:36 -0500176clean_build $juno_common_flags ENABLE_STACK_PROTECTOR=strong ARM_ETHOSN_NPU_DRIVER=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200177clean_build $juno_common_flags CSS_USE_SCMI_SDS_DRIVER=0
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500178
Leonardo Sandoval5163b562020-11-20 17:17:59 -0600179clean_build $juno_common_flags SPD=tspd ${ARM_TBB_OPTIONS} ARM_CRYPTOCELL_INTEG=1 CCSBROM_LIB_PATH=${CRYPTOCELL_LIB_PATH} KEY_SIZE=2048
Fathi Boudra422bf772019-12-02 11:10:16 +0200180
181#
182# System Guidance for Infrastructure platform SGI575
Zelalemc9531f82020-08-04 15:37:08 -0500183# Enable build config with RAS_EXTENSION to cover more files
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500184make $(common_flags) PLAT=sgi575 ${ARM_TBB_OPTIONS} EL3_EXCEPTION_HANDLING=1 FAULT_INJECTION_SUPPORT=1 \
Zelalemc9531f82020-08-04 15:37:08 -0500185 HANDLE_EA_EL3_FIRST=1 RAS_EXTENSION=1 SDEI_SUPPORT=1 SPM_MM=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200186
187#
Vijayenthiran Subramaniam2a47a6d2020-07-22 14:16:58 +0530188# System Guidance for Infrastructure platform RD-N1-Edge-Dual
Fathi Boudra422bf772019-12-02 11:10:16 +0200189#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500190make $(common_flags) PLAT=rdn1edge CSS_SGI_CHIP_COUNT=2 ${ARM_TBB_OPTIONS} all
Fathi Boudra422bf772019-12-02 11:10:16 +0200191
192#
193# System Guidance for Infrastructure platform RD-E1Edge
194#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500195make $(common_flags) PLAT=rde1edge ${ARM_TBB_OPTIONS} CSS_SGI_CHIP_COUNT=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500196
197#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530198# Reference Design platform RD-V1
Zelalemc9531f82020-08-04 15:37:08 -0500199#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530200make $(common_flags) PLAT=rdv1 ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500201
202#
Aditya Angadi61c54762021-01-04 09:30:52 +0530203# Reference Design platform RD-V1-MC
Zelalemc9531f82020-08-04 15:37:08 -0500204#
Aditya Angadi61c54762021-01-04 09:30:52 +0530205make $(common_flags) PLAT=rdv1mc ${ARM_TBB_OPTIONS} CSS_SGI_CHIP_COUNT=4 all
Zelalemc9531f82020-08-04 15:37:08 -0500206
207#
Vijayenthiran Subramaniama66de332020-11-23 14:20:14 +0530208# Reference Design Platform RD-N2
209#
210make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} all
211
212#
Zelalemc9531f82020-08-04 15:37:08 -0500213# Neoverse N1 SDP platform
214#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500215make $(common_flags) PLAT=n1sdp ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500216
217#
218# FVP VE platform
219#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500220make $(common_flags) PLAT=fvp_ve AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500221 CROSS_COMPILE=arm-none-eabi- ARM_ARCH_MAJOR=7 \
222 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
223 FVP_HW_CONFIG_DTS=fdts/fvp-ve-Cortex-A5x1.dts all
224
225#
226# A5 DesignStart Platform
227#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500228make $(common_flags) PLAT=a5ds AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500229 ARM_ARCH_MAJOR=7 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
230 CROSS_COMPILE=arm-none-eabi- FVP_HW_CONFIG_DTS=fdts/a5ds.dts
231
232#
233# Corstone700 Platform
234#
235
236corstone700_common_flags="CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500237 $(common_flags) \
Zelalemc9531f82020-08-04 15:37:08 -0500238 PLAT=corstone700 \
239 ARCH=aarch32 \
240 RESET_TO_SP_MIN=1 \
241 AARCH32_SP=sp_min \
242 ARM_LINUX_KERNEL_AS_BL33=0 \
243 ARM_PRELOADED_DTB_BASE=0x80400000 \
244 ENABLE_PIE=1 \
Zelalemc9531f82020-08-04 15:37:08 -0500245 ENABLE_STACK_PROTECTOR=all \
246 all"
247
248echo "Info: Building Corstone700 FVP ..."
249
250make TARGET_PLATFORM=fvp ${corstone700_common_flags}
251
252echo "Info: Building Corstone700 FPGA ..."
253
254make TARGET_PLATFORM=fpga ${corstone700_common_flags}
255
256#
257# Arm internal FPGA port
258#
Andre Przywara268c5c72021-09-03 14:56:56 +0100259make PLAT=arm_fpga $(common_flags) \
Zelalemc9531f82020-08-04 15:37:08 -0500260 FPGA_PRELOADED_DTB_BASE=0x88000000 PRELOADED_BL33_BASE=0x82080000 all
261
262#
Usama Arifcba711d2021-08-04 15:53:42 +0100263# Total Compute platforms
Zelalemc9531f82020-08-04 15:37:08 -0500264#
Usama Arifcba711d2021-08-04 15:53:42 +0100265make $(common_flags) PLAT=tc TARGET_PLATFORM=0 ${ARM_TBB_OPTIONS} all
266make $(common_flags) PLAT=tc TARGET_PLATFORM=1 ${ARM_TBB_OPTIONS} all
Fathi Boudra422bf772019-12-02 11:10:16 +0200267
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530268#
269# Morello platform
270#
271make $(common_flags) PLAT=morello all
272
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100273#
274# diphda Platform
275#
276
277make $(common_flags) \
278 PLAT=diphda \
279 SPD=spmd \
280 TARGET_PLATFORM=fpga \
281 ENABLE_STACK_PROTECTOR=strong \
282 ENABLE_PIE=1 \
283 BL2_AT_EL3=1 \
284 SPMD_SPM_AT_SEL2=0 \
285 ${ARM_TBB_OPTIONS} \
286 CREATE_KEYS=1 \
287 COT=tbbr \
288 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
289 bl2 \
290 bl31
291
Fathi Boudra422bf772019-12-02 11:10:16 +0200292# Partners' platforms.
293# Enable as many features as possible.
294# We don't need to clean between each build here because we only do one build
295# per platform so we don't hit the build flags dependency problem.
Fathi Boudra422bf772019-12-02 11:10:16 +0200296
Manish Pandey9c0ee742021-07-08 09:55:59 +0100297# Platforms from Mediatek
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500298make PLAT=mt8173 $(common_flags) all
299make PLAT=mt8183 $(common_flags) all
Zelalemd86e8762020-08-21 18:24:28 -0500300make PLAT=mt8192 $(common_flags) COREBOOT=1 all
Manish Pandey9c0ee742021-07-08 09:55:59 +0100301make PLAT=mt8195 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500302
303# Platforms from Qualcomm
304make PLAT=sc7180 $(common_flags) COREBOOT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200305
Zelalemc9531f82020-08-04 15:37:08 -0500306make PLAT=rk3288 CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500307 $(common_flags) ARCH=aarch32 AARCH32_SP=sp_min all
Madhukar Pappireddyd491ad02020-12-03 10:37:05 -0600308make PLAT=rk3368 $(common_flags) COREBOOT=1 \
309 ENABLE_STACK_PROTECTOR=strong all
310make PLAT=rk3399 $(common_flags) COREBOOT=1 PLAT_RK_DP_HDCP=1 \
311 ENABLE_STACK_PROTECTOR=strong all
312make PLAT=rk3328 $(common_flags) COREBOOT=1 PLAT_RK_SECURE_DDR_MINILOADER=1 \
313 ENABLE_STACK_PROTECTOR=strong all
314make PLAT=px30 $(common_flags) PLAT_RK_SECURE_DDR_MINILOADER=1 \
315 ENABLE_STACK_PROTECTOR=strong all
Fathi Boudra422bf772019-12-02 11:10:16 +0200316
317# Although we do several consecutive builds for the Tegra platform below, we
318# don't need to clean between each one because the Tegra makefiles specify
319# a different build directory per SoC.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500320make PLAT=tegra TARGET_SOC=t210 $(common_flags) all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500321make PLAT=tegra TARGET_SOC=t186 $(common_flags) all
322make PLAT=tegra TARGET_SOC=t194 $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200323
324# For the Xilinx platform, artificially increase the extents of BL31 memory
325# (using the platform-specific build options ZYNQMP_ATF_MEM_{BASE,SIZE}).
326# If we keep the default values, BL31 doesn't fit when it is built with all
327# these build flags.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500328make PLAT=zynqmp $(common_flags) \
Fathi Boudra422bf772019-12-02 11:10:16 +0200329 RESET_TO_BL31=1 SPD=tspd \
Zelalem4f3633e2021-06-18 11:53:47 -0500330 SDEI_SUPPORT=1 \
Fathi Boudra422bf772019-12-02 11:10:16 +0200331 ZYNQMP_ATF_MEM_BASE=0xFFFC0000 ZYNQMP_ATF_MEM_SIZE=0x00040000 \
332 all
333
Zelalemc9531f82020-08-04 15:37:08 -0500334# Build both for silicon (default) and virtual QEMU platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500335clean_build PLAT=versal $(common_flags)
336clean_build PLAT=versal $(common_flags) VERSAL_PLATFORM=versal_virt
Zelalemc9531f82020-08-04 15:37:08 -0500337
338# Platforms from Allwinner
Andre Przywaracf78a512021-09-03 14:59:38 +0100339clean_build PLAT=sun50i_a64 $(common_flags) all
340clean_build PLAT=sun50i_a64 $(common_flags) SUNXI_PSCI_USE_NATIVE=0 all
341clean_build PLAT=sun50i_a64 $(common_flags) SUNXI_PSCI_USE_SCPI=0 all
342clean_build PLAT=sun50i_h6 $(common_flags) all
343clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_NATIVE=0 all
344clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_SCPI=0 all
345clean_build PLAT=sun50i_h616 $(common_flags) all
346clean_build PLAT=sun50i_r329 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500347
348# Platforms from i.MX
349make AARCH32_SP=optee ARCH=aarch32 ARM_ARCH_MAJOR=7 ARM_CORTEX_A7=yes \
350 CROSS_COMPILE=arm-none-eabi- PLAT=warp7 ${TBB_OPTIONS} \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500351 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500352make AARCH32_SP=optee ARCH=aarch32 CROSS_COMPILE=arm-none-eabi- PLAT=picopi \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500353 $(common_flags) all
354make PLAT=imx8mm $(common_flags) all
355make PLAT=imx8mn $(common_flags) all
356make PLAT=imx8mp $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500357
Jacky Baib6cecc82021-06-07 09:49:46 +0800358# Due to the limited OCRAM space that can be used for TF-A, build test
359# will report failure caused by too small RAM size, so comment out the
360# build test for imx8mq in CI. It can also resolve the following ticket:
Zelalemc9531f82020-08-04 15:37:08 -0500361# https://developer.trustedfirmware.org/T626
Jacky Baib6cecc82021-06-07 09:49:46 +0800362#make PLAT=imx8mq $(common_flags release) all
Zelalemc9531f82020-08-04 15:37:08 -0500363
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500364make PLAT=imx8qm $(common_flags) all
365make PLAT=imx8qx $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500366
Olivier Deprezbac70192021-04-02 08:55:36 +0200367# Platforms for NXP Layerscape
368make PLAT=lx2160aqds $(common_flags) all
369make PLAT=lx2160ardb $(common_flags) all
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500370
371#CSF Based CoT:
372clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor SPD=opteed \
373 TRUSTED_BOARD_BOOT=1 CST_DIR=$(pwd) DDR_PHY_BIN_PATH=$(pwd)
374
375#X509 Based CoT
376clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor SPD=opteed \
377 TRUSTED_BOARD_BOOT=1 CST_DIR=$(pwd) GENERATE_COT=1 \
378 MBEDTLS_DIR=$(pwd)/mbedtls
379
380#BOOT_MODE=emmc and Stack protector
381clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=emmc SPD=opteed \
382 TRUSTED_BOARD_BOOT=1 CST_DIR=$(pwd) ENABLE_STACK_PROTECTOR=strong
Olivier Deprezbac70192021-04-02 08:55:36 +0200383
Zelalemc9531f82020-08-04 15:37:08 -0500384# Platforms from Intel
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500385make PLAT=stratix10 $(common_flags) all
386make PLAT=agilex $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500387
388# Platforms from Broadcom
Olivier Deprez07cc98b2021-04-02 09:56:55 +0200389clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t INCLUDE_EMMC_DRIVER_ERASE_CODE=1 DRIVER_I2C_ENABLE=1
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500390clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t-ns3 INCLUDE_EMMC_DRIVER_ERASE_CODE=1
Zelalemc9531f82020-08-04 15:37:08 -0500391
392# Platforms from Marvell
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500393make PLAT=a3700 $(common_flags) SCP_BL2=/dev/null CM3_SYSTEM_RESET=1 \
394 A3720_DB_PM_WAKEUP_SRC=1 HANDLE_EA_EL3_FIRST=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500395
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600396# Source files from mv-ddr-marvell repository are necessary
397# to build below four platforms
Pali Rohár6d8ddb42021-07-15 21:33:50 +0200398wget https://downloads.trustedfirmware.org/tf-a/mv-ddr-marvell/mv-ddr-marvell-02e23dbcf8dd22e038986052d99319a0eba8f25f.tar.gz 2> /dev/null
399tar -xzf mv-ddr-marvell-02e23dbcf8dd22e038986052d99319a0eba8f25f.tar.gz 2> /dev/null
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600400mv mv-ddr-marvell drivers/marvell/mv_ddr
Zelalemc9531f82020-08-04 15:37:08 -0500401
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600402# These platforms from Marvell have dependency on GCC-6.2.1 toolchain
Pali Rohár8f890402021-07-19 13:48:05 +0200403make PLAT=a80x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200404 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200405make PLAT=a80x0_mcbin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200406 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200407make PLAT=a70x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200408 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200409make PLAT=a70x0_amc DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200410 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200411make PLAT=a80x0_puzzle DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200412 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200413make PLAT=t9130 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200414 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500415make PLAT=t9130_cex7_eval DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
416 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500417
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600418# Removing the source files
419rm -rf drivers/marvell/mv_ddr 2> /dev/null
Zelalemc9531f82020-08-04 15:37:08 -0500420
421# Platforms from Meson
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500422make PLAT=gxbb $(common_flags) all
423make PLAT=gxl $(common_flags) all
424make PLAT=g12a $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500425
426# Platforms from Renesas
427# Renesas R-Car D3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500428clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500429 BL33=Makefile LIFEC_DBSC_PROTECT_ENABLE=0 LSI=D3 \
430 MBEDTLS_DIR=$(pwd)/mbedtls PMIC_ROHM_BD9571=0 \
431 RCAR_AVS_SETTING_ENABLE=0 SPD=none RCAR_LOSSY_ENABLE=0 \
432 RCAR_SA0_SIZE=0 RCAR_SYSTEM_SUSPEND=0 TRUSTED_BOARD_BOOT=1
433
434# Renesas R-Car H3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500435clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500436 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3 \
437 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
438 RCAR_DRAM_SPLIT=1 RCAR_GEN3_ULCB=1 SPD=opteed \
439 TRUSTED_BOARD_BOOT=1
440
441# Renesas R-Car H3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500442clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500443 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3N \
444 SPD=opteed TRUSTED_BOARD_BOOT=1
445
446# Renesas R-Car M3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500447clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500448 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3 \
449 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
450 RCAR_DRAM_SPLIT=2 RCAR_GEN3_ULCB=1 SPD=opteed \
451 TRUSTED_BOARD_BOOT=1
452
453# Renesas R-Car M3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500454clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500455 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3N \
456 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
457 RCAR_GEN3_ULCB=1 SPD=opteed TRUSTED_BOARD_BOOT=1
458
459# Renesas R-Car E3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500460clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500461 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=E3 \
462 RCAR_AVS_SETTING_ENABLE=0 RCAR_DRAM_DDR3L_MEMCONF=0 \
463 RCAR_SA0_SIZE=0 SPD=opteed TRUSTED_BOARD_BOOT=1
464
465# Renesas R-Car V3M Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500466clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500467 MBEDTLS_DIR=$(pwd)/mbedtls BL33=Makefile LSI=V3M MACHINE=eagle \
468 PMIC_ROHM_BD9571=0 RCAR_DRAM_SPLIT=0 RCAR_SYSTEM_SUSPEND=0 \
469 AVS_SETTING_ENABLE=0 SPD=none TRUSTED_BOARD_BOOT=1
470
Zelalemf4299672021-01-29 12:52:59 -0600471# Renesas HiHope RZ/G2M development kit
472clean_build PLAT=rzg $(common_flags) \
473 MBEDTLS_DIR=$(pwd)/mbedtls LSI=G2M \
474 RCAR_DRAM_SPLIT=2 RCAR_LOSSY_ENABLE=1 SPD=none
475
Zelalemc9531f82020-08-04 15:37:08 -0500476# Platforms from ST
477make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500478 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_EMMC=1 \
Zelalemc9531f82020-08-04 15:37:08 -0500479 STM32MP_RAW_NAND=1 STM32MP_SDMMC=1 STM32MP_SPI_NAND=1 STM32MP_SPI_NOR=1 \
480 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl1 bl2 bl32
481
482# Platforms from TI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500483make PLAT=k3 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500484
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500485clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS}
Zelalemc9531f82020-08-04 15:37:08 -0500486# Use GICV3 driver
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500487clean_build PLAT=qemu $(common_flags) QEMU_USE_GIC_DRIVER=QEMU_GICV3 \
Zelalemc9531f82020-08-04 15:37:08 -0500488 ENABLE_STACK_PROTECTOR=strong
489# Use encrypted FIP feature.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500490clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500491 BL32_RAM_LOCATION=tdram DECRYPTION_SUPPORT=aes_gcm ENCRYPT_BL31=1 \
492 ENCRYPT_BL32=1 FW_ENC_STATUS=0 SPD=opteed
493
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500494clean_build PLAT=qemu_sbsa $(common_flags)
Fathi Boudra422bf772019-12-02 11:10:16 +0200495
Zelalemd86e8762020-08-21 18:24:28 -0500496# QEMU with SPM support
497clean_build PLAT=qemu_sbsa $(common_flags) BL32=Makefile SPM_MM=1 \
498 EL3_EXCEPTION_HANDLING=1
499
Fathi Boudra422bf772019-12-02 11:10:16 +0200500# For hikey enable PMF to include all files in the platform port
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500501make PLAT=hikey $(common_flags) ${TBB_OPTIONS} ENABLE_PMF=1 all
502make PLAT=hikey960 $(common_flags) ${TBB_OPTIONS} all
503make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200504
Zelalemc9531f82020-08-04 15:37:08 -0500505# Platforms from Socionext
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500506clean_build PLAT=uniphier $(common_flags) ${TBB_OPTIONS} SPD=tspd
507clean_build PLAT=uniphier $(common_flags) FIP_GZIP=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200508
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500509clean_build PLAT=synquacer $(common_flags) SPM_MM=1 \
Zelalemc9531f82020-08-04 15:37:08 -0500510 EL3_EXCEPTION_HANDLING=1 PRELOADED_BL33_BASE=0x0
511
512# Support for SCP Message Interface protocol with platform specific drivers
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500513clean_build PLAT=synquacer $(common_flags) \
Zelalemc9531f82020-08-04 15:37:08 -0500514 PRELOADED_BL33_BASE=0x0 SQ_USE_SCMI_DRIVER=1
515
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500516make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200517
Zelalemc9531f82020-08-04 15:37:08 -0500518# Raspberry Pi Platforms
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500519make PLAT=rpi3 $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500520 ENABLE_STACK_PROTECTOR=strong PRELOADED_BL33_BASE=0xDEADBEEF all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500521make PLAT=rpi4 $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200522
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500523# Cannot use $(common_flags) for LS1043 platform, as then
Fathi Boudra422bf772019-12-02 11:10:16 +0200524# the binaries do not fit in memory.
525clean_build PLAT=ls1043 SPD=opteed ENABLE_STACK_PROTECTOR=strong
526clean_build PLAT=ls1043 SPD=tspd
527
Zelalemc9531f82020-08-04 15:37:08 -0500528# A113D (AXG) platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500529clean_build PLAT=axg $(common_flags) SPD=opteed
530clean_build PLAT=axg $(common_flags) AML_USE_ATOS=1
Zelalemc9531f82020-08-04 15:37:08 -0500531
Fathi Boudra422bf772019-12-02 11:10:16 +0200532cd ..