blob: 4692a9b82511734564577cf6eb54940e743bd0dd [file] [log] [blame]
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -05001#!/usr/bin/env bash
Fathi Boudra422bf772019-12-02 11:10:16 +02002#
Yann Gautier773c5502022-03-10 17:24:47 +01003# Copyright (c) 2019-2022, Arm Limited. All rights reserved.
Fathi Boudra422bf772019-12-02 11:10:16 +02004#
5# SPDX-License-Identifier: BSD-3-Clause
6#
7
8#
9# This script builds the TF in different configs.
10# Rather than telling cov-build to build TF using a simple 'make all' command,
11# the goal here is to combine several build flags to analyse more of our source
12# code in a single 'build'. The Coverity Scan service does not have the notion
13# of separate types of build - there is just one linear sequence of builds in
14# the project history.
15#
16
17# Bail out as soon as an error is encountered.
18set -e
19
20TF_SOURCES=$1
21if [ ! -d "$TF_SOURCES" ]; then
22 echo "ERROR: '$TF_SOURCES' does not exist or is not a directory"
23 echo "Usage: $(basename "$0") <trusted-firmware-directory>"
24 exit 1
25fi
26
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050027containing_dir="$(readlink -f "$(dirname "$0")/")"
28. $containing_dir/common-def.sh
29
Fathi Boudra422bf772019-12-02 11:10:16 +020030# Get mbed TLS library code to build Trusted Firmware with Trusted Board Boot
31# support. The version of mbed TLS to use here must be the same as when
32# building TF in the usual context.
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050033if [ ! -d "$MBED_TLS_DIR" ]; then
34 git clone -q --depth 1 -b "$MBED_TLS_SOURCES_TAG" "$MBED_TLS_URL_REPO" "$MBED_TLS_DIR"
Fathi Boudra422bf772019-12-02 11:10:16 +020035fi
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050036
Fathi Boudra422bf772019-12-02 11:10:16 +020037cd "$TF_SOURCES"
38
39# Clean TF source dir to make sure we don't analyse temporary files.
40make distclean
41
42#
43# Build TF in different configurations to get as much coverage as possible
44#
45
Fathi Boudra422bf772019-12-02 11:10:16 +020046#
47# FVP platform
48# We'll use the following flags for all FVP builds.
49#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050050fvp_common_flags="$(common_flags) PLAT=fvp"
Fathi Boudra422bf772019-12-02 11:10:16 +020051
52# Try all possible SPDs.
53clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd
54clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd TSP_INIT_ASYNC=1 \
55 TSP_NS_INTR_ASYNC_PREEMPT=1
56clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed
57clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tlkd
Florian Lugou70a76c02022-03-25 09:51:42 +010058clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=pncd SPD_PNCD_NS_IRQ=126 SPD_PNCD_S_IRQ=15
Fathi Boudra422bf772019-12-02 11:10:16 +020059
Zelalemc9531f82020-08-04 15:37:08 -050060# Dualroot chain of trust.
61clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tspd COT=dualroot
62
laurenw-armf48e9d22022-04-22 11:30:13 -050063# FEAT_RME with CCA chain of trust.
Sandrine Bailleuxe30bd0c2022-08-31 14:49:17 +020064#
65# Note that we override PLAT_RSS_NOT_SUPPORTED build flag (which defaults to 1
66# on the Base AEM FVP) just to analyse the RSS communication driver code through
67# Coverity. In reality, RSS is not supported on FVP right now (or on any other
68# upstream platform, for that matter) so the resulting firmware would not be
69# functional.
70clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tspd USE_ROMLIB=1 \
71 ENABLE_RME=1 MEASURED_BOOT=1 PLAT_RSS_NOT_SUPPORTED=0
laurenw-armf48e9d22022-04-22 11:30:13 -050072
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050073clean_build $fvp_common_flags SPD=trusty
74clean_build $fvp_common_flags SPD=trusty TRUSTY_SPD_WITH_GENERIC_SERVICES=1
Fathi Boudra422bf772019-12-02 11:10:16 +020075
76# SDEI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050077clean_build $fvp_common_flags SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Fathi Boudra422bf772019-12-02 11:10:16 +020078
Zelalemc9531f82020-08-04 15:37:08 -050079# SDEI with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050080clean_build $fvp_common_flags SDEI_IN_FCONF=1 SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Zelalemc9531f82020-08-04 15:37:08 -050081
Zelalem4f3633e2021-06-18 11:53:47 -050082# PCI Service
83clean_build $fvp_common_flags SMC_PCI_SUPPORT=1
84
Zelalemc9531f82020-08-04 15:37:08 -050085# Secure interrupt descriptors with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050086clean_build $fvp_common_flags SEC_INT_DESC_IN_FCONF=1
Zelalemc9531f82020-08-04 15:37:08 -050087
Fathi Boudra422bf772019-12-02 11:10:16 +020088# Without coherent memory
89clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd USE_COHERENT_MEM=0
90
91# Using PSCI extended State ID format rather than the original format
92clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd PSCI_EXTENDED_STATE_ID=1 \
93 ARM_RECOM_STATE_ID_ENC=1
94
95# Alternative boot flows (This changes some of the platform initialisation code)
96clean_build $fvp_common_flags EL3_PAYLOAD=0x80000000
97clean_build $fvp_common_flags PRELOADED_BL33_BASE=0x80000000
98
99# Using the SP804 timer instead of the Generic Timer
100clean_build $fvp_common_flags FVP_USE_SP804_TIMER=1
101
102# Using the CCN driver and multi cluster topology
103clean_build $fvp_common_flags FVP_CLUSTER_COUNT=4
104
105# PMF
106clean_build $fvp_common_flags ENABLE_PMF=1
107
108# stack protector
109clean_build $fvp_common_flags ENABLE_STACK_PROTECTOR=strong
110
111# AArch32 build
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500112clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200113 ARCH=aarch32 AARCH32_SP=sp_min \
114 RESET_TO_SP_MIN=1 PRELOADED_BL33_BASE=0x80000000
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500115clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200116 ARCH=aarch32 AARCH32_SP=sp_min
117
118# Xlat tables lib version 1 (AArch64 and AArch32)
119clean_build $fvp_common_flags ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500120clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200121 ARCH=aarch32 AARCH32_SP=sp_min ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
122
Zelalemc9531f82020-08-04 15:37:08 -0500123# SPM support based on Management Mode Interface Specification
Manish Pandeyaa9a03b2021-11-17 10:03:17 +0000124clean_build $fvp_common_flags SPM_MM=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0
Fathi Boudra422bf772019-12-02 11:10:16 +0200125
Zelalemc9531f82020-08-04 15:37:08 -0500126# SPM support with TOS(optee) as SPM sitting at S-EL1
127clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0
128
Shruti Gupta8cc89b92022-08-09 12:23:46 +0100129# SPM support with SPM at EL3 and TSP at S-EL1
130clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 CTX_INCLUDE_EL2_REGS=0 EL3_EXCEPTION_HANDLING=0 \
131 SPD=spmd SPMD_SPM_AT_SEL2=0 SPMC_AT_EL3=1 \
132 ARM_SPMC_MANIFEST_DTS=plat/arm/board/fvp/fdts/fvp_tsp_sp_manifest.dts
133
Zelalemc9531f82020-08-04 15:37:08 -0500134# SPM support with Secure hafnium as SPM sitting at S-EL2
135# SP_LAYOUT_FILE is used only during FIP creation but build won't progress
136# if we have NULL value to it, so passing a dummy string.
137clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=1 ARM_ARCH_MINOR=4 \
Max Shvetsov44d2a702021-02-18 16:41:45 +0000138 CTX_INCLUDE_EL2_REGS=1 SP_LAYOUT_FILE=dummy
Fathi Boudra422bf772019-12-02 11:10:16 +0200139
Marc Bonnici502fdaa2022-01-10 12:38:23 +0000140# SPM support with SPM sitting at EL3
141clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0 SPMC_AT_EL3=1
142
Fathi Boudra422bf772019-12-02 11:10:16 +0200143#BL2 at EL3 support
144clean_build $fvp_common_flags BL2_AT_EL3=1
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500145clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200146 ARCH=aarch32 AARCH32_SP=sp_min BL2_AT_EL3=1
147
Zelalemc9531f82020-08-04 15:37:08 -0500148# RAS Extension Support
149clean_build $fvp_common_flags EL3_EXCEPTION_HANDLING=1 \
Manish Pandey9ef33c52022-10-25 16:41:49 +0100150 FAULT_INJECTION_SUPPORT=1 HANDLE_EA_EL3_FIRST_NS=1 RAS_EXTENSION=1 \
Zelalemc9531f82020-08-04 15:37:08 -0500151 SDEI_SUPPORT=1
152
153# Hardware Assisted Coherency(DynamIQ)
154clean_build $fvp_common_flags FVP_CLUSTER_COUNT=1 FVP_MAX_CPUS_PER_CLUSTER=8 \
155 HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0
156
157# Pointer Authentication Support
158clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 \
159 ARM_ARCH_MINOR=5 EL3_EXCEPTION_HANDLING=1 BRANCH_PROTECTION=1 SDEI_SUPPORT=1 SPD=tspd TSP_NS_INTR_ASYNC_PREEMPT=1
160
161# Undefined Behaviour Sanitizer
162# Building with UBSAN SANITIZE_UB=on increases the executable size.
163# Hence it is only properly supported in bl31 with RESET_TO_BL31 enabled
164make $fvp_common_flags clean
165make $fvp_common_flags SANITIZE_UB=on RESET_TO_BL31=1 bl31
166
167# debugfs feature
168clean_build $fvp_common_flags DEBUG=1 USE_DEBUGFS=1
169
170# MPAM feature
171clean_build $fvp_common_flags ENABLE_MPAM_FOR_LOWER_ELS=1
172
173# Using GICv3.1 driver with extended PPI and SPI range
174clean_build $fvp_common_flags GIC_EXT_INTID=1
175
176# Using GICv4 features with extended PPI and SPI range
177clean_build $fvp_common_flags GIC_ENABLE_V4_EXTN=1 GIC_EXT_INTID=1
178
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100179# Measured Boot
laurenw-arm8531e702022-06-09 15:32:37 -0500180clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} MBOOT_EL_HASH_ALG=sha256 MEASURED_BOOT=1 USE_ROMLIB=1
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100181
Manish V Badarkhef43e3f52022-06-21 20:37:25 +0100182# DRTM
183clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} TPM_HASH_ALG=sha256 DRTM_SUPPORT=1 USE_ROMLIB=1
184
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100185# CoT descriptors in device tree
Manish V Badarkhe81102d12020-10-05 08:02:30 +0100186clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} COT_DESC_IN_DTB=1 USE_ROMLIB=1
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100187
Manish V Badarkhe107c8e32021-08-02 19:49:32 +0100188# PSA FWU support
189clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_GPT_SUPPORT=1 PSA_FWU_SUPPORT=1 USE_ROMLIB=1
190
johpow01153c8b22021-11-03 14:38:36 -0500191# SME and HCX features
192clean_build $fvp_common_flags ENABLE_SME_FOR_NS=1 ENABLE_FEAT_HCX=1
193
Jayanth Dodderi Chidanand84da1962022-04-11 11:38:44 +0100194# Architectural Feature Detection mechanism
195clean_build $fvp_common_flags FEATURE_DETECTION=1
196
Fathi Boudra422bf772019-12-02 11:10:16 +0200197#
198# Juno platform
199# We'll use the following flags for all Juno builds.
200#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500201juno_common_flags="$(common_flags) PLAT=juno"
Fathi Boudra422bf772019-12-02 11:10:16 +0200202clean_build $juno_common_flags SPD=tspd ${ARM_TBB_OPTIONS}
203clean_build $juno_common_flags EL3_PAYLOAD=0x80000000
Madhukar Pappireddydcb31f62021-05-06 11:36:36 -0500204clean_build $juno_common_flags ENABLE_STACK_PROTECTOR=strong ARM_ETHOSN_NPU_DRIVER=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200205clean_build $juno_common_flags CSS_USE_SCMI_SDS_DRIVER=0
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500206
Leonardo Sandoval5163b562020-11-20 17:17:59 -0600207clean_build $juno_common_flags SPD=tspd ${ARM_TBB_OPTIONS} ARM_CRYPTOCELL_INTEG=1 CCSBROM_LIB_PATH=${CRYPTOCELL_LIB_PATH} KEY_SIZE=2048
Fathi Boudra422bf772019-12-02 11:10:16 +0200208
Jayanth Dodderi Chidanand055394a2022-10-19 09:20:20 +0100209# TRNG Service
210clean_build $juno_common_flags TRNG_SUPPORT=1
211
Fathi Boudra422bf772019-12-02 11:10:16 +0200212#
Fathi Boudra422bf772019-12-02 11:10:16 +0200213# System Guidance for Infrastructure platform RD-E1Edge
214#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500215make $(common_flags) PLAT=rde1edge ${ARM_TBB_OPTIONS} CSS_SGI_CHIP_COUNT=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500216
217#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530218# Reference Design platform RD-V1
Zelalemc9531f82020-08-04 15:37:08 -0500219#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530220make $(common_flags) PLAT=rdv1 ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500221
222#
Aditya Angadi61c54762021-01-04 09:30:52 +0530223# Reference Design platform RD-V1-MC
Zelalemc9531f82020-08-04 15:37:08 -0500224#
Aditya Angadi61c54762021-01-04 09:30:52 +0530225make $(common_flags) PLAT=rdv1mc ${ARM_TBB_OPTIONS} CSS_SGI_CHIP_COUNT=4 all
Zelalemc9531f82020-08-04 15:37:08 -0500226
227#
Vijayenthiran Subramaniama66de332020-11-23 14:20:14 +0530228# Reference Design Platform RD-N2
229#
230make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} all
231
232#
Zelalemc9531f82020-08-04 15:37:08 -0500233# Neoverse N1 SDP platform
234#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500235make $(common_flags) PLAT=n1sdp ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500236
237#
238# FVP VE platform
239#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500240make $(common_flags) PLAT=fvp_ve AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500241 CROSS_COMPILE=arm-none-eabi- ARM_ARCH_MAJOR=7 \
242 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
243 FVP_HW_CONFIG_DTS=fdts/fvp-ve-Cortex-A5x1.dts all
244
245#
246# A5 DesignStart Platform
247#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500248make $(common_flags) PLAT=a5ds AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500249 ARM_ARCH_MAJOR=7 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
250 CROSS_COMPILE=arm-none-eabi- FVP_HW_CONFIG_DTS=fdts/a5ds.dts
251
252#
253# Corstone700 Platform
254#
255
256corstone700_common_flags="CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500257 $(common_flags) \
Zelalemc9531f82020-08-04 15:37:08 -0500258 PLAT=corstone700 \
259 ARCH=aarch32 \
260 RESET_TO_SP_MIN=1 \
261 AARCH32_SP=sp_min \
262 ARM_LINUX_KERNEL_AS_BL33=0 \
263 ARM_PRELOADED_DTB_BASE=0x80400000 \
264 ENABLE_PIE=1 \
Zelalemc9531f82020-08-04 15:37:08 -0500265 ENABLE_STACK_PROTECTOR=all \
266 all"
267
268echo "Info: Building Corstone700 FVP ..."
269
270make TARGET_PLATFORM=fvp ${corstone700_common_flags}
271
272echo "Info: Building Corstone700 FPGA ..."
273
274make TARGET_PLATFORM=fpga ${corstone700_common_flags}
275
276#
277# Arm internal FPGA port
278#
Andre Przywara13361b62022-04-26 11:16:55 +0100279make PLAT=arm_fpga $(common_flags release) \
280 FPGA_PRELOADED_DTB_BASE=0x88000000 PRELOADED_BL33_BASE=0x82080000 all
Zelalemc9531f82020-08-04 15:37:08 -0500281
282#
Usama Arifcba711d2021-08-04 15:53:42 +0100283# Total Compute platforms
Zelalemc9531f82020-08-04 15:37:08 -0500284#
Usama Arifcba711d2021-08-04 15:53:42 +0100285make $(common_flags) PLAT=tc TARGET_PLATFORM=0 ${ARM_TBB_OPTIONS} all
286make $(common_flags) PLAT=tc TARGET_PLATFORM=1 ${ARM_TBB_OPTIONS} all
Tamas Banaf5a6632022-09-21 16:02:39 +0200287make $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} MEASURED_BOOT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200288
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530289#
290# Morello platform
291#
Chandni Cherukuricbd45962021-12-12 13:37:33 +0530292clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=fvp ${ARM_TBB_OPTIONS}
293clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=soc ${ARM_TBB_OPTIONS}
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530294
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100295#
Vishnu Banavath2cb72b32022-01-20 14:27:55 +0000296# corstone1000 Platform
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100297#
298
299make $(common_flags) \
Vishnu Banavath2cb72b32022-01-20 14:27:55 +0000300 PLAT=corstone1000 \
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100301 SPD=spmd \
302 TARGET_PLATFORM=fpga \
303 ENABLE_STACK_PROTECTOR=strong \
304 ENABLE_PIE=1 \
305 BL2_AT_EL3=1 \
306 SPMD_SPM_AT_SEL2=0 \
307 ${ARM_TBB_OPTIONS} \
308 CREATE_KEYS=1 \
309 COT=tbbr \
310 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
311 bl2 \
312 bl31
313
johpow01aac58582021-10-05 16:51:34 -0500314#
315# FVP-R platform
316#
317clean_build $(common_flags) PLAT=fvp_r ${ARM_TBB_OPTIONS} ENABLE_STACK_PROTECTOR=all
318
Fathi Boudra422bf772019-12-02 11:10:16 +0200319# Partners' platforms.
320# Enable as many features as possible.
321# We don't need to clean between each build here because we only do one build
322# per platform so we don't hit the build flags dependency problem.
Fathi Boudra422bf772019-12-02 11:10:16 +0200323
Manish Pandey9c0ee742021-07-08 09:55:59 +0100324# Platforms from Mediatek
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500325make PLAT=mt8173 $(common_flags) all
326make PLAT=mt8183 $(common_flags) all
Rex-BC Chen946cace2021-11-17 10:15:42 +0800327make PLAT=mt8186 $(common_flags) COREBOOT=1 all
Bo-Chen Chen4d63afd2022-08-30 16:34:57 +0800328make PLAT=mt8188 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500329make PLAT=mt8192 $(common_flags) COREBOOT=1 all
Manish Pandey9c0ee742021-07-08 09:55:59 +0100330make PLAT=mt8195 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500331
332# Platforms from Qualcomm
333make PLAT=sc7180 $(common_flags) COREBOOT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200334
Zelalemc9531f82020-08-04 15:37:08 -0500335make PLAT=rk3288 CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500336 $(common_flags) ARCH=aarch32 AARCH32_SP=sp_min all
Madhukar Pappireddyd491ad02020-12-03 10:37:05 -0600337make PLAT=rk3368 $(common_flags) COREBOOT=1 \
338 ENABLE_STACK_PROTECTOR=strong all
339make PLAT=rk3399 $(common_flags) COREBOOT=1 PLAT_RK_DP_HDCP=1 \
340 ENABLE_STACK_PROTECTOR=strong all
341make PLAT=rk3328 $(common_flags) COREBOOT=1 PLAT_RK_SECURE_DDR_MINILOADER=1 \
342 ENABLE_STACK_PROTECTOR=strong all
343make PLAT=px30 $(common_flags) PLAT_RK_SECURE_DDR_MINILOADER=1 \
344 ENABLE_STACK_PROTECTOR=strong all
Fathi Boudra422bf772019-12-02 11:10:16 +0200345
346# Although we do several consecutive builds for the Tegra platform below, we
347# don't need to clean between each one because the Tegra makefiles specify
348# a different build directory per SoC.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500349make PLAT=tegra TARGET_SOC=t210 $(common_flags) all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500350make PLAT=tegra TARGET_SOC=t186 $(common_flags) all
351make PLAT=tegra TARGET_SOC=t194 $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200352
353# For the Xilinx platform, artificially increase the extents of BL31 memory
354# (using the platform-specific build options ZYNQMP_ATF_MEM_{BASE,SIZE}).
355# If we keep the default values, BL31 doesn't fit when it is built with all
356# these build flags.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500357make PLAT=zynqmp $(common_flags) \
Fathi Boudra422bf772019-12-02 11:10:16 +0200358 RESET_TO_BL31=1 SPD=tspd \
Zelalem4f3633e2021-06-18 11:53:47 -0500359 SDEI_SUPPORT=1 \
Fathi Boudra422bf772019-12-02 11:10:16 +0200360 ZYNQMP_ATF_MEM_BASE=0xFFFC0000 ZYNQMP_ATF_MEM_SIZE=0x00040000 \
361 all
362
Zelalemc9531f82020-08-04 15:37:08 -0500363# Build both for silicon (default) and virtual QEMU platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500364clean_build PLAT=versal $(common_flags)
365clean_build PLAT=versal $(common_flags) VERSAL_PLATFORM=versal_virt
Zelalemc9531f82020-08-04 15:37:08 -0500366
Michal Simek0f135242022-09-20 15:24:56 +0200367# Build Xilinx Versal NET platform
368clean_build PLAT=versal_net $(common_flags)
369
Jayanth Dodderi Chidanand0a2dd1e2022-10-27 11:17:37 +0100370# Build Xilinx Versal NET without Platform Management support
371clean_build PLAT=versal_net $(common_flags) TFA_NO_PM=1
372
Zelalemc9531f82020-08-04 15:37:08 -0500373# Platforms from Allwinner
Andre Przywara3a78c102022-04-26 11:08:54 +0100374clean_build PLAT=sun50i_a64 $(common_flags release) all
375clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_NATIVE=0 all
376clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_SCPI=0 all
377clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_AMEND_DTB=1 all
Andre Przywaracf78a512021-09-03 14:59:38 +0100378clean_build PLAT=sun50i_h6 $(common_flags) all
379clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_NATIVE=0 all
380clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_SCPI=0 all
381clean_build PLAT=sun50i_h616 $(common_flags) all
382clean_build PLAT=sun50i_r329 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500383
384# Platforms from i.MX
385make AARCH32_SP=optee ARCH=aarch32 ARM_ARCH_MAJOR=7 ARM_CORTEX_A7=yes \
386 CROSS_COMPILE=arm-none-eabi- PLAT=warp7 ${TBB_OPTIONS} \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500387 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500388make AARCH32_SP=optee ARCH=aarch32 CROSS_COMPILE=arm-none-eabi- PLAT=picopi \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500389 $(common_flags) all
Ying-Chun Liu (PaulLiu)f6528982021-11-17 17:20:00 +0800390make PLAT=imx8mm $(common_flags) NEED_BL2=yes MEASURED_BOOT=1 \
laurenw-arm8531e702022-06-09 15:32:37 -0500391 MBOOT_EL_HASH_ALG=sha256 ${TBB_OPTIONS} all
Madhukar Pappireddyc3ec06b2022-05-18 11:15:16 -0500392make PLAT=imx8mn $(common_flags) SDEI_SUPPORT=1 all
Ying-Chun Liu (PaulLiu)413e6102021-09-14 00:22:08 +0800393make PLAT=imx8mp $(common_flags) NEED_BL2=yes ${TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500394
Jacky Baib6cecc82021-06-07 09:49:46 +0800395# Due to the limited OCRAM space that can be used for TF-A, build test
396# will report failure caused by too small RAM size, so comment out the
397# build test for imx8mq in CI. It can also resolve the following ticket:
Zelalemc9531f82020-08-04 15:37:08 -0500398# https://developer.trustedfirmware.org/T626
Jacky Baib6cecc82021-06-07 09:49:46 +0800399#make PLAT=imx8mq $(common_flags release) all
Zelalemc9531f82020-08-04 15:37:08 -0500400
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500401make PLAT=imx8qm $(common_flags) all
402make PLAT=imx8qx $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500403
Olivier Deprezbac70192021-04-02 08:55:36 +0200404# Platforms for NXP Layerscape
Jiafei Pane48e56c2021-09-30 10:32:54 +0800405nxp_sb_flags="TRUSTED_BOARD_BOOT=1 CST_DIR=$(pwd) SPD=opteed"
406nxp_sb_fuse_flags="${nxp_sb_flags} FUSE_PROG=1"
407
408# Platform lx2
Olivier Deprezbac70192021-04-02 08:55:36 +0200409make PLAT=lx2160aqds $(common_flags) all
410make PLAT=lx2160ardb $(common_flags) all
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500411
412#CSF Based CoT:
Jiafei Pane48e56c2021-09-30 10:32:54 +0800413clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
414 $nxp_sb_fuse_flags DDR_PHY_BIN_PATH=$(pwd)
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500415
416#X509 Based CoT
Jiafei Pane48e56c2021-09-30 10:32:54 +0800417clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
418 $nxp_sb_flags GENERATE_COT=1 \
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500419 MBEDTLS_DIR=$(pwd)/mbedtls
420
421#BOOT_MODE=emmc and Stack protector
Jiafei Pane48e56c2021-09-30 10:32:54 +0800422clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=emmc \
423 $nxp_sb_fuse_flags ENABLE_STACK_PROTECTOR=strong
424
425# Platform ls1028ardb
426clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor
427clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc
428clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd
429
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800430# ls1028a Secure Boot
Jiafei Pane48e56c2021-09-30 10:32:54 +0800431clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor $nxp_sb_fuse_flags
432clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
433clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
Olivier Deprezbac70192021-04-02 08:55:36 +0200434
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800435# Platform ls1043ardb
436clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor
437clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand
438clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd
439
440# ls1043ardb Secure Boot
441clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
442clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
443clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
444
Jiafei Panbd0c22a2022-01-29 00:04:44 +0800445# ls1046ardb Secure Boot
446clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
447clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
448clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
449
450# ls1046afrwy Secure Boot
451clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
452clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
453
454# ls1046aqds Secure Boot
455clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
456clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
457clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
458clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
459
Jiafei Pan332cd792022-02-24 16:44:48 +0800460# ls1088ardb Secure Boot
461clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
462clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
463
464# ls1088aqds Secure Boot
465clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
466clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
467clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
468
Zelalemc9531f82020-08-04 15:37:08 -0500469# Platforms from Intel
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500470make PLAT=stratix10 $(common_flags) all
471make PLAT=agilex $(common_flags) all
Sieu Mun Tang03b57362022-03-05 01:54:59 +0800472make PLAT=n5x $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500473
474# Platforms from Broadcom
Madhukar Pappireddy97ad2582021-11-15 10:29:23 -0600475clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t \
476 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 DRIVER_I2C_ENABLE=1
477clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t-ns3 \
478 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 USE_USB=yes
Zelalemc9531f82020-08-04 15:37:08 -0500479
480# Platforms from Marvell
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500481make PLAT=a3700 $(common_flags) SCP_BL2=/dev/null CM3_SYSTEM_RESET=1 \
Manish Pandey9ef33c52022-10-25 16:41:49 +0100482 A3720_DB_PM_WAKEUP_SRC=1 HANDLE_EA_EL3_FIRST_NS=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500483
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600484# Source files from mv-ddr-marvell repository are necessary
485# to build below four platforms
Manish Pandey7c1e7452021-11-05 12:54:15 +0000486wget https://downloads.trustedfirmware.org/tf-a/mv-ddr-marvell/mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
487tar -xzf mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600488mv mv-ddr-marvell drivers/marvell/mv_ddr
Zelalemc9531f82020-08-04 15:37:08 -0500489
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600490# These platforms from Marvell have dependency on GCC-6.2.1 toolchain
Pali Rohár8f890402021-07-19 13:48:05 +0200491make PLAT=a80x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200492 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200493make PLAT=a80x0_mcbin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200494 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200495make PLAT=a70x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200496 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200497make PLAT=a70x0_amc DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200498 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Robert Markodf3319e2021-10-20 11:01:12 +0200499make PLAT=a70x0_mochabin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
500 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200501make PLAT=a80x0_puzzle DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200502 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200503make PLAT=t9130 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200504 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500505make PLAT=t9130_cex7_eval DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
506 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500507
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600508# Removing the source files
509rm -rf drivers/marvell/mv_ddr 2> /dev/null
Zelalemc9531f82020-08-04 15:37:08 -0500510
511# Platforms from Meson
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500512make PLAT=gxbb $(common_flags) all
513make PLAT=gxl $(common_flags) all
514make PLAT=g12a $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500515
516# Platforms from Renesas
517# Renesas R-Car D3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500518clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500519 BL33=Makefile LIFEC_DBSC_PROTECT_ENABLE=0 LSI=D3 \
520 MBEDTLS_DIR=$(pwd)/mbedtls PMIC_ROHM_BD9571=0 \
521 RCAR_AVS_SETTING_ENABLE=0 SPD=none RCAR_LOSSY_ENABLE=0 \
522 RCAR_SA0_SIZE=0 RCAR_SYSTEM_SUSPEND=0 TRUSTED_BOARD_BOOT=1
523
524# Renesas R-Car H3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500525clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500526 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3 \
527 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
528 RCAR_DRAM_SPLIT=1 RCAR_GEN3_ULCB=1 SPD=opteed \
529 TRUSTED_BOARD_BOOT=1
530
531# Renesas R-Car H3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500532clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500533 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3N \
534 SPD=opteed TRUSTED_BOARD_BOOT=1
535
536# Renesas R-Car M3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500537clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500538 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3 \
539 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
540 RCAR_DRAM_SPLIT=2 RCAR_GEN3_ULCB=1 SPD=opteed \
541 TRUSTED_BOARD_BOOT=1
542
543# Renesas R-Car M3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500544clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500545 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3N \
546 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
547 RCAR_GEN3_ULCB=1 SPD=opteed TRUSTED_BOARD_BOOT=1
548
549# Renesas R-Car E3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500550clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500551 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=E3 \
552 RCAR_AVS_SETTING_ENABLE=0 RCAR_DRAM_DDR3L_MEMCONF=0 \
553 RCAR_SA0_SIZE=0 SPD=opteed TRUSTED_BOARD_BOOT=1
554
555# Renesas R-Car V3M Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500556clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500557 MBEDTLS_DIR=$(pwd)/mbedtls BL33=Makefile LSI=V3M MACHINE=eagle \
558 PMIC_ROHM_BD9571=0 RCAR_DRAM_SPLIT=0 RCAR_SYSTEM_SUSPEND=0 \
559 AVS_SETTING_ENABLE=0 SPD=none TRUSTED_BOARD_BOOT=1
560
Zelalemf4299672021-01-29 12:52:59 -0600561# Renesas HiHope RZ/G2M development kit
562clean_build PLAT=rzg $(common_flags) \
563 MBEDTLS_DIR=$(pwd)/mbedtls LSI=G2M \
564 RCAR_DRAM_SPLIT=2 RCAR_LOSSY_ENABLE=1 SPD=none
565
Zelalemc9531f82020-08-04 15:37:08 -0500566# Platforms from ST
Yann Gautiera69cf792021-09-01 11:19:01 +0200567# STM32MP1 SDMMC boot
568make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
569 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_SDMMC=1 \
570 BUILD_PLAT=build/stm32mp1-sdmmc/debug \
571 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
572
573# STM32MP1 eMMC boot
Zelalemc9531f82020-08-04 15:37:08 -0500574make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500575 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_EMMC=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200576 BUILD_PLAT=build/stm32mp1-emmc/debug \
577 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
578
579# STM32MP1 Raw NAND boot
580make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
581 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_RAW_NAND=1 \
582 BUILD_PLAT=build/stm32mp1-nand/debug \
583 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
584
585# STM32MP1 SPI NAND boot
586make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
587 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_SPI_NAND=1 \
588 BUILD_PLAT=build/stm32mp1-snand/debug \
589 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
590
591# STM32MP1 SPI NOR boot
592make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
593 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_SPI_NOR=1 \
594 BUILD_PLAT=build/stm32mp1-snor/debug \
595 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
596
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100597# STM32MP1 UART boot
598make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
599 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_UART_PROGRAMMER=1 \
600 BUILD_PLAT=build/stm32mp1-uart/debug \
601 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
602
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200603# STM32MP1 USB boot
604make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
605 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_USB_PROGRAMMER=1 \
606 BUILD_PLAT=build/stm32mp1-usb/debug \
607 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
608
Lionel Debieve8f464c02022-10-13 09:25:45 +0200609# STM32MP1 TBBR
610make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
611 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_SDMMC=1 \
612 BUILD_PLAT=build/stm32mp1-sdmmc/debug \
613 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
614 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
615
Yann Gautier773c5502022-03-10 17:24:47 +0100616# STM32MP13 SDMMC boot
617make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
618 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_SDMMC=1 \
619 BUILD_PLAT=build/stm32mp1-mp13-sdmmc/debug STM32MP13=1 \
620 ARCH=aarch32 AARCH32_SP=optee ENABLE_STACK_PROTECTOR=strong bl2
621
Lionel Debieve8f464c02022-10-13 09:25:45 +0200622# STM32MP13 TBBR
623make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
624 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_SDMMC=1 \
625 BUILD_PLAT=build/stm32mp1-mp13-sdmmc/debug STM32MP13=1 \
626 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
627 ARCH=aarch32 AARCH32_SP=optee ENABLE_STACK_PROTECTOR=strong bl2
628
Zelalemc9531f82020-08-04 15:37:08 -0500629# Platforms from TI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500630make PLAT=k3 $(common_flags) all
Hari Nagalladadd89f2022-08-30 12:10:00 -0500631make PLAT=k3 TARGET_BOARD=j784s4 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500632
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500633clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS}
Zelalemc9531f82020-08-04 15:37:08 -0500634# Use GICV3 driver
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500635clean_build PLAT=qemu $(common_flags) QEMU_USE_GIC_DRIVER=QEMU_GICV3 \
Zelalemc9531f82020-08-04 15:37:08 -0500636 ENABLE_STACK_PROTECTOR=strong
637# Use encrypted FIP feature.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500638clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500639 BL32_RAM_LOCATION=tdram DECRYPTION_SUPPORT=aes_gcm ENCRYPT_BL31=1 \
640 ENCRYPT_BL32=1 FW_ENC_STATUS=0 SPD=opteed
Jens Wiklander1a9c2be2021-11-26 09:56:55 +0100641# QEMU with SPMD support
642clean_build PLAT=qemu $(common_flags) BL32=Makefile \
643 BL32_RAM_LOCATION=tdram ARM_BL31_IN_DRAM=1 \
644 SPD=spmd CTX_INCLUDE_EL2_REGS=0 SPMD_SPM_AT_SEL2=0 SPMC_OPTEE=1
Ruchika Gupta86e7f682022-04-12 10:25:46 +0530645# Measured Boot
laurenw-arm8531e702022-06-09 15:32:37 -0500646clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} MBOOT_EL_HASH_ALG=sha256 MEASURED_BOOT=1
Zelalemc9531f82020-08-04 15:37:08 -0500647
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500648clean_build PLAT=qemu_sbsa $(common_flags)
Fathi Boudra422bf772019-12-02 11:10:16 +0200649
Zelalemd86e8762020-08-21 18:24:28 -0500650# QEMU with SPM support
651clean_build PLAT=qemu_sbsa $(common_flags) BL32=Makefile SPM_MM=1 \
Manish Pandeyaa9a03b2021-11-17 10:03:17 +0000652 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0
Zelalemd86e8762020-08-21 18:24:28 -0500653
Fathi Boudra422bf772019-12-02 11:10:16 +0200654# For hikey enable PMF to include all files in the platform port
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500655make PLAT=hikey $(common_flags) ${TBB_OPTIONS} ENABLE_PMF=1 all
656make PLAT=hikey960 $(common_flags) ${TBB_OPTIONS} all
Lukas Haneld0752392022-10-13 11:13:19 +0200657make PLAT=hikey960 $(common_flags) ${TBB_OPTIONS} SPD=spmd SPMC_AT_EL3=1 \
658 SPMD_SPM_AT_SEL2=0 BL32=optee PLAT_SP_MANIFEST_DTS=foo NEED_FDT=no all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500659make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200660
Zelalemc9531f82020-08-04 15:37:08 -0500661# Platforms from Socionext
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500662clean_build PLAT=uniphier $(common_flags) ${TBB_OPTIONS} SPD=tspd
663clean_build PLAT=uniphier $(common_flags) FIP_GZIP=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200664
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500665clean_build PLAT=synquacer $(common_flags) SPM_MM=1 \
Jassi Brar86080922022-06-27 14:16:34 -0500666 RESET_TO_BL31=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0 \
667 PRELOADED_BL33_BASE=0x0
Zelalemc9531f82020-08-04 15:37:08 -0500668
669# Support for SCP Message Interface protocol with platform specific drivers
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500670clean_build PLAT=synquacer $(common_flags) \
Jassi Brar86080922022-06-27 14:16:34 -0500671 RESET_TO_BL31=1 PRELOADED_BL33_BASE=0x0 SQ_USE_SCMI_DRIVER=1
Zelalemc9531f82020-08-04 15:37:08 -0500672
Jassi Brarb8c7ca02022-06-27 14:22:10 -0500673# Support for BL2 and TBBR
674clean_build PLAT=synquacer $(common_flags) \
675 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
676 SQ_USE_SCMI_DRIVER=1 SPD=opteed all
677
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500678make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200679
Zelalemc9531f82020-08-04 15:37:08 -0500680# Raspberry Pi Platforms
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500681make PLAT=rpi3 $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500682 ENABLE_STACK_PROTECTOR=strong PRELOADED_BL33_BASE=0xDEADBEEF all
Andre Przywarae917ec82021-09-03 15:01:30 +0100683clean_build PLAT=rpi4 $(common_flags) SMC_PCI_SUPPORT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200684
Zelalemc9531f82020-08-04 15:37:08 -0500685# A113D (AXG) platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500686clean_build PLAT=axg $(common_flags) SPD=opteed
687clean_build PLAT=axg $(common_flags) AML_USE_ATOS=1
Zelalemc9531f82020-08-04 15:37:08 -0500688
Stephan Gerhold141a7662021-12-07 20:42:14 +0100689# QTI MSM8916 platform
690clean_build PLAT=msm8916 $(common_flags)
691
Fathi Boudra422bf772019-12-02 11:10:16 +0200692cd ..