blob: 3156048ec9b9f202be83eec7823350423d36ddb3 [file] [log] [blame]
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -05001#!/usr/bin/env bash
Fathi Boudra422bf772019-12-02 11:10:16 +02002#
Yann Gautier773c5502022-03-10 17:24:47 +01003# Copyright (c) 2019-2022, Arm Limited. All rights reserved.
Fathi Boudra422bf772019-12-02 11:10:16 +02004#
5# SPDX-License-Identifier: BSD-3-Clause
6#
7
8#
9# This script builds the TF in different configs.
10# Rather than telling cov-build to build TF using a simple 'make all' command,
11# the goal here is to combine several build flags to analyse more of our source
12# code in a single 'build'. The Coverity Scan service does not have the notion
13# of separate types of build - there is just one linear sequence of builds in
14# the project history.
15#
16
17# Bail out as soon as an error is encountered.
18set -e
19
20TF_SOURCES=$1
21if [ ! -d "$TF_SOURCES" ]; then
22 echo "ERROR: '$TF_SOURCES' does not exist or is not a directory"
23 echo "Usage: $(basename "$0") <trusted-firmware-directory>"
24 exit 1
25fi
26
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050027containing_dir="$(readlink -f "$(dirname "$0")/")"
28. $containing_dir/common-def.sh
29
Fathi Boudra422bf772019-12-02 11:10:16 +020030# Get mbed TLS library code to build Trusted Firmware with Trusted Board Boot
31# support. The version of mbed TLS to use here must be the same as when
32# building TF in the usual context.
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050033if [ ! -d "$MBED_TLS_DIR" ]; then
34 git clone -q --depth 1 -b "$MBED_TLS_SOURCES_TAG" "$MBED_TLS_URL_REPO" "$MBED_TLS_DIR"
Fathi Boudra422bf772019-12-02 11:10:16 +020035fi
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050036
Fathi Boudra422bf772019-12-02 11:10:16 +020037cd "$TF_SOURCES"
38
39# Clean TF source dir to make sure we don't analyse temporary files.
40make distclean
41
42#
43# Build TF in different configurations to get as much coverage as possible
44#
45
Fathi Boudra422bf772019-12-02 11:10:16 +020046#
47# FVP platform
48# We'll use the following flags for all FVP builds.
49#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050050fvp_common_flags="$(common_flags) PLAT=fvp"
Fathi Boudra422bf772019-12-02 11:10:16 +020051
52# Try all possible SPDs.
53clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd
54clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd TSP_INIT_ASYNC=1 \
55 TSP_NS_INTR_ASYNC_PREEMPT=1
56clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed
57clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tlkd
58
Zelalemc9531f82020-08-04 15:37:08 -050059# Dualroot chain of trust.
60clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tspd COT=dualroot
61
laurenw-armf48e9d22022-04-22 11:30:13 -050062# FEAT_RME with CCA chain of trust.
63clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tspd USE_ROMLIB=1 ENABLE_RME=1 MEASURED_BOOT=1
64
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050065clean_build $fvp_common_flags SPD=trusty
66clean_build $fvp_common_flags SPD=trusty TRUSTY_SPD_WITH_GENERIC_SERVICES=1
Fathi Boudra422bf772019-12-02 11:10:16 +020067
68# SDEI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050069clean_build $fvp_common_flags SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Fathi Boudra422bf772019-12-02 11:10:16 +020070
Zelalemc9531f82020-08-04 15:37:08 -050071# SDEI with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050072clean_build $fvp_common_flags SDEI_IN_FCONF=1 SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Zelalemc9531f82020-08-04 15:37:08 -050073
Zelalem4f3633e2021-06-18 11:53:47 -050074# PCI Service
75clean_build $fvp_common_flags SMC_PCI_SUPPORT=1
76
Zelalemc9531f82020-08-04 15:37:08 -050077# Secure interrupt descriptors with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050078clean_build $fvp_common_flags SEC_INT_DESC_IN_FCONF=1
Zelalemc9531f82020-08-04 15:37:08 -050079
Fathi Boudra422bf772019-12-02 11:10:16 +020080# Without coherent memory
81clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd USE_COHERENT_MEM=0
82
83# Using PSCI extended State ID format rather than the original format
84clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd PSCI_EXTENDED_STATE_ID=1 \
85 ARM_RECOM_STATE_ID_ENC=1
86
87# Alternative boot flows (This changes some of the platform initialisation code)
88clean_build $fvp_common_flags EL3_PAYLOAD=0x80000000
89clean_build $fvp_common_flags PRELOADED_BL33_BASE=0x80000000
90
91# Using the SP804 timer instead of the Generic Timer
92clean_build $fvp_common_flags FVP_USE_SP804_TIMER=1
93
94# Using the CCN driver and multi cluster topology
95clean_build $fvp_common_flags FVP_CLUSTER_COUNT=4
96
97# PMF
98clean_build $fvp_common_flags ENABLE_PMF=1
99
100# stack protector
101clean_build $fvp_common_flags ENABLE_STACK_PROTECTOR=strong
102
103# AArch32 build
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500104clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200105 ARCH=aarch32 AARCH32_SP=sp_min \
106 RESET_TO_SP_MIN=1 PRELOADED_BL33_BASE=0x80000000
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500107clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200108 ARCH=aarch32 AARCH32_SP=sp_min
109
110# Xlat tables lib version 1 (AArch64 and AArch32)
111clean_build $fvp_common_flags ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500112clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200113 ARCH=aarch32 AARCH32_SP=sp_min ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
114
Zelalemc9531f82020-08-04 15:37:08 -0500115# SPM support based on Management Mode Interface Specification
Manish Pandeyaa9a03b2021-11-17 10:03:17 +0000116clean_build $fvp_common_flags SPM_MM=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0
Fathi Boudra422bf772019-12-02 11:10:16 +0200117
Zelalemc9531f82020-08-04 15:37:08 -0500118# SPM support with TOS(optee) as SPM sitting at S-EL1
119clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0
120
Shruti Gupta8cc89b92022-08-09 12:23:46 +0100121# SPM support with SPM at EL3 and TSP at S-EL1
122clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 CTX_INCLUDE_EL2_REGS=0 EL3_EXCEPTION_HANDLING=0 \
123 SPD=spmd SPMD_SPM_AT_SEL2=0 SPMC_AT_EL3=1 \
124 ARM_SPMC_MANIFEST_DTS=plat/arm/board/fvp/fdts/fvp_tsp_sp_manifest.dts
125
Zelalemc9531f82020-08-04 15:37:08 -0500126# SPM support with Secure hafnium as SPM sitting at S-EL2
127# SP_LAYOUT_FILE is used only during FIP creation but build won't progress
128# if we have NULL value to it, so passing a dummy string.
129clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=1 ARM_ARCH_MINOR=4 \
Max Shvetsov44d2a702021-02-18 16:41:45 +0000130 CTX_INCLUDE_EL2_REGS=1 SP_LAYOUT_FILE=dummy
Fathi Boudra422bf772019-12-02 11:10:16 +0200131
Marc Bonnici502fdaa2022-01-10 12:38:23 +0000132# SPM support with SPM sitting at EL3
133clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0 SPMC_AT_EL3=1
134
Fathi Boudra422bf772019-12-02 11:10:16 +0200135#BL2 at EL3 support
136clean_build $fvp_common_flags BL2_AT_EL3=1
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500137clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200138 ARCH=aarch32 AARCH32_SP=sp_min BL2_AT_EL3=1
139
Zelalemc9531f82020-08-04 15:37:08 -0500140# RAS Extension Support
141clean_build $fvp_common_flags EL3_EXCEPTION_HANDLING=1 \
142 FAULT_INJECTION_SUPPORT=1 HANDLE_EA_EL3_FIRST=1 RAS_EXTENSION=1 \
143 SDEI_SUPPORT=1
144
145# Hardware Assisted Coherency(DynamIQ)
146clean_build $fvp_common_flags FVP_CLUSTER_COUNT=1 FVP_MAX_CPUS_PER_CLUSTER=8 \
147 HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0
148
149# Pointer Authentication Support
150clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 \
151 ARM_ARCH_MINOR=5 EL3_EXCEPTION_HANDLING=1 BRANCH_PROTECTION=1 SDEI_SUPPORT=1 SPD=tspd TSP_NS_INTR_ASYNC_PREEMPT=1
152
153# Undefined Behaviour Sanitizer
154# Building with UBSAN SANITIZE_UB=on increases the executable size.
155# Hence it is only properly supported in bl31 with RESET_TO_BL31 enabled
156make $fvp_common_flags clean
157make $fvp_common_flags SANITIZE_UB=on RESET_TO_BL31=1 bl31
158
159# debugfs feature
160clean_build $fvp_common_flags DEBUG=1 USE_DEBUGFS=1
161
162# MPAM feature
163clean_build $fvp_common_flags ENABLE_MPAM_FOR_LOWER_ELS=1
164
165# Using GICv3.1 driver with extended PPI and SPI range
166clean_build $fvp_common_flags GIC_EXT_INTID=1
167
168# Using GICv4 features with extended PPI and SPI range
169clean_build $fvp_common_flags GIC_ENABLE_V4_EXTN=1 GIC_EXT_INTID=1
170
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100171# Measured Boot
laurenw-arm8531e702022-06-09 15:32:37 -0500172clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} MBOOT_EL_HASH_ALG=sha256 MEASURED_BOOT=1 USE_ROMLIB=1
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100173
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100174# CoT descriptors in device tree
Manish V Badarkhe81102d12020-10-05 08:02:30 +0100175clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} COT_DESC_IN_DTB=1 USE_ROMLIB=1
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100176
Manish V Badarkhe107c8e32021-08-02 19:49:32 +0100177# PSA FWU support
178clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_GPT_SUPPORT=1 PSA_FWU_SUPPORT=1 USE_ROMLIB=1
179
johpow01153c8b22021-11-03 14:38:36 -0500180# SME and HCX features
181clean_build $fvp_common_flags ENABLE_SME_FOR_NS=1 ENABLE_FEAT_HCX=1
182
Jayanth Dodderi Chidanand84da1962022-04-11 11:38:44 +0100183# Architectural Feature Detection mechanism
184clean_build $fvp_common_flags FEATURE_DETECTION=1
185
Fathi Boudra422bf772019-12-02 11:10:16 +0200186#
187# Juno platform
188# We'll use the following flags for all Juno builds.
189#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500190juno_common_flags="$(common_flags) PLAT=juno"
Fathi Boudra422bf772019-12-02 11:10:16 +0200191clean_build $juno_common_flags SPD=tspd ${ARM_TBB_OPTIONS}
192clean_build $juno_common_flags EL3_PAYLOAD=0x80000000
Madhukar Pappireddydcb31f62021-05-06 11:36:36 -0500193clean_build $juno_common_flags ENABLE_STACK_PROTECTOR=strong ARM_ETHOSN_NPU_DRIVER=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200194clean_build $juno_common_flags CSS_USE_SCMI_SDS_DRIVER=0
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500195
Leonardo Sandoval5163b562020-11-20 17:17:59 -0600196clean_build $juno_common_flags SPD=tspd ${ARM_TBB_OPTIONS} ARM_CRYPTOCELL_INTEG=1 CCSBROM_LIB_PATH=${CRYPTOCELL_LIB_PATH} KEY_SIZE=2048
Fathi Boudra422bf772019-12-02 11:10:16 +0200197
198#
199# System Guidance for Infrastructure platform SGI575
Zelalemc9531f82020-08-04 15:37:08 -0500200# Enable build config with RAS_EXTENSION to cover more files
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500201make $(common_flags) PLAT=sgi575 ${ARM_TBB_OPTIONS} EL3_EXCEPTION_HANDLING=1 FAULT_INJECTION_SUPPORT=1 \
Manish Pandeyaa9a03b2021-11-17 10:03:17 +0000202 HANDLE_EA_EL3_FIRST=1 RAS_EXTENSION=1 SDEI_SUPPORT=1 SPM_MM=1 ENABLE_SVE_FOR_NS=0 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200203
204#
Vijayenthiran Subramaniam2a47a6d2020-07-22 14:16:58 +0530205# System Guidance for Infrastructure platform RD-N1-Edge-Dual
Fathi Boudra422bf772019-12-02 11:10:16 +0200206#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500207make $(common_flags) PLAT=rdn1edge CSS_SGI_CHIP_COUNT=2 ${ARM_TBB_OPTIONS} all
Fathi Boudra422bf772019-12-02 11:10:16 +0200208
209#
210# System Guidance for Infrastructure platform RD-E1Edge
211#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500212make $(common_flags) PLAT=rde1edge ${ARM_TBB_OPTIONS} CSS_SGI_CHIP_COUNT=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500213
214#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530215# Reference Design platform RD-V1
Zelalemc9531f82020-08-04 15:37:08 -0500216#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530217make $(common_flags) PLAT=rdv1 ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500218
219#
Aditya Angadi61c54762021-01-04 09:30:52 +0530220# Reference Design platform RD-V1-MC
Zelalemc9531f82020-08-04 15:37:08 -0500221#
Aditya Angadi61c54762021-01-04 09:30:52 +0530222make $(common_flags) PLAT=rdv1mc ${ARM_TBB_OPTIONS} CSS_SGI_CHIP_COUNT=4 all
Zelalemc9531f82020-08-04 15:37:08 -0500223
224#
Vijayenthiran Subramaniama66de332020-11-23 14:20:14 +0530225# Reference Design Platform RD-N2
226#
227make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} all
228
229#
Zelalemc9531f82020-08-04 15:37:08 -0500230# Neoverse N1 SDP platform
231#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500232make $(common_flags) PLAT=n1sdp ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500233
234#
235# FVP VE platform
236#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500237make $(common_flags) PLAT=fvp_ve AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500238 CROSS_COMPILE=arm-none-eabi- ARM_ARCH_MAJOR=7 \
239 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
240 FVP_HW_CONFIG_DTS=fdts/fvp-ve-Cortex-A5x1.dts all
241
242#
243# A5 DesignStart Platform
244#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500245make $(common_flags) PLAT=a5ds AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500246 ARM_ARCH_MAJOR=7 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
247 CROSS_COMPILE=arm-none-eabi- FVP_HW_CONFIG_DTS=fdts/a5ds.dts
248
249#
250# Corstone700 Platform
251#
252
253corstone700_common_flags="CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500254 $(common_flags) \
Zelalemc9531f82020-08-04 15:37:08 -0500255 PLAT=corstone700 \
256 ARCH=aarch32 \
257 RESET_TO_SP_MIN=1 \
258 AARCH32_SP=sp_min \
259 ARM_LINUX_KERNEL_AS_BL33=0 \
260 ARM_PRELOADED_DTB_BASE=0x80400000 \
261 ENABLE_PIE=1 \
Zelalemc9531f82020-08-04 15:37:08 -0500262 ENABLE_STACK_PROTECTOR=all \
263 all"
264
265echo "Info: Building Corstone700 FVP ..."
266
267make TARGET_PLATFORM=fvp ${corstone700_common_flags}
268
269echo "Info: Building Corstone700 FPGA ..."
270
271make TARGET_PLATFORM=fpga ${corstone700_common_flags}
272
273#
274# Arm internal FPGA port
275#
Andre Przywara13361b62022-04-26 11:16:55 +0100276make PLAT=arm_fpga $(common_flags release) \
277 FPGA_PRELOADED_DTB_BASE=0x88000000 PRELOADED_BL33_BASE=0x82080000 all
Zelalemc9531f82020-08-04 15:37:08 -0500278
279#
Usama Arifcba711d2021-08-04 15:53:42 +0100280# Total Compute platforms
Zelalemc9531f82020-08-04 15:37:08 -0500281#
Usama Arifcba711d2021-08-04 15:53:42 +0100282make $(common_flags) PLAT=tc TARGET_PLATFORM=0 ${ARM_TBB_OPTIONS} all
283make $(common_flags) PLAT=tc TARGET_PLATFORM=1 ${ARM_TBB_OPTIONS} all
Rupinderjit Singh385f17d2022-07-18 20:28:10 +0100284make $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} all
Fathi Boudra422bf772019-12-02 11:10:16 +0200285
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530286#
287# Morello platform
288#
Chandni Cherukuricbd45962021-12-12 13:37:33 +0530289clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=fvp ${ARM_TBB_OPTIONS}
290clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=soc ${ARM_TBB_OPTIONS}
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530291
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100292#
Vishnu Banavath2cb72b32022-01-20 14:27:55 +0000293# corstone1000 Platform
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100294#
295
296make $(common_flags) \
Vishnu Banavath2cb72b32022-01-20 14:27:55 +0000297 PLAT=corstone1000 \
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100298 SPD=spmd \
299 TARGET_PLATFORM=fpga \
300 ENABLE_STACK_PROTECTOR=strong \
301 ENABLE_PIE=1 \
302 BL2_AT_EL3=1 \
303 SPMD_SPM_AT_SEL2=0 \
304 ${ARM_TBB_OPTIONS} \
305 CREATE_KEYS=1 \
306 COT=tbbr \
307 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
308 bl2 \
309 bl31
310
johpow01aac58582021-10-05 16:51:34 -0500311#
312# FVP-R platform
313#
314clean_build $(common_flags) PLAT=fvp_r ${ARM_TBB_OPTIONS} ENABLE_STACK_PROTECTOR=all
315
Fathi Boudra422bf772019-12-02 11:10:16 +0200316# Partners' platforms.
317# Enable as many features as possible.
318# We don't need to clean between each build here because we only do one build
319# per platform so we don't hit the build flags dependency problem.
Fathi Boudra422bf772019-12-02 11:10:16 +0200320
Manish Pandey9c0ee742021-07-08 09:55:59 +0100321# Platforms from Mediatek
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500322make PLAT=mt8173 $(common_flags) all
323make PLAT=mt8183 $(common_flags) all
Rex-BC Chen946cace2021-11-17 10:15:42 +0800324make PLAT=mt8186 $(common_flags) COREBOOT=1 all
Bo-Chen Chen4d63afd2022-08-30 16:34:57 +0800325make PLAT=mt8188 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500326make PLAT=mt8192 $(common_flags) COREBOOT=1 all
Manish Pandey9c0ee742021-07-08 09:55:59 +0100327make PLAT=mt8195 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500328
329# Platforms from Qualcomm
330make PLAT=sc7180 $(common_flags) COREBOOT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200331
Zelalemc9531f82020-08-04 15:37:08 -0500332make PLAT=rk3288 CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500333 $(common_flags) ARCH=aarch32 AARCH32_SP=sp_min all
Madhukar Pappireddyd491ad02020-12-03 10:37:05 -0600334make PLAT=rk3368 $(common_flags) COREBOOT=1 \
335 ENABLE_STACK_PROTECTOR=strong all
336make PLAT=rk3399 $(common_flags) COREBOOT=1 PLAT_RK_DP_HDCP=1 \
337 ENABLE_STACK_PROTECTOR=strong all
338make PLAT=rk3328 $(common_flags) COREBOOT=1 PLAT_RK_SECURE_DDR_MINILOADER=1 \
339 ENABLE_STACK_PROTECTOR=strong all
340make PLAT=px30 $(common_flags) PLAT_RK_SECURE_DDR_MINILOADER=1 \
341 ENABLE_STACK_PROTECTOR=strong all
Fathi Boudra422bf772019-12-02 11:10:16 +0200342
343# Although we do several consecutive builds for the Tegra platform below, we
344# don't need to clean between each one because the Tegra makefiles specify
345# a different build directory per SoC.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500346make PLAT=tegra TARGET_SOC=t210 $(common_flags) all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500347make PLAT=tegra TARGET_SOC=t186 $(common_flags) all
348make PLAT=tegra TARGET_SOC=t194 $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200349
350# For the Xilinx platform, artificially increase the extents of BL31 memory
351# (using the platform-specific build options ZYNQMP_ATF_MEM_{BASE,SIZE}).
352# If we keep the default values, BL31 doesn't fit when it is built with all
353# these build flags.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500354make PLAT=zynqmp $(common_flags) \
Fathi Boudra422bf772019-12-02 11:10:16 +0200355 RESET_TO_BL31=1 SPD=tspd \
Zelalem4f3633e2021-06-18 11:53:47 -0500356 SDEI_SUPPORT=1 \
Fathi Boudra422bf772019-12-02 11:10:16 +0200357 ZYNQMP_ATF_MEM_BASE=0xFFFC0000 ZYNQMP_ATF_MEM_SIZE=0x00040000 \
358 all
359
Zelalemc9531f82020-08-04 15:37:08 -0500360# Build both for silicon (default) and virtual QEMU platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500361clean_build PLAT=versal $(common_flags)
362clean_build PLAT=versal $(common_flags) VERSAL_PLATFORM=versal_virt
Zelalemc9531f82020-08-04 15:37:08 -0500363
364# Platforms from Allwinner
Andre Przywara3a78c102022-04-26 11:08:54 +0100365clean_build PLAT=sun50i_a64 $(common_flags release) all
366clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_NATIVE=0 all
367clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_SCPI=0 all
368clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_AMEND_DTB=1 all
Andre Przywaracf78a512021-09-03 14:59:38 +0100369clean_build PLAT=sun50i_h6 $(common_flags) all
370clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_NATIVE=0 all
371clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_SCPI=0 all
372clean_build PLAT=sun50i_h616 $(common_flags) all
373clean_build PLAT=sun50i_r329 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500374
375# Platforms from i.MX
376make AARCH32_SP=optee ARCH=aarch32 ARM_ARCH_MAJOR=7 ARM_CORTEX_A7=yes \
377 CROSS_COMPILE=arm-none-eabi- PLAT=warp7 ${TBB_OPTIONS} \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500378 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500379make AARCH32_SP=optee ARCH=aarch32 CROSS_COMPILE=arm-none-eabi- PLAT=picopi \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500380 $(common_flags) all
Ying-Chun Liu (PaulLiu)f6528982021-11-17 17:20:00 +0800381make PLAT=imx8mm $(common_flags) NEED_BL2=yes MEASURED_BOOT=1 \
laurenw-arm8531e702022-06-09 15:32:37 -0500382 MBOOT_EL_HASH_ALG=sha256 ${TBB_OPTIONS} all
Madhukar Pappireddyc3ec06b2022-05-18 11:15:16 -0500383make PLAT=imx8mn $(common_flags) SDEI_SUPPORT=1 all
Ying-Chun Liu (PaulLiu)413e6102021-09-14 00:22:08 +0800384make PLAT=imx8mp $(common_flags) NEED_BL2=yes ${TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500385
Jacky Baib6cecc82021-06-07 09:49:46 +0800386# Due to the limited OCRAM space that can be used for TF-A, build test
387# will report failure caused by too small RAM size, so comment out the
388# build test for imx8mq in CI. It can also resolve the following ticket:
Zelalemc9531f82020-08-04 15:37:08 -0500389# https://developer.trustedfirmware.org/T626
Jacky Baib6cecc82021-06-07 09:49:46 +0800390#make PLAT=imx8mq $(common_flags release) all
Zelalemc9531f82020-08-04 15:37:08 -0500391
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500392make PLAT=imx8qm $(common_flags) all
393make PLAT=imx8qx $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500394
Olivier Deprezbac70192021-04-02 08:55:36 +0200395# Platforms for NXP Layerscape
Jiafei Pane48e56c2021-09-30 10:32:54 +0800396nxp_sb_flags="TRUSTED_BOARD_BOOT=1 CST_DIR=$(pwd) SPD=opteed"
397nxp_sb_fuse_flags="${nxp_sb_flags} FUSE_PROG=1"
398
399# Platform lx2
Olivier Deprezbac70192021-04-02 08:55:36 +0200400make PLAT=lx2160aqds $(common_flags) all
401make PLAT=lx2160ardb $(common_flags) all
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500402
403#CSF Based CoT:
Jiafei Pane48e56c2021-09-30 10:32:54 +0800404clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
405 $nxp_sb_fuse_flags DDR_PHY_BIN_PATH=$(pwd)
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500406
407#X509 Based CoT
Jiafei Pane48e56c2021-09-30 10:32:54 +0800408clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
409 $nxp_sb_flags GENERATE_COT=1 \
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500410 MBEDTLS_DIR=$(pwd)/mbedtls
411
412#BOOT_MODE=emmc and Stack protector
Jiafei Pane48e56c2021-09-30 10:32:54 +0800413clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=emmc \
414 $nxp_sb_fuse_flags ENABLE_STACK_PROTECTOR=strong
415
416# Platform ls1028ardb
417clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor
418clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc
419clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd
420
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800421# ls1028a Secure Boot
Jiafei Pane48e56c2021-09-30 10:32:54 +0800422clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor $nxp_sb_fuse_flags
423clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
424clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
Olivier Deprezbac70192021-04-02 08:55:36 +0200425
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800426# Platform ls1043ardb
427clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor
428clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand
429clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd
430
431# ls1043ardb Secure Boot
432clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
433clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
434clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
435
Jiafei Panbd0c22a2022-01-29 00:04:44 +0800436# ls1046ardb Secure Boot
437clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
438clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
439clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
440
441# ls1046afrwy Secure Boot
442clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
443clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
444
445# ls1046aqds Secure Boot
446clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
447clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
448clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
449clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
450
Jiafei Pan332cd792022-02-24 16:44:48 +0800451# ls1088ardb Secure Boot
452clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
453clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
454
455# ls1088aqds Secure Boot
456clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
457clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
458clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
459
Zelalemc9531f82020-08-04 15:37:08 -0500460# Platforms from Intel
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500461make PLAT=stratix10 $(common_flags) all
462make PLAT=agilex $(common_flags) all
Sieu Mun Tang03b57362022-03-05 01:54:59 +0800463make PLAT=n5x $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500464
465# Platforms from Broadcom
Madhukar Pappireddy97ad2582021-11-15 10:29:23 -0600466clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t \
467 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 DRIVER_I2C_ENABLE=1
468clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t-ns3 \
469 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 USE_USB=yes
Zelalemc9531f82020-08-04 15:37:08 -0500470
471# Platforms from Marvell
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500472make PLAT=a3700 $(common_flags) SCP_BL2=/dev/null CM3_SYSTEM_RESET=1 \
473 A3720_DB_PM_WAKEUP_SRC=1 HANDLE_EA_EL3_FIRST=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500474
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600475# Source files from mv-ddr-marvell repository are necessary
476# to build below four platforms
Manish Pandey7c1e7452021-11-05 12:54:15 +0000477wget https://downloads.trustedfirmware.org/tf-a/mv-ddr-marvell/mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
478tar -xzf mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600479mv mv-ddr-marvell drivers/marvell/mv_ddr
Zelalemc9531f82020-08-04 15:37:08 -0500480
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600481# These platforms from Marvell have dependency on GCC-6.2.1 toolchain
Pali Rohár8f890402021-07-19 13:48:05 +0200482make PLAT=a80x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200483 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200484make PLAT=a80x0_mcbin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200485 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200486make PLAT=a70x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200487 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200488make PLAT=a70x0_amc DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200489 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Robert Markodf3319e2021-10-20 11:01:12 +0200490make PLAT=a70x0_mochabin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
491 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200492make PLAT=a80x0_puzzle DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200493 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200494make PLAT=t9130 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200495 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500496make PLAT=t9130_cex7_eval DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
497 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500498
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600499# Removing the source files
500rm -rf drivers/marvell/mv_ddr 2> /dev/null
Zelalemc9531f82020-08-04 15:37:08 -0500501
502# Platforms from Meson
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500503make PLAT=gxbb $(common_flags) all
504make PLAT=gxl $(common_flags) all
505make PLAT=g12a $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500506
507# Platforms from Renesas
508# Renesas R-Car D3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500509clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500510 BL33=Makefile LIFEC_DBSC_PROTECT_ENABLE=0 LSI=D3 \
511 MBEDTLS_DIR=$(pwd)/mbedtls PMIC_ROHM_BD9571=0 \
512 RCAR_AVS_SETTING_ENABLE=0 SPD=none RCAR_LOSSY_ENABLE=0 \
513 RCAR_SA0_SIZE=0 RCAR_SYSTEM_SUSPEND=0 TRUSTED_BOARD_BOOT=1
514
515# Renesas R-Car H3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500516clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500517 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3 \
518 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
519 RCAR_DRAM_SPLIT=1 RCAR_GEN3_ULCB=1 SPD=opteed \
520 TRUSTED_BOARD_BOOT=1
521
522# Renesas R-Car H3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500523clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500524 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3N \
525 SPD=opteed TRUSTED_BOARD_BOOT=1
526
527# Renesas R-Car M3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500528clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500529 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3 \
530 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
531 RCAR_DRAM_SPLIT=2 RCAR_GEN3_ULCB=1 SPD=opteed \
532 TRUSTED_BOARD_BOOT=1
533
534# Renesas R-Car M3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500535clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500536 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3N \
537 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
538 RCAR_GEN3_ULCB=1 SPD=opteed TRUSTED_BOARD_BOOT=1
539
540# Renesas R-Car E3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500541clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500542 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=E3 \
543 RCAR_AVS_SETTING_ENABLE=0 RCAR_DRAM_DDR3L_MEMCONF=0 \
544 RCAR_SA0_SIZE=0 SPD=opteed TRUSTED_BOARD_BOOT=1
545
546# Renesas R-Car V3M Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500547clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500548 MBEDTLS_DIR=$(pwd)/mbedtls BL33=Makefile LSI=V3M MACHINE=eagle \
549 PMIC_ROHM_BD9571=0 RCAR_DRAM_SPLIT=0 RCAR_SYSTEM_SUSPEND=0 \
550 AVS_SETTING_ENABLE=0 SPD=none TRUSTED_BOARD_BOOT=1
551
Zelalemf4299672021-01-29 12:52:59 -0600552# Renesas HiHope RZ/G2M development kit
553clean_build PLAT=rzg $(common_flags) \
554 MBEDTLS_DIR=$(pwd)/mbedtls LSI=G2M \
555 RCAR_DRAM_SPLIT=2 RCAR_LOSSY_ENABLE=1 SPD=none
556
Zelalemc9531f82020-08-04 15:37:08 -0500557# Platforms from ST
Yann Gautiera69cf792021-09-01 11:19:01 +0200558# STM32MP1 SDMMC boot
559make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
560 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_SDMMC=1 \
561 BUILD_PLAT=build/stm32mp1-sdmmc/debug \
562 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
563
564# STM32MP1 eMMC boot
Zelalemc9531f82020-08-04 15:37:08 -0500565make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500566 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_EMMC=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200567 BUILD_PLAT=build/stm32mp1-emmc/debug \
568 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
569
570# STM32MP1 Raw NAND boot
571make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
572 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_RAW_NAND=1 \
573 BUILD_PLAT=build/stm32mp1-nand/debug \
574 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
575
576# STM32MP1 SPI NAND boot
577make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
578 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_SPI_NAND=1 \
579 BUILD_PLAT=build/stm32mp1-snand/debug \
580 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
581
582# STM32MP1 SPI NOR boot
583make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
584 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_SPI_NOR=1 \
585 BUILD_PLAT=build/stm32mp1-snor/debug \
586 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
587
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100588# STM32MP1 UART boot
589make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
590 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_UART_PROGRAMMER=1 \
591 BUILD_PLAT=build/stm32mp1-uart/debug \
592 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
593
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200594# STM32MP1 USB boot
595make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
596 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_USB_PROGRAMMER=1 \
597 BUILD_PLAT=build/stm32mp1-usb/debug \
598 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
599
Yann Gautiera69cf792021-09-01 11:19:01 +0200600# STM32MP1 SDMMC boot without FIP
601make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
602 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_SDMMC=1 \
603 BUILD_PLAT=build/stm32mp1-sdmmc-stm32image/debug \
604 STM32MP_USE_STM32IMAGE=1 \
605 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
Zelalemc9531f82020-08-04 15:37:08 -0500606
Yann Gautier773c5502022-03-10 17:24:47 +0100607# STM32MP13 SDMMC boot
608make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
609 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_SDMMC=1 \
610 BUILD_PLAT=build/stm32mp1-mp13-sdmmc/debug STM32MP13=1 \
611 ARCH=aarch32 AARCH32_SP=optee ENABLE_STACK_PROTECTOR=strong bl2
612
Zelalemc9531f82020-08-04 15:37:08 -0500613# Platforms from TI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500614make PLAT=k3 $(common_flags) all
Hari Nagalladadd89f2022-08-30 12:10:00 -0500615make PLAT=k3 TARGET_BOARD=j784s4 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500616
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500617clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS}
Zelalemc9531f82020-08-04 15:37:08 -0500618# Use GICV3 driver
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500619clean_build PLAT=qemu $(common_flags) QEMU_USE_GIC_DRIVER=QEMU_GICV3 \
Zelalemc9531f82020-08-04 15:37:08 -0500620 ENABLE_STACK_PROTECTOR=strong
621# Use encrypted FIP feature.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500622clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500623 BL32_RAM_LOCATION=tdram DECRYPTION_SUPPORT=aes_gcm ENCRYPT_BL31=1 \
624 ENCRYPT_BL32=1 FW_ENC_STATUS=0 SPD=opteed
Jens Wiklander1a9c2be2021-11-26 09:56:55 +0100625# QEMU with SPMD support
626clean_build PLAT=qemu $(common_flags) BL32=Makefile \
627 BL32_RAM_LOCATION=tdram ARM_BL31_IN_DRAM=1 \
628 SPD=spmd CTX_INCLUDE_EL2_REGS=0 SPMD_SPM_AT_SEL2=0 SPMC_OPTEE=1
Ruchika Gupta86e7f682022-04-12 10:25:46 +0530629# Measured Boot
laurenw-arm8531e702022-06-09 15:32:37 -0500630clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} MBOOT_EL_HASH_ALG=sha256 MEASURED_BOOT=1
Zelalemc9531f82020-08-04 15:37:08 -0500631
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500632clean_build PLAT=qemu_sbsa $(common_flags)
Fathi Boudra422bf772019-12-02 11:10:16 +0200633
Zelalemd86e8762020-08-21 18:24:28 -0500634# QEMU with SPM support
635clean_build PLAT=qemu_sbsa $(common_flags) BL32=Makefile SPM_MM=1 \
Manish Pandeyaa9a03b2021-11-17 10:03:17 +0000636 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0
Zelalemd86e8762020-08-21 18:24:28 -0500637
Fathi Boudra422bf772019-12-02 11:10:16 +0200638# For hikey enable PMF to include all files in the platform port
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500639make PLAT=hikey $(common_flags) ${TBB_OPTIONS} ENABLE_PMF=1 all
640make PLAT=hikey960 $(common_flags) ${TBB_OPTIONS} all
641make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200642
Zelalemc9531f82020-08-04 15:37:08 -0500643# Platforms from Socionext
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500644clean_build PLAT=uniphier $(common_flags) ${TBB_OPTIONS} SPD=tspd
645clean_build PLAT=uniphier $(common_flags) FIP_GZIP=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200646
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500647clean_build PLAT=synquacer $(common_flags) SPM_MM=1 \
Jassi Brar86080922022-06-27 14:16:34 -0500648 RESET_TO_BL31=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0 \
649 PRELOADED_BL33_BASE=0x0
Zelalemc9531f82020-08-04 15:37:08 -0500650
651# Support for SCP Message Interface protocol with platform specific drivers
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500652clean_build PLAT=synquacer $(common_flags) \
Jassi Brar86080922022-06-27 14:16:34 -0500653 RESET_TO_BL31=1 PRELOADED_BL33_BASE=0x0 SQ_USE_SCMI_DRIVER=1
Zelalemc9531f82020-08-04 15:37:08 -0500654
Jassi Brarb8c7ca02022-06-27 14:22:10 -0500655# Support for BL2 and TBBR
656clean_build PLAT=synquacer $(common_flags) \
657 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
658 SQ_USE_SCMI_DRIVER=1 SPD=opteed all
659
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500660make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200661
Zelalemc9531f82020-08-04 15:37:08 -0500662# Raspberry Pi Platforms
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500663make PLAT=rpi3 $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500664 ENABLE_STACK_PROTECTOR=strong PRELOADED_BL33_BASE=0xDEADBEEF all
Andre Przywarae917ec82021-09-03 15:01:30 +0100665clean_build PLAT=rpi4 $(common_flags) SMC_PCI_SUPPORT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200666
Zelalemc9531f82020-08-04 15:37:08 -0500667# A113D (AXG) platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500668clean_build PLAT=axg $(common_flags) SPD=opteed
669clean_build PLAT=axg $(common_flags) AML_USE_ATOS=1
Zelalemc9531f82020-08-04 15:37:08 -0500670
Stephan Gerhold141a7662021-12-07 20:42:14 +0100671# QTI MSM8916 platform
672clean_build PLAT=msm8916 $(common_flags)
673
Fathi Boudra422bf772019-12-02 11:10:16 +0200674cd ..