blob: 2c8ed855ef4116506937fe20c3068c3b004860e0 [file] [log] [blame]
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -05001#!/usr/bin/env bash
Fathi Boudra422bf772019-12-02 11:10:16 +02002#
Rohit Mathew17675f22024-02-14 22:41:37 +00003# Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
Fathi Boudra422bf772019-12-02 11:10:16 +02004#
5# SPDX-License-Identifier: BSD-3-Clause
6#
7
8#
9# This script builds the TF in different configs.
10# Rather than telling cov-build to build TF using a simple 'make all' command,
11# the goal here is to combine several build flags to analyse more of our source
12# code in a single 'build'. The Coverity Scan service does not have the notion
13# of separate types of build - there is just one linear sequence of builds in
14# the project history.
15#
16
Harrison Mutaiee958c12023-09-06 12:16:21 +010017set -E
18trap 'rc=$?; error_count=$((error_count+1));' ERR INT
Fathi Boudra422bf772019-12-02 11:10:16 +020019
20TF_SOURCES=$1
21if [ ! -d "$TF_SOURCES" ]; then
22 echo "ERROR: '$TF_SOURCES' does not exist or is not a directory"
23 echo "Usage: $(basename "$0") <trusted-firmware-directory>"
24 exit 1
25fi
26
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050027containing_dir="$(readlink -f "$(dirname "$0")/")"
28. $containing_dir/common-def.sh
29
Fathi Boudra422bf772019-12-02 11:10:16 +020030# Get mbed TLS library code to build Trusted Firmware with Trusted Board Boot
31# support. The version of mbed TLS to use here must be the same as when
32# building TF in the usual context.
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050033if [ ! -d "$MBED_TLS_DIR" ]; then
34 git clone -q --depth 1 -b "$MBED_TLS_SOURCES_TAG" "$MBED_TLS_URL_REPO" "$MBED_TLS_DIR"
Fathi Boudra422bf772019-12-02 11:10:16 +020035fi
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050036
David Vincze82db6932024-02-21 12:05:50 +010037if [ ! -d "$QCBOR_LIB_DIR" ]; then
38 git clone "$QCBOR_URL_REPO" "$QCBOR_LIB_DIR"
39 cd "$QCBOR_LIB_DIR"
40 git checkout v1.2
41fi
42
Fathi Boudra422bf772019-12-02 11:10:16 +020043cd "$TF_SOURCES"
44
45# Clean TF source dir to make sure we don't analyse temporary files.
46make distclean
47
48#
49# Build TF in different configurations to get as much coverage as possible
50#
51
Fathi Boudra422bf772019-12-02 11:10:16 +020052#
53# FVP platform
54# We'll use the following flags for all FVP builds.
55#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050056fvp_common_flags="$(common_flags) PLAT=fvp"
Fathi Boudra422bf772019-12-02 11:10:16 +020057
58# Try all possible SPDs.
Chris Kayab29d432023-08-10 13:06:18 +000059clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram \
60 SPD=tspd FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +020061clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd TSP_INIT_ASYNC=1 \
Sona Mathew40e5be92023-08-10 16:31:45 -050062 TSP_NS_INTR_ASYNC_PREEMPT=1 FVP_TRUSTED_SRAM_SIZE=384
Manish V Badarkhe48ed0bf2023-06-28 09:33:16 +010063clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed FVP_TRUSTED_SRAM_SIZE=384
Elizabeth Ho1a04df12023-07-27 16:06:24 +010064clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tlkd FVP_TRUSTED_SRAM_SIZE=384
Manish V Badarkhee7528ff2023-07-01 10:20:05 +010065clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=pncd SPD_PNCD_NS_IRQ=126 \
66 SPD_PNCD_S_IRQ=15 FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +020067
Zelalemc9531f82020-08-04 15:37:08 -050068# Dualroot chain of trust.
69clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tspd COT=dualroot
70
laurenw-armf48e9d22022-04-22 11:30:13 -050071# FEAT_RME with CCA chain of trust.
Manish V Badarkhe5304aaf2023-08-18 14:38:20 +010072clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} USE_ROMLIB=1 \
Manish V Badarkhed5e9c752023-11-07 17:57:36 +000073 ENABLE_RME=1 MEASURED_BOOT=1
laurenw-armf48e9d22022-04-22 11:30:13 -050074
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050075clean_build $fvp_common_flags SPD=trusty
76clean_build $fvp_common_flags SPD=trusty TRUSTY_SPD_WITH_GENERIC_SERVICES=1
Fathi Boudra422bf772019-12-02 11:10:16 +020077
Sona Mathewff9c2a72023-05-10 21:18:01 -050078# ERRATA ABI
79clean_build $fvp_common_flags ERRATA_ABI_SUPPORT=1
80
Fathi Boudra422bf772019-12-02 11:10:16 +020081# SDEI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050082clean_build $fvp_common_flags SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Fathi Boudra422bf772019-12-02 11:10:16 +020083
Zelalemc9531f82020-08-04 15:37:08 -050084# SDEI with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050085clean_build $fvp_common_flags SDEI_IN_FCONF=1 SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Zelalemc9531f82020-08-04 15:37:08 -050086
Zelalem4f3633e2021-06-18 11:53:47 -050087# PCI Service
88clean_build $fvp_common_flags SMC_PCI_SUPPORT=1
89
Zelalemc9531f82020-08-04 15:37:08 -050090# Secure interrupt descriptors with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050091clean_build $fvp_common_flags SEC_INT_DESC_IN_FCONF=1
Zelalemc9531f82020-08-04 15:37:08 -050092
Fathi Boudra422bf772019-12-02 11:10:16 +020093# Without coherent memory
Sona Mathewa06f62d2023-08-24 16:34:13 -050094clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd \
95 USE_COHERENT_MEM=0 FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +020096
97# Using PSCI extended State ID format rather than the original format
Sona Mathewa06f62d2023-08-24 16:34:13 -050098clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd \
99 PSCI_EXTENDED_STATE_ID=1 ARM_RECOM_STATE_ID_ENC=1 FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +0200100
101# Alternative boot flows (This changes some of the platform initialisation code)
Elizabeth Ho4cdb2f42023-07-11 12:27:14 +0100102clean_build $fvp_common_flags EL3_PAYLOAD_BASE=0x80000000
Fathi Boudra422bf772019-12-02 11:10:16 +0200103clean_build $fvp_common_flags PRELOADED_BL33_BASE=0x80000000
104
105# Using the SP804 timer instead of the Generic Timer
106clean_build $fvp_common_flags FVP_USE_SP804_TIMER=1
107
108# Using the CCN driver and multi cluster topology
109clean_build $fvp_common_flags FVP_CLUSTER_COUNT=4
110
111# PMF
112clean_build $fvp_common_flags ENABLE_PMF=1
113
114# stack protector
115clean_build $fvp_common_flags ENABLE_STACK_PROTECTOR=strong
116
117# AArch32 build
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500118clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200119 ARCH=aarch32 AARCH32_SP=sp_min \
120 RESET_TO_SP_MIN=1 PRELOADED_BL33_BASE=0x80000000
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500121clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200122 ARCH=aarch32 AARCH32_SP=sp_min
123
124# Xlat tables lib version 1 (AArch64 and AArch32)
125clean_build $fvp_common_flags ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500126clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200127 ARCH=aarch32 AARCH32_SP=sp_min ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
128
Zelalemc9531f82020-08-04 15:37:08 -0500129# SPM support based on Management Mode Interface Specification
Manish Pandeyaa9a03b2021-11-17 10:03:17 +0000130clean_build $fvp_common_flags SPM_MM=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0
Fathi Boudra422bf772019-12-02 11:10:16 +0200131
Zelalemc9531f82020-08-04 15:37:08 -0500132# SPM support with TOS(optee) as SPM sitting at S-EL1
133clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0
134
Shruti Gupta8cc89b92022-08-09 12:23:46 +0100135# SPM support with SPM at EL3 and TSP at S-EL1
136clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 CTX_INCLUDE_EL2_REGS=0 EL3_EXCEPTION_HANDLING=0 \
137 SPD=spmd SPMD_SPM_AT_SEL2=0 SPMC_AT_EL3=1 \
138 ARM_SPMC_MANIFEST_DTS=plat/arm/board/fvp/fdts/fvp_tsp_sp_manifest.dts
139
Zelalemc9531f82020-08-04 15:37:08 -0500140# SPM support with Secure hafnium as SPM sitting at S-EL2
141# SP_LAYOUT_FILE is used only during FIP creation but build won't progress
142# if we have NULL value to it, so passing a dummy string.
143clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=1 ARM_ARCH_MINOR=4 \
Max Shvetsov44d2a702021-02-18 16:41:45 +0000144 CTX_INCLUDE_EL2_REGS=1 SP_LAYOUT_FILE=dummy
Fathi Boudra422bf772019-12-02 11:10:16 +0200145
J-Alves85ba07b2023-07-12 14:37:45 +0100146# SPM support with logical partitions in the SPMD.
147clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=1 ARM_ARCH_MINOR=4 \
148 CTX_INCLUDE_EL2_REGS=1 SP_LAYOUT_FILE=dummy ENABLE_SPMD_LP=1
149
Marc Bonnici502fdaa2022-01-10 12:38:23 +0000150# SPM support with SPM sitting at EL3
151clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0 SPMC_AT_EL3=1
152
Harrison Mutaib352c0e2023-08-11 18:27:57 +0100153# Firmware Handoff framework support
154clean_build $fvp_common_flags TRANSFER_LIST=1
155
Fathi Boudra422bf772019-12-02 11:10:16 +0200156#BL2 at EL3 support
Harrison Mutaic3c8cfc2023-09-05 12:03:03 +0100157clean_build $fvp_common_flags RESET_TO_BL2=1 FVP_TRUSTED_SRAM_SIZE=384
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500158clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Maksims Svecovs7a0da522023-03-06 16:28:27 +0000159 ARCH=aarch32 AARCH32_SP=sp_min RESET_TO_BL2=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200160
Zelalemc9531f82020-08-04 15:37:08 -0500161# RAS Extension Support
Manish Pandeyc1fa25b2023-02-16 17:35:36 +0000162clean_build $fvp_common_flags EL3_EXCEPTION_HANDLING=1 ENABLE_FEAT_RAS=1 \
Manish Pandeyf3816802023-10-11 17:13:58 +0100163 FAULT_INJECTION_SUPPORT=1 HANDLE_EA_EL3_FIRST_NS=1 \
Manish Pandey010e9b42023-04-24 15:49:27 +0100164 SDEI_SUPPORT=1 PLATFORM_TEST_RAS_FFH=1
Zelalemc9531f82020-08-04 15:37:08 -0500165
Manish Pandeyfd4c6b72023-04-24 10:29:52 +0100166# EA handled in EL3 first
167clean_build $fvp_common_flags HANDLE_EA_EL3_FIRST_NS=1 PLATFORM_TEST_EA_FFH=1
168
Zelalemc9531f82020-08-04 15:37:08 -0500169# Hardware Assisted Coherency(DynamIQ)
170clean_build $fvp_common_flags FVP_CLUSTER_COUNT=1 FVP_MAX_CPUS_PER_CLUSTER=8 \
171 HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0
172
173# Pointer Authentication Support
174clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 \
Sona Mathewa06f62d2023-08-24 16:34:13 -0500175 ARM_ARCH_MINOR=5 EL3_EXCEPTION_HANDLING=1 BRANCH_PROTECTION=1 SDEI_SUPPORT=1 SPD=tspd \
Sona Mathew08c17962023-08-28 09:36:17 -0500176 TSP_NS_INTR_ASYNC_PREEMPT=1 FVP_TRUSTED_SRAM_SIZE=384
Zelalemc9531f82020-08-04 15:37:08 -0500177
178# Undefined Behaviour Sanitizer
179# Building with UBSAN SANITIZE_UB=on increases the executable size.
180# Hence it is only properly supported in bl31 with RESET_TO_BL31 enabled
181make $fvp_common_flags clean
Manish V Badarkhe4e79cab2023-09-07 10:07:58 +0100182make $fvp_common_flags SANITIZE_UB=on RESET_TO_BL31=1 FVP_TRUSTED_SRAM_SIZE=384 bl31
Zelalemc9531f82020-08-04 15:37:08 -0500183
184# debugfs feature
185clean_build $fvp_common_flags DEBUG=1 USE_DEBUGFS=1
186
187# MPAM feature
Arvind Ram Prakashbd4e43a2023-10-02 11:12:34 -0500188clean_build $fvp_common_flags ENABLE_FEAT_MPAM=1
Zelalemc9531f82020-08-04 15:37:08 -0500189
190# Using GICv3.1 driver with extended PPI and SPI range
191clean_build $fvp_common_flags GIC_EXT_INTID=1
192
193# Using GICv4 features with extended PPI and SPI range
194clean_build $fvp_common_flags GIC_ENABLE_V4_EXTN=1 GIC_EXT_INTID=1
195
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100196# Measured Boot
laurenw-arm8531e702022-06-09 15:32:37 -0500197clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} MBOOT_EL_HASH_ALG=sha256 MEASURED_BOOT=1 USE_ROMLIB=1
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100198
Manish V Badarkhef43e3f52022-06-21 20:37:25 +0100199# DRTM
200clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} TPM_HASH_ALG=sha256 DRTM_SUPPORT=1 USE_ROMLIB=1
201
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100202# CoT descriptors in device tree
Manish V Badarkhe81102d12020-10-05 08:02:30 +0100203clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} COT_DESC_IN_DTB=1 USE_ROMLIB=1
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100204
Chris Kayf4789fe2023-06-12 15:52:28 +0100205# PSA FWU support
206clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_GPT_SUPPORT=1 PSA_FWU_SUPPORT=1 USE_ROMLIB=1 FVP_TRUSTED_SRAM_SIZE=384
Manish V Badarkhe107c8e32021-08-02 19:49:32 +0100207
Manish V Badarkhe92616ae2023-09-18 10:06:00 +0100208# PSA Crypto support
209clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} PSA_CRYPTO=1 FVP_TRUSTED_SRAM_SIZE=384
210
johpow01153c8b22021-11-03 14:38:36 -0500211# SME and HCX features
212clean_build $fvp_common_flags ENABLE_SME_FOR_NS=1 ENABLE_FEAT_HCX=1
213
Jayanth Dodderi Chidanand41edd012023-01-12 14:50:34 +0000214# SME2
215clean_build $fvp_common_flags ENABLE_SME2_FOR_NS=1 ENABLE_SME_FOR_NS=1 ENABLE_FEAT_HCX=1
216
Jayanth Dodderi Chidanand84da1962022-04-11 11:38:44 +0100217# Architectural Feature Detection mechanism
218clean_build $fvp_common_flags FEATURE_DETECTION=1
219
Manish Pandeye3561fd2023-01-05 10:46:25 +0000220# RNG trap feature
221clean_build $fvp_common_flags ENABLE_FEAT_RNG=1 ENABLE_FEAT_RNG_TRAP=1
222
Yi Choua765ae42023-05-26 15:51:02 +0800223# OPTEE_ALLOW_SMC_LOAD and CROS_WIDEVINE_SMC features
224clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed OPTEE_ALLOW_SMC_LOAD=1 CROS_WIDEVINE_SMC=1 PLAT_XLAT_TABLES_DYNAMIC=1 FVP_TRUSTED_SRAM_SIZE=384
Jeffrey Kardatzke09e18e22023-01-25 12:24:13 -0800225
Jayanth Dodderi Chidanand508936d2023-12-22 14:33:38 +0000226# Report Context_Memory
227clean_build $fvp_common_flags PLATFORM_REPORT_CTX_MEM_USE=1
228
Fathi Boudra422bf772019-12-02 11:10:16 +0200229#
230# Juno platform
231# We'll use the following flags for all Juno builds.
232#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500233juno_common_flags="$(common_flags) PLAT=juno"
Fathi Boudra422bf772019-12-02 11:10:16 +0200234clean_build $juno_common_flags SPD=tspd ${ARM_TBB_OPTIONS}
Elizabeth Ho4cdb2f42023-07-11 12:27:14 +0100235clean_build $juno_common_flags EL3_PAYLOAD_BASE=0x80000000
Manish V Badarkhe05626442023-09-12 09:54:50 +0100236clean_build $juno_common_flags ENABLE_STACK_PROTECTOR=strong ETHOSN_NPU_DRIVER=1
237clean_build $juno_common_flags ${ARM_TBB_OPTIONS} ENABLE_STACK_PROTECTOR=strong ETHOSN_NPU_DRIVER=1 ETHOSN_NPU_TZMP1=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200238clean_build $juno_common_flags CSS_USE_SCMI_SDS_DRIVER=0
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500239
Jayanth Dodderi Chidanand055394a2022-10-19 09:20:20 +0100240# TRNG Service
241clean_build $juno_common_flags TRNG_SUPPORT=1
242
Fathi Boudra422bf772019-12-02 11:10:16 +0200243#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530244# Reference Design platform RD-V1
Zelalemc9531f82020-08-04 15:37:08 -0500245#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530246make $(common_flags) PLAT=rdv1 ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500247
248#
Aditya Angadi61c54762021-01-04 09:30:52 +0530249# Reference Design platform RD-V1-MC
Zelalemc9531f82020-08-04 15:37:08 -0500250#
Rohit Mathew17675f22024-02-14 22:41:37 +0000251make $(common_flags) PLAT=rdv1mc ${ARM_TBB_OPTIONS} NRD_CHIP_COUNT=4 all
Zelalemc9531f82020-08-04 15:37:08 -0500252
253#
Vijayenthiran Subramaniama66de332020-11-23 14:20:14 +0530254# Reference Design Platform RD-N2
255#
256make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} all
Omkar Anand Kulkarnif6e268e2023-06-21 20:32:22 +0530257# RAS Extension Support
258make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} ENABLE_FEAT_RAS=1 \
Manish Pandeyf3816802023-10-11 17:13:58 +0100259 HANDLE_EA_EL3_FIRST_NS=1 SDEI_SUPPORT=1 SPM_MM=1 all
260
Nishant Sharmabd7092e2023-10-11 09:17:13 +0100261# SPMC At EL3 Support
262make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} SPMC_AT_EL3=1 SPD=spmd \
263 SPMD_SPM_AT_SEL2=0 BL32=1 SPMC_AT_EL3_SEL0_SP=1 EL3_EXCEPTION_HANDLING=1 \
264 PLAT_RO_XLAT_TABLES=1 all
Vijayenthiran Subramaniama66de332020-11-23 14:20:14 +0530265
266#
Zelalemc9531f82020-08-04 15:37:08 -0500267# Neoverse N1 SDP platform
268#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500269make $(common_flags) PLAT=n1sdp ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500270
271#
272# FVP VE platform
273#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500274make $(common_flags) PLAT=fvp_ve AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500275 CROSS_COMPILE=arm-none-eabi- ARM_ARCH_MAJOR=7 \
276 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
277 FVP_HW_CONFIG_DTS=fdts/fvp-ve-Cortex-A5x1.dts all
278
279#
280# A5 DesignStart Platform
281#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500282make $(common_flags) PLAT=a5ds AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500283 ARM_ARCH_MAJOR=7 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
284 CROSS_COMPILE=arm-none-eabi- FVP_HW_CONFIG_DTS=fdts/a5ds.dts
285
286#
287# Corstone700 Platform
288#
289
290corstone700_common_flags="CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500291 $(common_flags) \
Zelalemc9531f82020-08-04 15:37:08 -0500292 PLAT=corstone700 \
293 ARCH=aarch32 \
294 RESET_TO_SP_MIN=1 \
295 AARCH32_SP=sp_min \
296 ARM_LINUX_KERNEL_AS_BL33=0 \
297 ARM_PRELOADED_DTB_BASE=0x80400000 \
298 ENABLE_PIE=1 \
Zelalemc9531f82020-08-04 15:37:08 -0500299 ENABLE_STACK_PROTECTOR=all \
300 all"
301
302echo "Info: Building Corstone700 FVP ..."
303
304make TARGET_PLATFORM=fvp ${corstone700_common_flags}
305
306echo "Info: Building Corstone700 FPGA ..."
307
308make TARGET_PLATFORM=fpga ${corstone700_common_flags}
309
310#
311# Arm internal FPGA port
312#
Andre Przywara13361b62022-04-26 11:16:55 +0100313make PLAT=arm_fpga $(common_flags release) \
314 FPGA_PRELOADED_DTB_BASE=0x88000000 PRELOADED_BL33_BASE=0x82080000 all
Zelalemc9531f82020-08-04 15:37:08 -0500315
316#
Usama Arifcba711d2021-08-04 15:53:42 +0100317# Total Compute platforms
Zelalemc9531f82020-08-04 15:37:08 -0500318#
laurenw-arm915f70a2023-07-14 16:20:49 -0500319clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=1 ${ARM_TBB_OPTIONS}
320clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} MEASURED_BOOT=1
David Vincze82db6932024-02-21 12:05:50 +0100321clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} MEASURED_BOOT=1 \
322 DICE_PROTECTION_ENVIRONMENT=1 QCBOR_DIR=$(pwd)/qcbor
laurenw-arm915f70a2023-07-14 16:20:49 -0500323clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} PLATFORM_TEST=rss-rotpk
324clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} PLATFORM_TEST=rss-nv-counters
Manish V Badarkhe58a88f02023-11-06 21:42:11 +0000325clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} PLATFORM_TEST=tfm-testsuite \
Manish V Badarkhe8f3a3fa2024-03-13 11:37:46 +0000326 MEASURED_BOOT=1 TF_M_TESTS_PATH=$(pwd)/../tf-m-tests TF_M_EXTRAS_PATH=$(pwd)/../tf-m-extras
Fathi Boudra422bf772019-12-02 11:10:16 +0200327
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530328#
329# Morello platform
330#
Chandni Cherukuricbd45962021-12-12 13:37:33 +0530331clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=fvp ${ARM_TBB_OPTIONS}
332clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=soc ${ARM_TBB_OPTIONS}
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530333
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100334#
Vishnu Banavath2cb72b32022-01-20 14:27:55 +0000335# corstone1000 Platform
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100336#
337
338make $(common_flags) \
Vishnu Banavath2cb72b32022-01-20 14:27:55 +0000339 PLAT=corstone1000 \
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100340 SPD=spmd \
341 TARGET_PLATFORM=fpga \
342 ENABLE_STACK_PROTECTOR=strong \
343 ENABLE_PIE=1 \
Maksims Svecovs7a0da522023-03-06 16:28:27 +0000344 RESET_TO_BL2=1 \
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100345 SPMD_SPM_AT_SEL2=0 \
346 ${ARM_TBB_OPTIONS} \
347 CREATE_KEYS=1 \
348 COT=tbbr \
349 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
350 bl2 \
351 bl31
352
johpow01aac58582021-10-05 16:51:34 -0500353#
354# FVP-R platform
355#
356clean_build $(common_flags) PLAT=fvp_r ${ARM_TBB_OPTIONS} ENABLE_STACK_PROTECTOR=all
357
Fathi Boudra422bf772019-12-02 11:10:16 +0200358# Partners' platforms.
359# Enable as many features as possible.
360# We don't need to clean between each build here because we only do one build
361# per platform so we don't hit the build flags dependency problem.
Fathi Boudra422bf772019-12-02 11:10:16 +0200362
Manish Pandey9c0ee742021-07-08 09:55:59 +0100363# Platforms from Mediatek
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500364make PLAT=mt8173 $(common_flags) all
365make PLAT=mt8183 $(common_flags) all
Rex-BC Chen946cace2021-11-17 10:15:42 +0800366make PLAT=mt8186 $(common_flags) COREBOOT=1 all
Bo-Chen Chen4d63afd2022-08-30 16:34:57 +0800367make PLAT=mt8188 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500368make PLAT=mt8192 $(common_flags) COREBOOT=1 all
Manish Pandey9c0ee742021-07-08 09:55:59 +0100369make PLAT=mt8195 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500370
371# Platforms from Qualcomm
372make PLAT=sc7180 $(common_flags) COREBOOT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200373
Zelalemc9531f82020-08-04 15:37:08 -0500374make PLAT=rk3288 CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500375 $(common_flags) ARCH=aarch32 AARCH32_SP=sp_min all
Madhukar Pappireddyd491ad02020-12-03 10:37:05 -0600376make PLAT=rk3368 $(common_flags) COREBOOT=1 \
377 ENABLE_STACK_PROTECTOR=strong all
378make PLAT=rk3399 $(common_flags) COREBOOT=1 PLAT_RK_DP_HDCP=1 \
379 ENABLE_STACK_PROTECTOR=strong all
380make PLAT=rk3328 $(common_flags) COREBOOT=1 PLAT_RK_SECURE_DDR_MINILOADER=1 \
381 ENABLE_STACK_PROTECTOR=strong all
382make PLAT=px30 $(common_flags) PLAT_RK_SECURE_DDR_MINILOADER=1 \
383 ENABLE_STACK_PROTECTOR=strong all
Fathi Boudra422bf772019-12-02 11:10:16 +0200384
385# Although we do several consecutive builds for the Tegra platform below, we
386# don't need to clean between each one because the Tegra makefiles specify
387# a different build directory per SoC.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500388make PLAT=tegra TARGET_SOC=t210 $(common_flags) all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500389make PLAT=tegra TARGET_SOC=t186 $(common_flags) all
390make PLAT=tegra TARGET_SOC=t194 $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200391
392# For the Xilinx platform, artificially increase the extents of BL31 memory
393# (using the platform-specific build options ZYNQMP_ATF_MEM_{BASE,SIZE}).
394# If we keep the default values, BL31 doesn't fit when it is built with all
395# these build flags.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500396make PLAT=zynqmp $(common_flags) \
Fathi Boudra422bf772019-12-02 11:10:16 +0200397 RESET_TO_BL31=1 SPD=tspd \
Zelalem4f3633e2021-06-18 11:53:47 -0500398 SDEI_SUPPORT=1 \
Fathi Boudra422bf772019-12-02 11:10:16 +0200399 ZYNQMP_ATF_MEM_BASE=0xFFFC0000 ZYNQMP_ATF_MEM_SIZE=0x00040000 \
400 all
401
Zelalemc9531f82020-08-04 15:37:08 -0500402# Build both for silicon (default) and virtual QEMU platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500403clean_build PLAT=versal $(common_flags)
404clean_build PLAT=versal $(common_flags) VERSAL_PLATFORM=versal_virt
Zelalemc9531f82020-08-04 15:37:08 -0500405
Michal Simek0f135242022-09-20 15:24:56 +0200406# Build Xilinx Versal NET platform
407clean_build PLAT=versal_net $(common_flags)
408
Jayanth Dodderi Chidanand0a2dd1e2022-10-27 11:17:37 +0100409# Build Xilinx Versal NET without Platform Management support
410clean_build PLAT=versal_net $(common_flags) TFA_NO_PM=1
411
Zelalemc9531f82020-08-04 15:37:08 -0500412# Platforms from Allwinner
Andre Przywara3a78c102022-04-26 11:08:54 +0100413clean_build PLAT=sun50i_a64 $(common_flags release) all
414clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_NATIVE=0 all
415clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_SCPI=0 all
416clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_AMEND_DTB=1 all
Andre Przywaracf78a512021-09-03 14:59:38 +0100417clean_build PLAT=sun50i_h6 $(common_flags) all
418clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_NATIVE=0 all
419clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_SCPI=0 all
420clean_build PLAT=sun50i_h616 $(common_flags) all
421clean_build PLAT=sun50i_r329 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500422
423# Platforms from i.MX
424make AARCH32_SP=optee ARCH=aarch32 ARM_ARCH_MAJOR=7 ARM_CORTEX_A7=yes \
425 CROSS_COMPILE=arm-none-eabi- PLAT=warp7 ${TBB_OPTIONS} \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500426 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500427make AARCH32_SP=optee ARCH=aarch32 CROSS_COMPILE=arm-none-eabi- PLAT=picopi \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500428 $(common_flags) all
Ying-Chun Liu (PaulLiu)f6528982021-11-17 17:20:00 +0800429make PLAT=imx8mm $(common_flags) NEED_BL2=yes MEASURED_BOOT=1 \
laurenw-arm8531e702022-06-09 15:32:37 -0500430 MBOOT_EL_HASH_ALG=sha256 ${TBB_OPTIONS} all
Madhukar Pappireddyc3ec06b2022-05-18 11:15:16 -0500431make PLAT=imx8mn $(common_flags) SDEI_SUPPORT=1 all
Ying-Chun Liu (PaulLiu)413e6102021-09-14 00:22:08 +0800432make PLAT=imx8mp $(common_flags) NEED_BL2=yes ${TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500433
Jacky Baib6cecc82021-06-07 09:49:46 +0800434# Due to the limited OCRAM space that can be used for TF-A, build test
435# will report failure caused by too small RAM size, so comment out the
436# build test for imx8mq in CI. It can also resolve the following ticket:
Zelalemc9531f82020-08-04 15:37:08 -0500437# https://developer.trustedfirmware.org/T626
Jacky Baib6cecc82021-06-07 09:49:46 +0800438#make PLAT=imx8mq $(common_flags release) all
Zelalemc9531f82020-08-04 15:37:08 -0500439
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500440make PLAT=imx8qm $(common_flags) all
441make PLAT=imx8qx $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500442
Jacky Baif5e936c2023-12-27 11:11:09 +0800443make PLAT=imx8ulp $(common_flags) all
444
Jacky Bai87091a62023-06-21 16:25:12 +0800445make PLAT=imx93 $(common_flags) all
446
Olivier Deprezbac70192021-04-02 08:55:36 +0200447# Platforms for NXP Layerscape
Jiafei Pane48e56c2021-09-30 10:32:54 +0800448nxp_sb_flags="TRUSTED_BOARD_BOOT=1 CST_DIR=$(pwd) SPD=opteed"
449nxp_sb_fuse_flags="${nxp_sb_flags} FUSE_PROG=1"
450
451# Platform lx2
Olivier Deprezbac70192021-04-02 08:55:36 +0200452make PLAT=lx2160aqds $(common_flags) all
453make PLAT=lx2160ardb $(common_flags) all
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500454
455#CSF Based CoT:
Jiafei Pane48e56c2021-09-30 10:32:54 +0800456clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
457 $nxp_sb_fuse_flags DDR_PHY_BIN_PATH=$(pwd)
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500458
459#X509 Based CoT
Jiafei Pane48e56c2021-09-30 10:32:54 +0800460clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
461 $nxp_sb_flags GENERATE_COT=1 \
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500462 MBEDTLS_DIR=$(pwd)/mbedtls
463
464#BOOT_MODE=emmc and Stack protector
Jiafei Pane48e56c2021-09-30 10:32:54 +0800465clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=emmc \
466 $nxp_sb_fuse_flags ENABLE_STACK_PROTECTOR=strong
467
468# Platform ls1028ardb
469clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor
470clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc
471clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd
472
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800473# ls1028a Secure Boot
Jiafei Pane48e56c2021-09-30 10:32:54 +0800474clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor $nxp_sb_fuse_flags
475clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
476clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
Olivier Deprezbac70192021-04-02 08:55:36 +0200477
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800478# Platform ls1043ardb
479clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor
480clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand
481clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd
482
483# ls1043ardb Secure Boot
484clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
485clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
486clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
487
Jiafei Panbd0c22a2022-01-29 00:04:44 +0800488# ls1046ardb Secure Boot
489clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
490clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
491clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
492
493# ls1046afrwy Secure Boot
494clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
495clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
496
497# ls1046aqds Secure Boot
498clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
499clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
500clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
501clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
502
Jiafei Pan332cd792022-02-24 16:44:48 +0800503# ls1088ardb Secure Boot
504clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
505clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
506
507# ls1088aqds Secure Boot
508clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
509clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
510clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
511
Zelalemc9531f82020-08-04 15:37:08 -0500512# Platforms from Intel
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500513make PLAT=stratix10 $(common_flags) all
514make PLAT=agilex $(common_flags) all
Sieu Mun Tang9081bac2023-05-29 18:08:24 +0800515make PLAT=agilex5 $(common_flags) all
Sieu Mun Tang03b57362022-03-05 01:54:59 +0800516make PLAT=n5x $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500517
518# Platforms from Broadcom
Madhukar Pappireddy97ad2582021-11-15 10:29:23 -0600519clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t \
520 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 DRIVER_I2C_ENABLE=1
521clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t-ns3 \
522 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 USE_USB=yes
Zelalemc9531f82020-08-04 15:37:08 -0500523
524# Platforms from Marvell
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500525make PLAT=a3700 $(common_flags) SCP_BL2=/dev/null CM3_SYSTEM_RESET=1 \
Manish Pandey9ef33c52022-10-25 16:41:49 +0100526 A3720_DB_PM_WAKEUP_SRC=1 HANDLE_EA_EL3_FIRST_NS=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500527
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600528# Source files from mv-ddr-marvell repository are necessary
529# to build below four platforms
Manish Pandey7c1e7452021-11-05 12:54:15 +0000530wget https://downloads.trustedfirmware.org/tf-a/mv-ddr-marvell/mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
531tar -xzf mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600532mv mv-ddr-marvell drivers/marvell/mv_ddr
Zelalemc9531f82020-08-04 15:37:08 -0500533
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600534# These platforms from Marvell have dependency on GCC-6.2.1 toolchain
Pali Rohár8f890402021-07-19 13:48:05 +0200535make PLAT=a80x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200536 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200537make PLAT=a80x0_mcbin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200538 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200539make PLAT=a70x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200540 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200541make PLAT=a70x0_amc DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200542 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Robert Markodf3319e2021-10-20 11:01:12 +0200543make PLAT=a70x0_mochabin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
544 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200545make PLAT=a80x0_puzzle DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200546 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200547make PLAT=t9130 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200548 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500549make PLAT=t9130_cex7_eval DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
550 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500551
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600552# Removing the source files
553rm -rf drivers/marvell/mv_ddr 2> /dev/null
Zelalemc9531f82020-08-04 15:37:08 -0500554
555# Platforms from Meson
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500556make PLAT=gxbb $(common_flags) all
557make PLAT=gxl $(common_flags) all
558make PLAT=g12a $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500559
560# Platforms from Renesas
561# Renesas R-Car D3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500562clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500563 BL33=Makefile LIFEC_DBSC_PROTECT_ENABLE=0 LSI=D3 \
564 MBEDTLS_DIR=$(pwd)/mbedtls PMIC_ROHM_BD9571=0 \
565 RCAR_AVS_SETTING_ENABLE=0 SPD=none RCAR_LOSSY_ENABLE=0 \
566 RCAR_SA0_SIZE=0 RCAR_SYSTEM_SUSPEND=0 TRUSTED_BOARD_BOOT=1
567
568# Renesas R-Car H3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500569clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500570 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3 \
571 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
572 RCAR_DRAM_SPLIT=1 RCAR_GEN3_ULCB=1 SPD=opteed \
573 TRUSTED_BOARD_BOOT=1
574
575# Renesas R-Car H3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500576clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500577 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3N \
578 SPD=opteed TRUSTED_BOARD_BOOT=1
579
580# Renesas R-Car M3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500581clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500582 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3 \
583 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
584 RCAR_DRAM_SPLIT=2 RCAR_GEN3_ULCB=1 SPD=opteed \
585 TRUSTED_BOARD_BOOT=1
586
587# Renesas R-Car M3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500588clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500589 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3N \
590 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
591 RCAR_GEN3_ULCB=1 SPD=opteed TRUSTED_BOARD_BOOT=1
592
593# Renesas R-Car E3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500594clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500595 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=E3 \
596 RCAR_AVS_SETTING_ENABLE=0 RCAR_DRAM_DDR3L_MEMCONF=0 \
597 RCAR_SA0_SIZE=0 SPD=opteed TRUSTED_BOARD_BOOT=1
598
599# Renesas R-Car V3M Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500600clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500601 MBEDTLS_DIR=$(pwd)/mbedtls BL33=Makefile LSI=V3M MACHINE=eagle \
602 PMIC_ROHM_BD9571=0 RCAR_DRAM_SPLIT=0 RCAR_SYSTEM_SUSPEND=0 \
603 AVS_SETTING_ENABLE=0 SPD=none TRUSTED_BOARD_BOOT=1
604
Zelalemf4299672021-01-29 12:52:59 -0600605# Renesas HiHope RZ/G2M development kit
606clean_build PLAT=rzg $(common_flags) \
607 MBEDTLS_DIR=$(pwd)/mbedtls LSI=G2M \
608 RCAR_DRAM_SPLIT=2 RCAR_LOSSY_ENABLE=1 SPD=none
609
Zelalemc9531f82020-08-04 15:37:08 -0500610# Platforms from ST
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100611stm32mp1_common_flags="$(common_flags) \
612 ARCH=aarch32 \
613 ARM_ARCH_MAJOR=7 \
614 CROSS_COMPILE=arm-none-eabi- \
615 ENABLE_STACK_PROTECTOR=strong \
616 PLAT=stm32mp1"
617
Yann Gautiera69cf792021-09-01 11:19:01 +0200618# STM32MP1 SDMMC boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000619make ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200620 BUILD_PLAT=build/stm32mp1-sdmmc/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100621 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200622
Yann Gautier15c45392023-08-21 11:03:33 +0200623# STM32MP1 SDMMC boot BL2 without AARCH32_SP
624make ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
625 BUILD_PLAT=build/stm32mp1-sdmmc/debug \
626 bl2
627
Yann Gautiera69cf792021-09-01 11:19:01 +0200628# STM32MP1 eMMC boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000629make ${stm32mp1_common_flags} STM32MP_EMMC=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200630 BUILD_PLAT=build/stm32mp1-emmc/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100631 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200632
633# STM32MP1 Raw NAND boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000634make ${stm32mp1_common_flags} STM32MP_RAW_NAND=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200635 BUILD_PLAT=build/stm32mp1-nand/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100636 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200637
638# STM32MP1 SPI NAND boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000639make ${stm32mp1_common_flags} STM32MP_SPI_NAND=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200640 BUILD_PLAT=build/stm32mp1-snand/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100641 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200642
643# STM32MP1 SPI NOR boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000644make ${stm32mp1_common_flags} STM32MP_SPI_NOR=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200645 BUILD_PLAT=build/stm32mp1-snor/debug \
Govindraj Raja95f855c2023-03-01 13:11:42 +0000646 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200647
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100648# STM32MP1 UART boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000649make ${stm32mp1_common_flags} STM32MP_UART_PROGRAMMER=1 \
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100650 BUILD_PLAT=build/stm32mp1-uart/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100651 AARCH32_SP=sp_min bl2 bl32
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100652
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200653# STM32MP1 USB boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000654make ${stm32mp1_common_flags} STM32MP_USB_PROGRAMMER=1 \
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200655 BUILD_PLAT=build/stm32mp1-usb/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100656 AARCH32_SP=sp_min bl2 bl32
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200657
Lionel Debieve8f464c02022-10-13 09:25:45 +0200658# STM32MP1 TBBR
Govindraj Raja95f855c2023-03-01 13:11:42 +0000659make ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
Yann Gautier741e8492022-11-14 19:04:27 +0100660 BUILD_PLAT=build/stm32mp1-sdmmc-tbbr/debug \
Lionel Debieve8f464c02022-10-13 09:25:45 +0200661 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100662 AARCH32_SP=sp_min bl2 bl32
Lionel Debieve8f464c02022-10-13 09:25:45 +0200663
Govindraj Raja95f855c2023-03-01 13:11:42 +0000664stm32mp13_common_flags="${stm32mp1_common_flags} \
665 AARCH32_SP=optee \
666 STM32MP13=1"
667
Yann Gautier773c5502022-03-10 17:24:47 +0100668# STM32MP13 SDMMC boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000669make ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100670 BUILD_PLAT=build/stm32mp1-mp13-sdmmc/debug bl2
Yann Gautier773c5502022-03-10 17:24:47 +0100671
Lionel Debieve8f464c02022-10-13 09:25:45 +0200672# STM32MP13 TBBR
Govindraj Raja95f855c2023-03-01 13:11:42 +0000673make ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Lionel Debieve8f464c02022-10-13 09:25:45 +0200674 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100675 BUILD_PLAT=build/stm32mp1-mp13-sdmmc-tbbr/debug bl2
Lionel Debieve8f464c02022-10-13 09:25:45 +0200676
Yann Gautiera66e5012022-12-13 13:52:35 +0100677# STM32MP13 TBBR DECRYPTION AES GCM
Govindraj Raja95f855c2023-03-01 13:11:42 +0000678make ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Yann Gautiera66e5012022-12-13 13:52:35 +0100679 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
680 DECRYPTION_SUPPORT=aes_gcm ENCRYPT_BL32=1 \
681 BUILD_PLAT=build/stm32mp1-mp13-sdmmc-tbbr-dec/debug bl2
682
Yann Gautiere9da1e22023-08-11 14:50:04 +0200683stm32mp2_common_flags="$(common_flags) \
684 ARCH=aarch64 \
685 CROSS_COMPILE=aarch64-none-elf- \
686 PLAT=stm32mp2"
687
688# STM32MP25 SDMMC boot
689make ${stm32mp2_common_flags} STM32MP_SDMMC=1 \
690 SPD=opteed STM32MP_DDR4_TYPE=1 \
691 BUILD_PLAT=build/stm32mp2-mp25-sdmmc/debug
692
Zelalemc9531f82020-08-04 15:37:08 -0500693# Platforms from TI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500694make PLAT=k3 $(common_flags) all
Hari Nagalladadd89f2022-08-30 12:10:00 -0500695make PLAT=k3 TARGET_BOARD=j784s4 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500696
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500697clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS}
Zelalemc9531f82020-08-04 15:37:08 -0500698# Use GICV3 driver
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500699clean_build PLAT=qemu $(common_flags) QEMU_USE_GIC_DRIVER=QEMU_GICV3 \
Zelalemc9531f82020-08-04 15:37:08 -0500700 ENABLE_STACK_PROTECTOR=strong
Dongjiu Geng72819ee2023-06-16 18:48:57 +0800701# Use GICV3 driver with SDEI support
702clean_build PLAT=qemu $(common_flags) QEMU_USE_GIC_DRIVER=QEMU_GICV3 \
703 ENABLE_STACK_PROTECTOR=strong SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Zelalemc9531f82020-08-04 15:37:08 -0500704# Use encrypted FIP feature.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500705clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500706 BL32_RAM_LOCATION=tdram DECRYPTION_SUPPORT=aes_gcm ENCRYPT_BL31=1 \
707 ENCRYPT_BL32=1 FW_ENC_STATUS=0 SPD=opteed
Jens Wiklander1a9c2be2021-11-26 09:56:55 +0100708# QEMU with SPMD support
709clean_build PLAT=qemu $(common_flags) BL32=Makefile \
710 BL32_RAM_LOCATION=tdram ARM_BL31_IN_DRAM=1 \
711 SPD=spmd CTX_INCLUDE_EL2_REGS=0 SPMD_SPM_AT_SEL2=0 SPMC_OPTEE=1
Ruchika Gupta86e7f682022-04-12 10:25:46 +0530712# Measured Boot
laurenw-arm8531e702022-06-09 15:32:37 -0500713clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} MBOOT_EL_HASH_ALG=sha256 MEASURED_BOOT=1
Raymond Mao7681ba02023-08-10 14:05:44 -0700714# Transfer List
715clean_build PLAT=qemu $(common_flags) TRANSFER_LIST=1
Zelalemc9531f82020-08-04 15:37:08 -0500716
Jean-Philippe Bruckerb586eee2023-11-02 18:13:30 +0000717# FEAT_RME
718clean_build PLAT=qemu $(common_flags) ENABLE_RME=1 \
719 QEMU_USE_GIC_DRIVER=QEMU_GICV3
720
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500721clean_build PLAT=qemu_sbsa $(common_flags)
Fathi Boudra422bf772019-12-02 11:10:16 +0200722
Zelalemd86e8762020-08-21 18:24:28 -0500723# QEMU with SPM support
724clean_build PLAT=qemu_sbsa $(common_flags) BL32=Makefile SPM_MM=1 \
Paul Sokolovskycf9fe862023-01-02 16:22:21 +0300725 EL3_EXCEPTION_HANDLING=1 ENABLE_SME_FOR_NS=0 ENABLE_SVE_FOR_NS=0
Zelalemd86e8762020-08-21 18:24:28 -0500726
Fathi Boudra422bf772019-12-02 11:10:16 +0200727# For hikey enable PMF to include all files in the platform port
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500728make PLAT=hikey $(common_flags) ${TBB_OPTIONS} ENABLE_PMF=1 all
729make PLAT=hikey960 $(common_flags) ${TBB_OPTIONS} all
Lukas Haneld0752392022-10-13 11:13:19 +0200730make PLAT=hikey960 $(common_flags) ${TBB_OPTIONS} SPD=spmd SPMC_AT_EL3=1 \
731 SPMD_SPM_AT_SEL2=0 BL32=optee PLAT_SP_MANIFEST_DTS=foo NEED_FDT=no all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500732make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200733
Zelalemc9531f82020-08-04 15:37:08 -0500734# Platforms from Socionext
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500735clean_build PLAT=uniphier $(common_flags) ${TBB_OPTIONS} SPD=tspd
736clean_build PLAT=uniphier $(common_flags) FIP_GZIP=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200737
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500738clean_build PLAT=synquacer $(common_flags) SPM_MM=1 \
Jassi Brar86080922022-06-27 14:16:34 -0500739 RESET_TO_BL31=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0 \
740 PRELOADED_BL33_BASE=0x0
Zelalemc9531f82020-08-04 15:37:08 -0500741
742# Support for SCP Message Interface protocol with platform specific drivers
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500743clean_build PLAT=synquacer $(common_flags) \
Jassi Brar86080922022-06-27 14:16:34 -0500744 RESET_TO_BL31=1 PRELOADED_BL33_BASE=0x0 SQ_USE_SCMI_DRIVER=1
Zelalemc9531f82020-08-04 15:37:08 -0500745
Jassi Brarb8c7ca02022-06-27 14:22:10 -0500746# Support for BL2 and TBBR
747clean_build PLAT=synquacer $(common_flags) \
748 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
749 SQ_USE_SCMI_DRIVER=1 SPD=opteed all
750
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500751make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200752
Zelalemc9531f82020-08-04 15:37:08 -0500753# Raspberry Pi Platforms
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500754make PLAT=rpi3 $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500755 ENABLE_STACK_PROTECTOR=strong PRELOADED_BL33_BASE=0xDEADBEEF all
Andre Przywarae917ec82021-09-03 15:01:30 +0100756clean_build PLAT=rpi4 $(common_flags) SMC_PCI_SUPPORT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200757
Zelalemc9531f82020-08-04 15:37:08 -0500758# A113D (AXG) platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500759clean_build PLAT=axg $(common_flags) SPD=opteed
760clean_build PLAT=axg $(common_flags) AML_USE_ATOS=1
Zelalemc9531f82020-08-04 15:37:08 -0500761
Stephan Gerhold141a7662021-12-07 20:42:14 +0100762# QTI MSM8916 platform
Stephan Gerhold3b3976f2023-04-17 16:27:11 +0200763clean_build PLAT=mdm9607 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
764 ARCH=aarch32 AARCH32_SP=sp_min
765clean_build PLAT=msm8909 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
766 ARCH=aarch32 AARCH32_SP=sp_min
Stephan Gerhold141a7662021-12-07 20:42:14 +0100767clean_build PLAT=msm8916 $(common_flags)
Manish V Badarkhec540e622023-06-28 17:56:40 +0100768clean_build PLAT=msm8916 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
769 ARCH=aarch32 AARCH32_SP=sp_min
Stephan Gerhold998f0d62023-04-17 16:22:52 +0200770clean_build PLAT=msm8916 $(common_flags) SPD=tspd
Stephan Gerhold3b3976f2023-04-17 16:27:11 +0200771clean_build PLAT=msm8939 $(common_flags)
772clean_build PLAT=msm8939 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
773 ARCH=aarch32 AARCH32_SP=sp_min
774clean_build PLAT=msm8939 $(common_flags) SPD=tspd
Stephan Gerhold141a7662021-12-07 20:42:14 +0100775
Chia-Wei Wang7dcb0d02023-06-09 09:52:52 +0800776# Platforms from Aspeed
777clean_build PLAT=ast2700 $(common_flags) SPD=opteed
778
rutigl@gmail.com86cfcf92023-03-21 10:10:11 +0200779# Nuvoton npcm845x platform
780make PLAT=npcm845x $(common_flags) all SPD=opteed
781
Harrison Mutaiee958c12023-09-06 12:16:21 +0100782if [[ "$rc" -gt 0 ]]; then
783 echo "ERROR: tc-cov-make failed with $error_count failures"
784 exit $rc
785fi
786
Fathi Boudra422bf772019-12-02 11:10:16 +0200787cd ..