Wedson Almeida Filho | 3fcbcff | 2018-07-10 23:53:39 +0100 | [diff] [blame] | 1 | #include "api.h" |
| 2 | #include "arch_api.h" |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 3 | #include "cpu.h" |
| 4 | #include "dlog.h" |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 5 | #include "vm.h" |
| 6 | |
| 7 | #include "msr.h" |
| 8 | |
| 9 | struct hvc_handler_return { |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 10 | long user_ret; |
| 11 | struct vcpu *new; |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 12 | }; |
| 13 | |
| 14 | void irq_current(void) |
| 15 | { |
| 16 | dlog("IRQ from current\n"); |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 17 | for (;;) { |
| 18 | /* do nothing */ |
| 19 | } |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 20 | } |
| 21 | |
| 22 | void sync_current_exception(uint64_t esr, uint64_t elr) |
| 23 | { |
Wedson Almeida Filho | fed6902 | 2018-07-11 15:39:12 +0100 | [diff] [blame] | 24 | switch (esr >> 26) { |
| 25 | case 0x25: /* EC = 100101, Data abort. */ |
Andrew Scull | 4f170f5 | 2018-07-19 12:58:20 +0100 | [diff] [blame] | 26 | dlog("Data abort: pc=0x%x, esr=0x%x, ec=0x%x", elr, esr, |
| 27 | esr >> 26); |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 28 | if (!(esr & (1u << 10))) { /* Check FnV bit. */ |
Andrew Scull | 4f170f5 | 2018-07-19 12:58:20 +0100 | [diff] [blame] | 29 | dlog(", far=0x%x, hpfar=0x%x", read_msr(far_el2), |
| 30 | read_msr(hpfar_el2) << 8); |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 31 | } else { |
Wedson Almeida Filho | fed6902 | 2018-07-11 15:39:12 +0100 | [diff] [blame] | 32 | dlog(", far=invalid"); |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 33 | } |
Wedson Almeida Filho | fed6902 | 2018-07-11 15:39:12 +0100 | [diff] [blame] | 34 | |
| 35 | dlog("\n"); |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 36 | for (;;) { |
| 37 | /* do nothing */ |
| 38 | } |
Wedson Almeida Filho | fed6902 | 2018-07-11 15:39:12 +0100 | [diff] [blame] | 39 | |
| 40 | default: |
Wedson Almeida Filho | 2f94ec1 | 2018-07-26 16:00:48 +0100 | [diff] [blame^] | 41 | dlog("Unknown current sync exception pc=0x%x, esr=0x%x, " |
| 42 | "ec=0x%x\n", |
| 43 | elr, esr, esr >> 26); |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 44 | for (;;) { |
| 45 | /* do nothing */ |
| 46 | } |
Wedson Almeida Filho | fed6902 | 2018-07-11 15:39:12 +0100 | [diff] [blame] | 47 | } |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 48 | for (;;) { |
| 49 | /* do nothing */ |
| 50 | } |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 51 | } |
| 52 | |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 53 | struct hvc_handler_return hvc_handler(size_t arg0, size_t arg1, size_t arg2, |
| 54 | size_t arg3) |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 55 | { |
Andrew Scull | 020ae69 | 2018-07-19 16:20:14 +0100 | [diff] [blame] | 56 | (void)arg3; |
| 57 | |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 58 | struct hvc_handler_return ret; |
| 59 | |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 60 | ret.new = NULL; |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 61 | |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 62 | switch (arg0) { |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 63 | case 0x84000000: /* PSCI_VERSION */ |
| 64 | ret.user_ret = 2; |
| 65 | break; |
| 66 | |
| 67 | case 0x84000006: /* PSCI_MIGRATE */ |
| 68 | ret.user_ret = 2; |
| 69 | break; |
| 70 | |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 71 | case HF_VM_GET_COUNT: |
Wedson Almeida Filho | 3fcbcff | 2018-07-10 23:53:39 +0100 | [diff] [blame] | 72 | ret.user_ret = api_vm_get_count(); |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 73 | break; |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 74 | |
| 75 | case HF_VCPU_GET_COUNT: |
Wedson Almeida Filho | 3fcbcff | 2018-07-10 23:53:39 +0100 | [diff] [blame] | 76 | ret.user_ret = api_vcpu_get_count(arg1); |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 77 | break; |
| 78 | |
| 79 | case HF_VCPU_RUN: |
Wedson Almeida Filho | 3fcbcff | 2018-07-10 23:53:39 +0100 | [diff] [blame] | 80 | ret.user_ret = api_vcpu_run(arg1, arg2, &ret.new); |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 81 | break; |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 82 | |
Wedson Almeida Filho | 2f94ec1 | 2018-07-26 16:00:48 +0100 | [diff] [blame^] | 83 | case HF_VM_CONFIGURE: |
| 84 | ret.user_ret = api_vm_configure(arg1, arg2); |
| 85 | break; |
| 86 | |
| 87 | case HF_RPC_REQUEST: |
| 88 | ret.user_ret = api_rpc_request(arg1, arg2); |
| 89 | break; |
| 90 | |
| 91 | case HF_RPC_READ_REQUEST: |
| 92 | ret.user_ret = api_rpc_read_request(arg1, &ret.new); |
| 93 | break; |
| 94 | |
| 95 | case HF_RPC_ACK: |
| 96 | ret.user_ret = api_rpc_ack(); |
| 97 | break; |
| 98 | |
| 99 | case HF_RPC_REPLY: |
| 100 | ret.user_ret = api_rpc_reply(arg1, arg2, &ret.new); |
| 101 | break; |
| 102 | |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 103 | default: |
| 104 | ret.user_ret = -1; |
| 105 | } |
| 106 | |
| 107 | return ret; |
| 108 | } |
| 109 | |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 110 | struct vcpu *irq_lower(void) |
| 111 | { |
| 112 | /* TODO: Only switch if we know the interrupt was not for the secondary |
| 113 | * VM. */ |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 114 | /* Switch back to primary VM, interrupts will be handled there. */ |
Wedson Almeida Filho | 2f94ec1 | 2018-07-26 16:00:48 +0100 | [diff] [blame^] | 115 | return api_switch_to_primary(HF_VCPU_YIELD, vcpu_state_ready); |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 116 | } |
| 117 | |
| 118 | struct vcpu *sync_lower_exception(uint64_t esr) |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 119 | { |
| 120 | struct cpu *c = cpu(); |
| 121 | struct vcpu *vcpu = c->current; |
| 122 | |
| 123 | switch (esr >> 26) { |
| 124 | case 0x01: /* EC = 000001, WFI or WFE. */ |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 125 | /* Check TI bit of ISS, 0 = WFI, 1 = WFE. */ |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 126 | if (esr & 1) { |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 127 | return NULL; |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 128 | } |
Wedson Almeida Filho | 3fcbcff | 2018-07-10 23:53:39 +0100 | [diff] [blame] | 129 | return api_wait_for_interrupt(); |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 130 | |
| 131 | case 0x24: /* EC = 100100, Data abort. */ |
Andrew Scull | 4f170f5 | 2018-07-19 12:58:20 +0100 | [diff] [blame] | 132 | dlog("Data abort: pc=0x%x, esr=0x%x, ec=0x%x", vcpu->regs.pc, |
| 133 | esr, esr >> 26); |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 134 | if (!(esr & (1u << 10))) { /* Check FnV bit. */ |
Andrew Scull | 4f170f5 | 2018-07-19 12:58:20 +0100 | [diff] [blame] | 135 | dlog(", far=0x%x, hpfar=0x%x", read_msr(far_el2), |
| 136 | read_msr(hpfar_el2) << 8); |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 137 | } else { |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 138 | dlog(", far=invalid"); |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 139 | } |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 140 | |
| 141 | dlog("\n"); |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 142 | for (;;) { |
| 143 | /* do nothing */ |
| 144 | } |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 145 | |
Wedson Almeida Filho | 2f94ec1 | 2018-07-26 16:00:48 +0100 | [diff] [blame^] | 146 | case 0x20: /* EC = 100000, Instruction abort. */ |
| 147 | dlog("Instruction abort: pc=0x%x, esr=0x%x, ec=0x%x", |
| 148 | vcpu->regs.pc, esr, esr >> 26); |
| 149 | if (!(esr & (1u << 10))) { /* Check FnV bit. */ |
| 150 | dlog(", far=0x%x, hpfar=0x%x", read_msr(far_el2), |
| 151 | read_msr(hpfar_el2) << 8); |
| 152 | } else { |
| 153 | dlog(", far=invalid"); |
| 154 | } |
| 155 | |
| 156 | dlog(", vttbr_el2=0x%x", read_msr(vttbr_el2)); |
| 157 | dlog("\n"); |
| 158 | for (;;) { |
| 159 | /* do nothing */ |
| 160 | } |
| 161 | |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 162 | default: |
Wedson Almeida Filho | 2f94ec1 | 2018-07-26 16:00:48 +0100 | [diff] [blame^] | 163 | dlog("Unknown lower sync exception pc=0x%x, esr=0x%x, " |
| 164 | "ec=0x%x\n", |
Andrew Scull | 4f170f5 | 2018-07-19 12:58:20 +0100 | [diff] [blame] | 165 | vcpu->regs.pc, esr, esr >> 26); |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 166 | for (;;) { |
| 167 | /* do nothing */ |
| 168 | } |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 169 | } |
| 170 | |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 171 | return NULL; |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 172 | } |