blob: 8999403fb22a4fa34ba887f138c3d3fa06302aba [file] [log] [blame]
Wedson Almeida Filho3fcbcff2018-07-10 23:53:39 +01001#include "api.h"
2#include "arch_api.h"
Wedson Almeida Filho987c0ff2018-06-20 16:34:38 +01003#include "cpu.h"
4#include "dlog.h"
Wedson Almeida Filho987c0ff2018-06-20 16:34:38 +01005#include "vm.h"
6
7#include "msr.h"
8
9struct hvc_handler_return {
Wedson Almeida Filho87009642018-07-02 10:20:07 +010010 long user_ret;
11 struct vcpu *new;
Wedson Almeida Filho987c0ff2018-06-20 16:34:38 +010012};
13
14void irq_current(void)
15{
16 dlog("IRQ from current\n");
Andrew Scull7364a8e2018-07-19 15:39:29 +010017 for (;;) {
18 /* do nothing */
19 }
Wedson Almeida Filho987c0ff2018-06-20 16:34:38 +010020}
21
22void sync_current_exception(uint64_t esr, uint64_t elr)
23{
Wedson Almeida Filhofed69022018-07-11 15:39:12 +010024 switch (esr >> 26) {
25 case 0x25: /* EC = 100101, Data abort. */
Andrew Scull4f170f52018-07-19 12:58:20 +010026 dlog("Data abort: pc=0x%x, esr=0x%x, ec=0x%x", elr, esr,
27 esr >> 26);
Andrew Scull7364a8e2018-07-19 15:39:29 +010028 if (!(esr & (1u << 10))) { /* Check FnV bit. */
Andrew Scull4f170f52018-07-19 12:58:20 +010029 dlog(", far=0x%x, hpfar=0x%x", read_msr(far_el2),
30 read_msr(hpfar_el2) << 8);
Andrew Scull7364a8e2018-07-19 15:39:29 +010031 } else {
Wedson Almeida Filhofed69022018-07-11 15:39:12 +010032 dlog(", far=invalid");
Andrew Scull7364a8e2018-07-19 15:39:29 +010033 }
Wedson Almeida Filhofed69022018-07-11 15:39:12 +010034
35 dlog("\n");
Andrew Scull7364a8e2018-07-19 15:39:29 +010036 for (;;) {
37 /* do nothing */
38 }
Wedson Almeida Filhofed69022018-07-11 15:39:12 +010039
40 default:
Andrew Scull4f170f52018-07-19 12:58:20 +010041 dlog("Unknown sync exception pc=0x%x, esr=0x%x, ec=0x%x\n", elr,
42 esr, esr >> 26);
Andrew Scull7364a8e2018-07-19 15:39:29 +010043 for (;;) {
44 /* do nothing */
45 }
Wedson Almeida Filhofed69022018-07-11 15:39:12 +010046 }
Andrew Scull7364a8e2018-07-19 15:39:29 +010047 for (;;) {
48 /* do nothing */
49 }
Wedson Almeida Filho987c0ff2018-06-20 16:34:38 +010050}
51
Wedson Almeida Filho87009642018-07-02 10:20:07 +010052struct hvc_handler_return hvc_handler(size_t arg0, size_t arg1, size_t arg2,
53 size_t arg3)
Wedson Almeida Filho987c0ff2018-06-20 16:34:38 +010054{
55 struct hvc_handler_return ret;
56
Wedson Almeida Filho87009642018-07-02 10:20:07 +010057 ret.new = NULL;
Wedson Almeida Filho987c0ff2018-06-20 16:34:38 +010058
Wedson Almeida Filho87009642018-07-02 10:20:07 +010059 switch (arg0) {
Wedson Almeida Filho987c0ff2018-06-20 16:34:38 +010060 case 0x84000000: /* PSCI_VERSION */
61 ret.user_ret = 2;
62 break;
63
64 case 0x84000006: /* PSCI_MIGRATE */
65 ret.user_ret = 2;
66 break;
67
Wedson Almeida Filho87009642018-07-02 10:20:07 +010068 case HF_VM_GET_COUNT:
Wedson Almeida Filho3fcbcff2018-07-10 23:53:39 +010069 ret.user_ret = api_vm_get_count();
Wedson Almeida Filho987c0ff2018-06-20 16:34:38 +010070 break;
Wedson Almeida Filho87009642018-07-02 10:20:07 +010071
72 case HF_VCPU_GET_COUNT:
Wedson Almeida Filho3fcbcff2018-07-10 23:53:39 +010073 ret.user_ret = api_vcpu_get_count(arg1);
Wedson Almeida Filho87009642018-07-02 10:20:07 +010074 break;
75
76 case HF_VCPU_RUN:
Wedson Almeida Filho3fcbcff2018-07-10 23:53:39 +010077 ret.user_ret = api_vcpu_run(arg1, arg2, &ret.new);
Wedson Almeida Filho87009642018-07-02 10:20:07 +010078 break;
Wedson Almeida Filho987c0ff2018-06-20 16:34:38 +010079
80 default:
81 ret.user_ret = -1;
82 }
83
84 return ret;
85}
86
Wedson Almeida Filho87009642018-07-02 10:20:07 +010087struct vcpu *irq_lower(void)
88{
89 /* TODO: Only switch if we know the interrupt was not for the secondary
90 * VM. */
91
92 /* Switch back to primary VM, interrupts will be handled there. */
93 arch_set_vm_mm(&primary_vm.page_table);
Wedson Almeida Filho3fcbcff2018-07-10 23:53:39 +010094 return &primary_vm.vcpus[cpu_index(cpu())];
Wedson Almeida Filho87009642018-07-02 10:20:07 +010095}
96
97struct vcpu *sync_lower_exception(uint64_t esr)
Wedson Almeida Filho987c0ff2018-06-20 16:34:38 +010098{
99 struct cpu *c = cpu();
100 struct vcpu *vcpu = c->current;
101
102 switch (esr >> 26) {
103 case 0x01: /* EC = 000001, WFI or WFE. */
Wedson Almeida Filho87009642018-07-02 10:20:07 +0100104 /* Check TI bit of ISS, 0 = WFI, 1 = WFE. */
Andrew Scull7364a8e2018-07-19 15:39:29 +0100105 if (esr & 1) {
Wedson Almeida Filho87009642018-07-02 10:20:07 +0100106 return NULL;
Andrew Scull7364a8e2018-07-19 15:39:29 +0100107 }
Wedson Almeida Filho3fcbcff2018-07-10 23:53:39 +0100108 return api_wait_for_interrupt();
Wedson Almeida Filho987c0ff2018-06-20 16:34:38 +0100109
110 case 0x24: /* EC = 100100, Data abort. */
Andrew Scull4f170f52018-07-19 12:58:20 +0100111 dlog("Data abort: pc=0x%x, esr=0x%x, ec=0x%x", vcpu->regs.pc,
112 esr, esr >> 26);
Andrew Scull7364a8e2018-07-19 15:39:29 +0100113 if (!(esr & (1u << 10))) { /* Check FnV bit. */
Andrew Scull4f170f52018-07-19 12:58:20 +0100114 dlog(", far=0x%x, hpfar=0x%x", read_msr(far_el2),
115 read_msr(hpfar_el2) << 8);
Andrew Scull7364a8e2018-07-19 15:39:29 +0100116 } else {
Wedson Almeida Filho987c0ff2018-06-20 16:34:38 +0100117 dlog(", far=invalid");
Andrew Scull7364a8e2018-07-19 15:39:29 +0100118 }
Wedson Almeida Filho987c0ff2018-06-20 16:34:38 +0100119
120 dlog("\n");
Andrew Scull7364a8e2018-07-19 15:39:29 +0100121 for (;;) {
122 /* do nothing */
123 }
Wedson Almeida Filho987c0ff2018-06-20 16:34:38 +0100124
125 default:
Andrew Scull4f170f52018-07-19 12:58:20 +0100126 dlog("Unknown sync exception pc=0x%x, esr=0x%x, ec=0x%x\n",
127 vcpu->regs.pc, esr, esr >> 26);
Andrew Scull7364a8e2018-07-19 15:39:29 +0100128 for (;;) {
129 /* do nothing */
130 }
Wedson Almeida Filho987c0ff2018-06-20 16:34:38 +0100131 }
132
Wedson Almeida Filho87009642018-07-02 10:20:07 +0100133 return NULL;
Wedson Almeida Filho987c0ff2018-06-20 16:34:38 +0100134}