Wedson Almeida Filho | 3fcbcff | 2018-07-10 23:53:39 +0100 | [diff] [blame] | 1 | #include "api.h" |
| 2 | #include "arch_api.h" |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 3 | #include "cpu.h" |
| 4 | #include "dlog.h" |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 5 | #include "vm.h" |
| 6 | |
| 7 | #include "msr.h" |
| 8 | |
| 9 | struct hvc_handler_return { |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 10 | long user_ret; |
| 11 | struct vcpu *new; |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 12 | }; |
| 13 | |
| 14 | void irq_current(void) |
| 15 | { |
| 16 | dlog("IRQ from current\n"); |
Andrew Scull | 4f170f5 | 2018-07-19 12:58:20 +0100 | [diff] [blame^] | 17 | for (;;) |
| 18 | ; |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 19 | } |
| 20 | |
| 21 | void sync_current_exception(uint64_t esr, uint64_t elr) |
| 22 | { |
Wedson Almeida Filho | fed6902 | 2018-07-11 15:39:12 +0100 | [diff] [blame] | 23 | switch (esr >> 26) { |
| 24 | case 0x25: /* EC = 100101, Data abort. */ |
Andrew Scull | 4f170f5 | 2018-07-19 12:58:20 +0100 | [diff] [blame^] | 25 | dlog("Data abort: pc=0x%x, esr=0x%x, ec=0x%x", elr, esr, |
| 26 | esr >> 26); |
Wedson Almeida Filho | fed6902 | 2018-07-11 15:39:12 +0100 | [diff] [blame] | 27 | if (!(esr & (1u << 10))) /* Check FnV bit. */ |
Andrew Scull | 4f170f5 | 2018-07-19 12:58:20 +0100 | [diff] [blame^] | 28 | dlog(", far=0x%x, hpfar=0x%x", read_msr(far_el2), |
| 29 | read_msr(hpfar_el2) << 8); |
Wedson Almeida Filho | fed6902 | 2018-07-11 15:39:12 +0100 | [diff] [blame] | 30 | else |
| 31 | dlog(", far=invalid"); |
| 32 | |
| 33 | dlog("\n"); |
Andrew Scull | 4f170f5 | 2018-07-19 12:58:20 +0100 | [diff] [blame^] | 34 | for (;;) |
| 35 | ; |
Wedson Almeida Filho | fed6902 | 2018-07-11 15:39:12 +0100 | [diff] [blame] | 36 | |
| 37 | default: |
Andrew Scull | 4f170f5 | 2018-07-19 12:58:20 +0100 | [diff] [blame^] | 38 | dlog("Unknown sync exception pc=0x%x, esr=0x%x, ec=0x%x\n", elr, |
| 39 | esr, esr >> 26); |
| 40 | for (;;) |
| 41 | ; |
Wedson Almeida Filho | fed6902 | 2018-07-11 15:39:12 +0100 | [diff] [blame] | 42 | } |
Andrew Scull | 4f170f5 | 2018-07-19 12:58:20 +0100 | [diff] [blame^] | 43 | for (;;) |
| 44 | ; |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 45 | } |
| 46 | |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 47 | struct hvc_handler_return hvc_handler(size_t arg0, size_t arg1, size_t arg2, |
| 48 | size_t arg3) |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 49 | { |
| 50 | struct hvc_handler_return ret; |
| 51 | |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 52 | ret.new = NULL; |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 53 | |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 54 | switch (arg0) { |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 55 | case 0x84000000: /* PSCI_VERSION */ |
| 56 | ret.user_ret = 2; |
| 57 | break; |
| 58 | |
| 59 | case 0x84000006: /* PSCI_MIGRATE */ |
| 60 | ret.user_ret = 2; |
| 61 | break; |
| 62 | |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 63 | case HF_VM_GET_COUNT: |
Wedson Almeida Filho | 3fcbcff | 2018-07-10 23:53:39 +0100 | [diff] [blame] | 64 | ret.user_ret = api_vm_get_count(); |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 65 | break; |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 66 | |
| 67 | case HF_VCPU_GET_COUNT: |
Wedson Almeida Filho | 3fcbcff | 2018-07-10 23:53:39 +0100 | [diff] [blame] | 68 | ret.user_ret = api_vcpu_get_count(arg1); |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 69 | break; |
| 70 | |
| 71 | case HF_VCPU_RUN: |
Wedson Almeida Filho | 3fcbcff | 2018-07-10 23:53:39 +0100 | [diff] [blame] | 72 | ret.user_ret = api_vcpu_run(arg1, arg2, &ret.new); |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 73 | break; |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 74 | |
| 75 | default: |
| 76 | ret.user_ret = -1; |
| 77 | } |
| 78 | |
| 79 | return ret; |
| 80 | } |
| 81 | |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 82 | struct vcpu *irq_lower(void) |
| 83 | { |
| 84 | /* TODO: Only switch if we know the interrupt was not for the secondary |
| 85 | * VM. */ |
| 86 | |
| 87 | /* Switch back to primary VM, interrupts will be handled there. */ |
| 88 | arch_set_vm_mm(&primary_vm.page_table); |
Wedson Almeida Filho | 3fcbcff | 2018-07-10 23:53:39 +0100 | [diff] [blame] | 89 | return &primary_vm.vcpus[cpu_index(cpu())]; |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 90 | } |
| 91 | |
| 92 | struct vcpu *sync_lower_exception(uint64_t esr) |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 93 | { |
| 94 | struct cpu *c = cpu(); |
| 95 | struct vcpu *vcpu = c->current; |
| 96 | |
| 97 | switch (esr >> 26) { |
| 98 | case 0x01: /* EC = 000001, WFI or WFE. */ |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 99 | /* Check TI bit of ISS, 0 = WFI, 1 = WFE. */ |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 100 | if (esr & 1) |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 101 | return NULL; |
Wedson Almeida Filho | 3fcbcff | 2018-07-10 23:53:39 +0100 | [diff] [blame] | 102 | return api_wait_for_interrupt(); |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 103 | |
| 104 | case 0x24: /* EC = 100100, Data abort. */ |
Andrew Scull | 4f170f5 | 2018-07-19 12:58:20 +0100 | [diff] [blame^] | 105 | dlog("Data abort: pc=0x%x, esr=0x%x, ec=0x%x", vcpu->regs.pc, |
| 106 | esr, esr >> 26); |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 107 | if (!(esr & (1u << 10))) /* Check FnV bit. */ |
Andrew Scull | 4f170f5 | 2018-07-19 12:58:20 +0100 | [diff] [blame^] | 108 | dlog(", far=0x%x, hpfar=0x%x", read_msr(far_el2), |
| 109 | read_msr(hpfar_el2) << 8); |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 110 | else |
| 111 | dlog(", far=invalid"); |
| 112 | |
| 113 | dlog("\n"); |
Andrew Scull | 4f170f5 | 2018-07-19 12:58:20 +0100 | [diff] [blame^] | 114 | for (;;) |
| 115 | ; |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 116 | |
| 117 | default: |
Andrew Scull | 4f170f5 | 2018-07-19 12:58:20 +0100 | [diff] [blame^] | 118 | dlog("Unknown sync exception pc=0x%x, esr=0x%x, ec=0x%x\n", |
| 119 | vcpu->regs.pc, esr, esr >> 26); |
| 120 | for (;;) |
| 121 | ; |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 122 | } |
| 123 | |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 124 | return NULL; |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 125 | } |