Wedson Almeida Filho | 3fcbcff | 2018-07-10 23:53:39 +0100 | [diff] [blame] | 1 | #include "api.h" |
| 2 | #include "arch_api.h" |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 3 | #include "cpu.h" |
| 4 | #include "dlog.h" |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 5 | #include "vm.h" |
| 6 | |
| 7 | #include "msr.h" |
| 8 | |
| 9 | struct hvc_handler_return { |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 10 | long user_ret; |
| 11 | struct vcpu *new; |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 12 | }; |
| 13 | |
| 14 | void irq_current(void) |
| 15 | { |
| 16 | dlog("IRQ from current\n"); |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 17 | for (;;) { |
| 18 | /* do nothing */ |
| 19 | } |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 20 | } |
| 21 | |
| 22 | void sync_current_exception(uint64_t esr, uint64_t elr) |
| 23 | { |
Wedson Almeida Filho | fed6902 | 2018-07-11 15:39:12 +0100 | [diff] [blame] | 24 | switch (esr >> 26) { |
| 25 | case 0x25: /* EC = 100101, Data abort. */ |
Andrew Scull | 4f170f5 | 2018-07-19 12:58:20 +0100 | [diff] [blame] | 26 | dlog("Data abort: pc=0x%x, esr=0x%x, ec=0x%x", elr, esr, |
| 27 | esr >> 26); |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 28 | if (!(esr & (1u << 10))) { /* Check FnV bit. */ |
Andrew Scull | 4f170f5 | 2018-07-19 12:58:20 +0100 | [diff] [blame] | 29 | dlog(", far=0x%x, hpfar=0x%x", read_msr(far_el2), |
| 30 | read_msr(hpfar_el2) << 8); |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 31 | } else { |
Wedson Almeida Filho | fed6902 | 2018-07-11 15:39:12 +0100 | [diff] [blame] | 32 | dlog(", far=invalid"); |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 33 | } |
Wedson Almeida Filho | fed6902 | 2018-07-11 15:39:12 +0100 | [diff] [blame] | 34 | |
| 35 | dlog("\n"); |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 36 | for (;;) { |
| 37 | /* do nothing */ |
| 38 | } |
Wedson Almeida Filho | fed6902 | 2018-07-11 15:39:12 +0100 | [diff] [blame] | 39 | |
| 40 | default: |
Andrew Scull | 4f170f5 | 2018-07-19 12:58:20 +0100 | [diff] [blame] | 41 | dlog("Unknown sync exception pc=0x%x, esr=0x%x, ec=0x%x\n", elr, |
| 42 | esr, esr >> 26); |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 43 | for (;;) { |
| 44 | /* do nothing */ |
| 45 | } |
Wedson Almeida Filho | fed6902 | 2018-07-11 15:39:12 +0100 | [diff] [blame] | 46 | } |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 47 | for (;;) { |
| 48 | /* do nothing */ |
| 49 | } |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 50 | } |
| 51 | |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 52 | struct hvc_handler_return hvc_handler(size_t arg0, size_t arg1, size_t arg2, |
| 53 | size_t arg3) |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 54 | { |
Andrew Scull | 020ae69 | 2018-07-19 16:20:14 +0100 | [diff] [blame^] | 55 | (void)arg3; |
| 56 | |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 57 | struct hvc_handler_return ret; |
| 58 | |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 59 | ret.new = NULL; |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 60 | |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 61 | switch (arg0) { |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 62 | case 0x84000000: /* PSCI_VERSION */ |
| 63 | ret.user_ret = 2; |
| 64 | break; |
| 65 | |
| 66 | case 0x84000006: /* PSCI_MIGRATE */ |
| 67 | ret.user_ret = 2; |
| 68 | break; |
| 69 | |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 70 | case HF_VM_GET_COUNT: |
Wedson Almeida Filho | 3fcbcff | 2018-07-10 23:53:39 +0100 | [diff] [blame] | 71 | ret.user_ret = api_vm_get_count(); |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 72 | break; |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 73 | |
| 74 | case HF_VCPU_GET_COUNT: |
Wedson Almeida Filho | 3fcbcff | 2018-07-10 23:53:39 +0100 | [diff] [blame] | 75 | ret.user_ret = api_vcpu_get_count(arg1); |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 76 | break; |
| 77 | |
| 78 | case HF_VCPU_RUN: |
Wedson Almeida Filho | 3fcbcff | 2018-07-10 23:53:39 +0100 | [diff] [blame] | 79 | ret.user_ret = api_vcpu_run(arg1, arg2, &ret.new); |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 80 | break; |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 81 | |
| 82 | default: |
| 83 | ret.user_ret = -1; |
| 84 | } |
| 85 | |
| 86 | return ret; |
| 87 | } |
| 88 | |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 89 | struct vcpu *irq_lower(void) |
| 90 | { |
| 91 | /* TODO: Only switch if we know the interrupt was not for the secondary |
| 92 | * VM. */ |
| 93 | |
| 94 | /* Switch back to primary VM, interrupts will be handled there. */ |
| 95 | arch_set_vm_mm(&primary_vm.page_table); |
Wedson Almeida Filho | 3fcbcff | 2018-07-10 23:53:39 +0100 | [diff] [blame] | 96 | return &primary_vm.vcpus[cpu_index(cpu())]; |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 97 | } |
| 98 | |
| 99 | struct vcpu *sync_lower_exception(uint64_t esr) |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 100 | { |
| 101 | struct cpu *c = cpu(); |
| 102 | struct vcpu *vcpu = c->current; |
| 103 | |
| 104 | switch (esr >> 26) { |
| 105 | case 0x01: /* EC = 000001, WFI or WFE. */ |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 106 | /* Check TI bit of ISS, 0 = WFI, 1 = WFE. */ |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 107 | if (esr & 1) { |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 108 | return NULL; |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 109 | } |
Wedson Almeida Filho | 3fcbcff | 2018-07-10 23:53:39 +0100 | [diff] [blame] | 110 | return api_wait_for_interrupt(); |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 111 | |
| 112 | case 0x24: /* EC = 100100, Data abort. */ |
Andrew Scull | 4f170f5 | 2018-07-19 12:58:20 +0100 | [diff] [blame] | 113 | dlog("Data abort: pc=0x%x, esr=0x%x, ec=0x%x", vcpu->regs.pc, |
| 114 | esr, esr >> 26); |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 115 | if (!(esr & (1u << 10))) { /* Check FnV bit. */ |
Andrew Scull | 4f170f5 | 2018-07-19 12:58:20 +0100 | [diff] [blame] | 116 | dlog(", far=0x%x, hpfar=0x%x", read_msr(far_el2), |
| 117 | read_msr(hpfar_el2) << 8); |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 118 | } else { |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 119 | dlog(", far=invalid"); |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 120 | } |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 121 | |
| 122 | dlog("\n"); |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 123 | for (;;) { |
| 124 | /* do nothing */ |
| 125 | } |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 126 | |
| 127 | default: |
Andrew Scull | 4f170f5 | 2018-07-19 12:58:20 +0100 | [diff] [blame] | 128 | dlog("Unknown sync exception pc=0x%x, esr=0x%x, ec=0x%x\n", |
| 129 | vcpu->regs.pc, esr, esr >> 26); |
Andrew Scull | 7364a8e | 2018-07-19 15:39:29 +0100 | [diff] [blame] | 130 | for (;;) { |
| 131 | /* do nothing */ |
| 132 | } |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 133 | } |
| 134 | |
Wedson Almeida Filho | 8700964 | 2018-07-02 10:20:07 +0100 | [diff] [blame] | 135 | return NULL; |
Wedson Almeida Filho | 987c0ff | 2018-06-20 16:34:38 +0100 | [diff] [blame] | 136 | } |