Blame - tftf/framework/aarch64/exceptions.S - TF-A/tf-a-tests.git

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Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	1	/*
				2	* Copyright (c) 2018, Arm Limited. All rights reserved.
				3	*
				4	* SPDX-License-Identifier: BSD-3-Clause
				5	*/
				6
				7	#include <asm_macros.S>
				8
				9	.globl tftf_vector
				10
				11	vector_base tftf_vector
Sandrine Bailleux	8b170a2	2019-01-11 18:47:26 +0100	[diff] [blame]	12
				13	/*
				14	* Current EL with SP0 : 0x0 - 0x200.
				15	*/
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	16	vector_entry SynchronousExceptionSP0
				17	b SynchronousExceptionSP0
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame]	18	end_vector_entry SynchronousExceptionSP0
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	19
				20	vector_entry IrqSP0
				21	b IrqSP0
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame]	22	end_vector_entry IrqSP0
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	23
				24	vector_entry FiqSP0
				25	b FiqSP0
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame]	26	end_vector_entry FiqSP0
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	27
				28	vector_entry SErrorSP0
				29	b SErrorSP0
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame]	30	end_vector_entry SErrorSP0
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	31
Sandrine Bailleux	8b170a2	2019-01-11 18:47:26 +0100	[diff] [blame]	32	/*
				33	* Current EL with SPx : 0x200 - 0x400.
				34	*/
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	35	vector_entry SynchronousExceptionSPx
				36	b SynchronousExceptionSPx
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame]	37	end_vector_entry SynchronousExceptionSPx
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	38
				39	vector_entry IrqSPx
Sandrine Bailleux	d101967	2019-01-11 18:39:24 +0100	[diff] [blame^]	40	b irq_vector_entry
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame]	41	end_vector_entry IrqSPx
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	42
				43	vector_entry FiqSPx
				44	b FiqSPx
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame]	45	end_vector_entry FiqSPx
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	46
				47	vector_entry SErrorSPx
				48	b SErrorSPx
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame]	49	end_vector_entry SErrorSPx
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	50
Sandrine Bailleux	8b170a2	2019-01-11 18:47:26 +0100	[diff] [blame]	51	/*
				52	* Lower EL using AArch64 : 0x400 - 0x600.
				53	*/
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	54	vector_entry SynchronousExceptionA64
				55	b SynchronousExceptionA64
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame]	56	end_vector_entry SynchronousExceptionA64
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	57
				58	vector_entry IrqA64
				59	b IrqA64
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame]	60	end_vector_entry IrqA64
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	61
				62	vector_entry FiqA64
				63	b FiqA64
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame]	64	end_vector_entry FiqA64
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	65
				66	vector_entry SErrorA64
				67	b SErrorA64
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame]	68	end_vector_entry SErrorA64
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	69
Sandrine Bailleux	8b170a2	2019-01-11 18:47:26 +0100	[diff] [blame]	70	/*
				71	* Lower EL using AArch32 : 0x600 - 0x800.
				72	*/
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	73	vector_entry SynchronousExceptionA32
				74	b SynchronousExceptionA32
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame]	75	end_vector_entry SynchronousExceptionA32
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	76
				77	vector_entry IrqA32
				78	b IrqA32
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame]	79	end_vector_entry IrqA32
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	80
				81	vector_entry FiqA32
				82	b FiqA32
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame]	83	end_vector_entry FiqA32
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	84
				85	vector_entry SErrorA32
				86	b SErrorA32
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame]	87	end_vector_entry SErrorA32
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	88
Sandrine Bailleux	d101967	2019-01-11 18:39:24 +0100	[diff] [blame^]	89	/*
				90	* Exceptions will always be from the same exception level so no need to save
				91	* and restore SPSR.
				92	*/
				93	.macro save_gp_regs
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	94	stp x0, x1, [sp, #0x0]
				95	stp x2, x3, [sp, #0x10]
				96	stp x4, x5, [sp, #0x20]
				97	stp x6, x7, [sp, #0x30]
				98	stp x8, x9, [sp, #0x40]
				99	stp x10, x11, [sp, #0x50]
				100	stp x12, x13, [sp, #0x60]
				101	stp x14, x15, [sp, #0x70]
				102	stp x16, x17, [sp, #0x80]
				103	stp x18, x19, [sp, #0x90]
				104	stp x20, x21, [sp, #0xa0]
				105	stp x22, x23, [sp, #0xb0]
				106	stp x24, x25, [sp, #0xc0]
				107	stp x26, x27, [sp, #0xd0]
Sandrine Bailleux	d101967	2019-01-11 18:39:24 +0100	[diff] [blame^]	108	stp x28, x29, [sp, #0xe0]
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	109	mrs x0, sp_el0
Sandrine Bailleux	d101967	2019-01-11 18:39:24 +0100	[diff] [blame^]	110	stp x30, x0, [sp, #0xf0]
				111	.endm
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	112
Sandrine Bailleux	d101967	2019-01-11 18:39:24 +0100	[diff] [blame^]	113	.macro restore_gp_regs
				114	ldp x30, x0, [sp, #0xf0]
				115	msr sp_el0, x0
				116	ldp x28, x29, [sp, #0xe0]
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	117	ldp x26, x27, [sp, #0xd0]
				118	ldp x24, x25, [sp, #0xc0]
				119	ldp x22, x23, [sp, #0xb0]
				120	ldp x20, x21, [sp, #0xa0]
				121	ldp x18, x19, [sp, #0x90]
				122	ldp x16, x17, [sp, #0x80]
				123	ldp x14, x15, [sp, #0x70]
				124	ldp x12, x13, [sp, #0x60]
				125	ldp x10, x11, [sp, #0x50]
				126	ldp x8, x9, [sp, #0x40]
				127	ldp x6, x7, [sp, #0x30]
				128	ldp x4, x5, [sp, #0x20]
				129	ldp x2, x3, [sp, #0x10]
				130	ldp x0, x1, [sp, #0x0]
Sandrine Bailleux	d101967	2019-01-11 18:39:24 +0100	[diff] [blame^]	131	.endm
				132
				133	func irq_vector_entry
				134	sub sp, sp, #0x100
				135	save_gp_regs
				136	bl tftf_irq_handler_dispatcher
				137	restore_gp_regs
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	138	add sp, sp, #0x100
Sandrine Bailleux	d101967	2019-01-11 18:39:24 +0100	[diff] [blame^]	139	eret
				140	endfunc irq_vector_entry