Blame - tftf/framework/aarch64/exceptions.S - TF-A/tf-a-tests.git

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Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	1	/*
				2	* Copyright (c) 2018, Arm Limited. All rights reserved.
				3	*
				4	* SPDX-License-Identifier: BSD-3-Clause
				5	*/
				6
				7	#include <asm_macros.S>
				8
				9	.globl tftf_vector
				10
				11	vector_base tftf_vector
Sandrine Bailleux	8b170a2	2019-01-11 18:47:26 +0100	[diff] [blame]	12
				13	/*
				14	* Current EL with SP0 : 0x0 - 0x200.
				15	*/
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	16	vector_entry SynchronousExceptionSP0
				17	b SynchronousExceptionSP0
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame^]	18	end_vector_entry SynchronousExceptionSP0
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	19
				20	vector_entry IrqSP0
				21	b IrqSP0
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame^]	22	end_vector_entry IrqSP0
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	23
				24	vector_entry FiqSP0
				25	b FiqSP0
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame^]	26	end_vector_entry FiqSP0
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	27
				28	vector_entry SErrorSP0
				29	b SErrorSP0
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame^]	30	end_vector_entry SErrorSP0
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	31
Sandrine Bailleux	8b170a2	2019-01-11 18:47:26 +0100	[diff] [blame]	32	/*
				33	* Current EL with SPx : 0x200 - 0x400.
				34	*/
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	35	vector_entry SynchronousExceptionSPx
				36	b SynchronousExceptionSPx
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame^]	37	end_vector_entry SynchronousExceptionSPx
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	38
				39	vector_entry IrqSPx
				40	/*
				41	* TODO: Investigate whether the Trusted Firmware-A code for context
				42	* save/restore could be reused
				43	*/
				44	stp x29, x30, [sp, #-0x10]!
				45	bl save_regs
				46	bl tftf_irq_handler_dispatcher
				47	bl restore_regs
				48	ldp x29, x30, [sp], #0x10
				49	eret
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame^]	50	end_vector_entry IrqSPx
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	51
				52	vector_entry FiqSPx
				53	b FiqSPx
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame^]	54	end_vector_entry FiqSPx
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	55
				56	vector_entry SErrorSPx
				57	b SErrorSPx
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame^]	58	end_vector_entry SErrorSPx
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	59
Sandrine Bailleux	8b170a2	2019-01-11 18:47:26 +0100	[diff] [blame]	60	/*
				61	* Lower EL using AArch64 : 0x400 - 0x600.
				62	*/
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	63	vector_entry SynchronousExceptionA64
				64	b SynchronousExceptionA64
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame^]	65	end_vector_entry SynchronousExceptionA64
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	66
				67	vector_entry IrqA64
				68	b IrqA64
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame^]	69	end_vector_entry IrqA64
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	70
				71	vector_entry FiqA64
				72	b FiqA64
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame^]	73	end_vector_entry FiqA64
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	74
				75	vector_entry SErrorA64
				76	b SErrorA64
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame^]	77	end_vector_entry SErrorA64
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	78
Sandrine Bailleux	8b170a2	2019-01-11 18:47:26 +0100	[diff] [blame]	79	/*
				80	* Lower EL using AArch32 : 0x600 - 0x800.
				81	*/
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	82	vector_entry SynchronousExceptionA32
				83	b SynchronousExceptionA32
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame^]	84	end_vector_entry SynchronousExceptionA32
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	85
				86	vector_entry IrqA32
				87	b IrqA32
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame^]	88	end_vector_entry IrqA32
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	89
				90	vector_entry FiqA32
				91	b FiqA32
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame^]	92	end_vector_entry FiqA32
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	93
				94	vector_entry SErrorA32
				95	b SErrorA32
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame^]	96	end_vector_entry SErrorA32
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	97
				98
				99	// Note: Exceptions will always be from the same EL, so no need to save spsr
				100	func save_regs
				101	sub sp, sp, #0x100
				102	stp x0, x1, [sp, #0x0]
				103	stp x2, x3, [sp, #0x10]
				104	stp x4, x5, [sp, #0x20]
				105	stp x6, x7, [sp, #0x30]
				106	stp x8, x9, [sp, #0x40]
				107	stp x10, x11, [sp, #0x50]
				108	stp x12, x13, [sp, #0x60]
				109	stp x14, x15, [sp, #0x70]
				110	stp x16, x17, [sp, #0x80]
				111	stp x18, x19, [sp, #0x90]
				112	stp x20, x21, [sp, #0xa0]
				113	stp x22, x23, [sp, #0xb0]
				114	stp x24, x25, [sp, #0xc0]
				115	stp x26, x27, [sp, #0xd0]
				116	mrs x0, sp_el0
				117	stp x28, x0, [sp, #0xe0]
				118	str x0, [sp, #0xf0]
				119	ret
				120	endfunc save_regs
				121
				122
				123	// Note: Exceptions will always be from the same EL, so no need to restore spsr
				124	func restore_regs
				125	ldr x9, [sp, #0xf0]
				126	ldp x28, x9, [sp, #0xe0]
				127	msr sp_el0, x9
				128	ldp x26, x27, [sp, #0xd0]
				129	ldp x24, x25, [sp, #0xc0]
				130	ldp x22, x23, [sp, #0xb0]
				131	ldp x20, x21, [sp, #0xa0]
				132	ldp x18, x19, [sp, #0x90]
				133	ldp x16, x17, [sp, #0x80]
				134	ldp x14, x15, [sp, #0x70]
				135	ldp x12, x13, [sp, #0x60]
				136	ldp x10, x11, [sp, #0x50]
				137	ldp x8, x9, [sp, #0x40]
				138	ldp x6, x7, [sp, #0x30]
				139	ldp x4, x5, [sp, #0x20]
				140	ldp x2, x3, [sp, #0x10]
				141	ldp x0, x1, [sp, #0x0]
				142	add sp, sp, #0x100
				143	ret
				144	endfunc restore_regs