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Sandrine Bailleux3cd87d72018-10-09 11:12:55 +02001/*
2 * Copyright (c) 2018, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <asm_macros.S>
8
9 .globl tftf_vector
10
11vector_base tftf_vector
12 //-----------------------------------------------------
13 // Current EL with SP0 : 0x0 - 0x180
14 //-----------------------------------------------------
15vector_entry SynchronousExceptionSP0
16 b SynchronousExceptionSP0
17 check_vector_size SynchronousExceptionSP0
18
19vector_entry IrqSP0
20 b IrqSP0
21 check_vector_size IrqSP0
22
23vector_entry FiqSP0
24 b FiqSP0
25 check_vector_size FiqSP0
26
27vector_entry SErrorSP0
28 b SErrorSP0
29 check_vector_size SErrorSP0
30
31 //-----------------------------------------------------
32 // Current EL with SPx: 0x200 - 0x380
33 //-----------------------------------------------------
34vector_entry SynchronousExceptionSPx
35 b SynchronousExceptionSPx
36 check_vector_size SynchronousExceptionSPx
37
38vector_entry IrqSPx
39 /*
40 * TODO: Investigate whether the Trusted Firmware-A code for context
41 * save/restore could be reused
42 */
43 stp x29, x30, [sp, #-0x10]!
44 bl save_regs
45 bl tftf_irq_handler_dispatcher
46 bl restore_regs
47 ldp x29, x30, [sp], #0x10
48 eret
49 check_vector_size IrqSPx
50
51vector_entry FiqSPx
52 b FiqSPx
53 check_vector_size FiqSPx
54
55vector_entry SErrorSPx
56 b SErrorSPx
57 check_vector_size SErrorSPx
58
59 //-----------------------------------------------------
60 // Lower EL using AArch64 : 0x400 - 0x580
61 //-----------------------------------------------------
62vector_entry SynchronousExceptionA64
63 b SynchronousExceptionA64
64 check_vector_size SynchronousExceptionA64
65
66vector_entry IrqA64
67 b IrqA64
68 check_vector_size IrqA64
69
70vector_entry FiqA64
71 b FiqA64
72 check_vector_size FiqA64
73
74vector_entry SErrorA64
75 b SErrorA64
76 check_vector_size SErrorA64
77
78 //-----------------------------------------------------
79 // Lower EL using AArch32 : 0x0 - 0x180
80 //-----------------------------------------------------
81vector_entry SynchronousExceptionA32
82 b SynchronousExceptionA32
83 check_vector_size SynchronousExceptionA32
84
85vector_entry IrqA32
86 b IrqA32
87 check_vector_size IrqA32
88
89vector_entry FiqA32
90 b FiqA32
91 check_vector_size FiqA32
92
93vector_entry SErrorA32
94 b SErrorA32
95 check_vector_size SErrorA32
96
97
98// Note: Exceptions will always be from the same EL, so no need to save spsr
99func save_regs
100 sub sp, sp, #0x100
101 stp x0, x1, [sp, #0x0]
102 stp x2, x3, [sp, #0x10]
103 stp x4, x5, [sp, #0x20]
104 stp x6, x7, [sp, #0x30]
105 stp x8, x9, [sp, #0x40]
106 stp x10, x11, [sp, #0x50]
107 stp x12, x13, [sp, #0x60]
108 stp x14, x15, [sp, #0x70]
109 stp x16, x17, [sp, #0x80]
110 stp x18, x19, [sp, #0x90]
111 stp x20, x21, [sp, #0xa0]
112 stp x22, x23, [sp, #0xb0]
113 stp x24, x25, [sp, #0xc0]
114 stp x26, x27, [sp, #0xd0]
115 mrs x0, sp_el0
116 stp x28, x0, [sp, #0xe0]
117 str x0, [sp, #0xf0]
118 ret
119endfunc save_regs
120
121
122// Note: Exceptions will always be from the same EL, so no need to restore spsr
123func restore_regs
124 ldr x9, [sp, #0xf0]
125 ldp x28, x9, [sp, #0xe0]
126 msr sp_el0, x9
127 ldp x26, x27, [sp, #0xd0]
128 ldp x24, x25, [sp, #0xc0]
129 ldp x22, x23, [sp, #0xb0]
130 ldp x20, x21, [sp, #0xa0]
131 ldp x18, x19, [sp, #0x90]
132 ldp x16, x17, [sp, #0x80]
133 ldp x14, x15, [sp, #0x70]
134 ldp x12, x13, [sp, #0x60]
135 ldp x10, x11, [sp, #0x50]
136 ldp x8, x9, [sp, #0x40]
137 ldp x6, x7, [sp, #0x30]
138 ldp x4, x5, [sp, #0x20]
139 ldp x2, x3, [sp, #0x10]
140 ldp x0, x1, [sp, #0x0]
141 add sp, sp, #0x100
142 ret
143endfunc restore_regs