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David Hu50711e32019-06-12 18:32:30 +08001/*
Ronald Cron312be682019-09-23 09:27:33 +02002 * Copyright (c) 2018-2020, Arm Limited. All rights reserved.
David Hu50711e32019-06-12 18:32:30 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7#ifndef __TFM_ARCH_H__
8#define __TFM_ARCH_H__
9
10/* This header file collects the architecture related operations. */
11
Ken Liu1d96c132019-12-31 15:51:30 +080012#include <stddef.h>
David Hu50711e32019-06-12 18:32:30 +080013#include <inttypes.h>
Kevin Pengbc5e5aa2019-10-16 10:55:17 +080014#include "tfm_hal_device_header.h"
David Hu50711e32019-06-12 18:32:30 +080015#include "cmsis_compiler.h"
16
Ronald Cron312be682019-09-23 09:27:33 +020017#if defined(__ARM_ARCH_8_1M_MAIN__) || \
18 defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__)
David Hu50711e32019-06-12 18:32:30 +080019#include "tfm_arch_v8m.h"
David Hu40455c92019-07-02 14:31:34 +080020#elif defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_7M__) || \
21 defined(__ARM_ARCH_7EM__)
22#include "tfm_arch_v6m_v7m.h"
David Hu50711e32019-06-12 18:32:30 +080023#else
24#error "Unsupported ARM Architecture."
25#endif
26
27#define XPSR_T32 0x01000000
28
29/* General core state context */
Ken Liu5a2b9052019-08-15 19:03:29 +080030struct tfm_state_context_t {
David Hu50711e32019-06-12 18:32:30 +080031 uint32_t r0;
32 uint32_t r1;
33 uint32_t r2;
34 uint32_t r3;
35 uint32_t r12;
Ken Liu5a2b9052019-08-15 19:03:29 +080036 uint32_t lr;
David Hu50711e32019-06-12 18:32:30 +080037 uint32_t ra;
38 uint32_t xpsr;
39};
40
Summer Qinf68f0de2020-01-14 11:31:50 +080041#define TFM_STATE_RET_VAL(ctx) (((struct tfm_state_context_t *)((ctx)->sp))->r0)
David Hu50711e32019-06-12 18:32:30 +080042
43__attribute__ ((always_inline))
44__STATIC_INLINE void tfm_arch_trigger_pendsv(void)
45{
46 SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;
47}
48
49/**
50 * \brief Get Link Register
51 * \details Returns the value of the Link Register (LR)
52 * \return LR value
53 */
TTornblomdd233d12020-11-05 11:44:28 +010054#if !defined ( __ICCARM__ )
David Hu50711e32019-06-12 18:32:30 +080055__attribute__ ((always_inline)) __STATIC_INLINE uint32_t __get_LR(void)
56{
57 register uint32_t result;
58
59 __ASM volatile ("MOV %0, LR\n" : "=r" (result));
60 return result;
61}
TTornblomdd233d12020-11-05 11:44:28 +010062#endif
David Hu50711e32019-06-12 18:32:30 +080063
64__attribute__ ((always_inline))
65__STATIC_INLINE uint32_t __get_active_exc_num(void)
66{
67 IPSR_Type IPSR;
68
69 /* if non-zero, exception is active. NOT banked S/NS */
70 IPSR.w = __get_IPSR();
71 return IPSR.b.ISR;
72}
73
74__attribute__ ((always_inline))
75__STATIC_INLINE void __set_CONTROL_SPSEL(uint32_t SPSEL)
76{
77 CONTROL_Type ctrl;
78
79 ctrl.w = __get_CONTROL();
80 ctrl.b.SPSEL = SPSEL;
81 __set_CONTROL(ctrl.w);
82 __ISB();
83}
84
85/*
86 * Initialize CPU architecture specific thread context extension
87 */
Summer Qinf68f0de2020-01-14 11:31:50 +080088void tfm_arch_init_actx(struct tfm_arch_ctx_t *p_actx,
89 uint32_t sp, uint32_t sp_limit);
David Hu50711e32019-06-12 18:32:30 +080090
David Hu4e165602019-06-12 18:38:31 +080091/*
Ken Liu50e21092020-10-14 16:42:15 +080092 * Set secure exceptions priority
David Hu4e165602019-06-12 18:38:31 +080093 */
Ken Liu50e21092020-10-14 16:42:15 +080094void tfm_arch_set_secure_exception_priorities(void);
Jamie Fox3ede9712020-09-28 23:14:54 +010095
Jamie Fox45587672020-08-17 18:31:14 +010096/**
97 * \brief Configure coprocessors
98 */
99void tfm_arch_configure_coprocessors(void);
100
Ken Liuce2692d2020-02-11 12:39:36 +0800101/*
102 * Clear float point status.
103 */
104void tfm_arch_clear_fp_status(void);
105
Summer Qinaf3b9e12020-01-13 15:56:36 +0800106void tfm_arch_init_context(struct tfm_arch_ctx_t *p_actx,
107 void *param, uintptr_t pfn,
108 uintptr_t stk_btm, uintptr_t stk_top);
David Hu50711e32019-06-12 18:32:30 +0800109#endif