| /* |
| * Copyright (c) 2018-2020, Arm Limited. All rights reserved. |
| * |
| * SPDX-License-Identifier: BSD-3-Clause |
| * |
| */ |
| #ifndef __TFM_ARCH_H__ |
| #define __TFM_ARCH_H__ |
| |
| /* This header file collects the architecture related operations. */ |
| |
| #include <stddef.h> |
| #include <inttypes.h> |
| #include "tfm_hal_device_header.h" |
| #include "cmsis_compiler.h" |
| |
| #if defined(__ARM_ARCH_8_1M_MAIN__) || \ |
| defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__) |
| #include "tfm_arch_v8m.h" |
| #elif defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_7M__) || \ |
| defined(__ARM_ARCH_7EM__) |
| #include "tfm_arch_v6m_v7m.h" |
| #else |
| #error "Unsupported ARM Architecture." |
| #endif |
| |
| #define XPSR_T32 0x01000000 |
| |
| /* General core state context */ |
| struct tfm_state_context_t { |
| uint32_t r0; |
| uint32_t r1; |
| uint32_t r2; |
| uint32_t r3; |
| uint32_t r12; |
| uint32_t lr; |
| uint32_t ra; |
| uint32_t xpsr; |
| }; |
| |
| #define TFM_STATE_RET_VAL(ctx) (((struct tfm_state_context_t *)((ctx)->sp))->r0) |
| |
| __attribute__ ((always_inline)) |
| __STATIC_INLINE void tfm_arch_trigger_pendsv(void) |
| { |
| SCB->ICSR = SCB_ICSR_PENDSVSET_Msk; |
| } |
| |
| /** |
| * \brief Get Link Register |
| * \details Returns the value of the Link Register (LR) |
| * \return LR value |
| */ |
| #if !defined ( __ICCARM__ ) |
| __attribute__ ((always_inline)) __STATIC_INLINE uint32_t __get_LR(void) |
| { |
| register uint32_t result; |
| |
| __ASM volatile ("MOV %0, LR\n" : "=r" (result)); |
| return result; |
| } |
| #endif |
| |
| __attribute__ ((always_inline)) |
| __STATIC_INLINE uint32_t __get_active_exc_num(void) |
| { |
| IPSR_Type IPSR; |
| |
| /* if non-zero, exception is active. NOT banked S/NS */ |
| IPSR.w = __get_IPSR(); |
| return IPSR.b.ISR; |
| } |
| |
| __attribute__ ((always_inline)) |
| __STATIC_INLINE void __set_CONTROL_SPSEL(uint32_t SPSEL) |
| { |
| CONTROL_Type ctrl; |
| |
| ctrl.w = __get_CONTROL(); |
| ctrl.b.SPSEL = SPSEL; |
| __set_CONTROL(ctrl.w); |
| __ISB(); |
| } |
| |
| /* |
| * Initialize CPU architecture specific thread context extension |
| */ |
| void tfm_arch_init_actx(struct tfm_arch_ctx_t *p_actx, |
| uint32_t sp, uint32_t sp_limit); |
| |
| /* |
| * Set secure exceptions priority |
| */ |
| void tfm_arch_set_secure_exception_priorities(void); |
| |
| /** |
| * \brief Configure coprocessors |
| */ |
| void tfm_arch_configure_coprocessors(void); |
| |
| /* |
| * Clear float point status. |
| */ |
| void tfm_arch_clear_fp_status(void); |
| |
| void tfm_arch_init_context(struct tfm_arch_ctx_t *p_actx, |
| void *param, uintptr_t pfn, |
| uintptr_t stk_btm, uintptr_t stk_top); |
| #endif |