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nabkah01002e5692022-10-10 12:36:46 +01001/*
AlexeiFedorovc398c8f2025-01-16 14:35:48 +00002 * Copyright (c) 2022-2025, Arm Limited. All rights reserved.
nabkah01002e5692022-10-10 12:36:46 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8#include <stdio.h>
9
Shruti Gupta9d0cfe82023-04-17 10:57:26 +010010#include <arch_features.h>
nabkah01002e5692022-10-10 12:36:46 +010011#include <debug.h>
Shruti Gupta369955a2023-04-19 18:05:56 +010012#include <fpu.h>
nabkah01002e5692022-10-10 12:36:46 +010013#include <host_realm_helper.h>
14#include <host_shared_data.h>
Shruti Gupta9d0cfe82023-04-17 10:57:26 +010015#include <pauth.h>
nabkah01002e5692022-10-10 12:36:46 +010016#include "realm_def.h"
Shruti Gupta91105082024-11-27 05:29:55 +000017#include <realm_helpers.h>
18#include <realm_psi.h>
nabkah01002e5692022-10-10 12:36:46 +010019#include <realm_rsi.h>
AlexeiFedorov2f30f102023-03-13 19:37:46 +000020#include <realm_tests.h>
Javier Almansa Sobrino7c78f7b2024-10-25 11:44:32 +010021#include <serror.h>
Shruti Guptab027f572024-01-02 22:00:29 +000022#include <sync.h>
nabkah01002e5692022-10-10 12:36:46 +010023#include <tftf_lib.h>
24
Arunachalam Ganapathy7e514f62023-08-30 13:27:36 +010025static fpu_state_t rl_fpu_state_write;
26static fpu_state_t rl_fpu_state_read;
Shruti Gupta158208e2024-11-27 10:12:41 +000027static rsi_plane_run run __aligned(PAGE_SIZE);
Javier Almansa Sobrino7c78f7b2024-10-25 11:44:32 +010028
nabkah01002e5692022-10-10 12:36:46 +010029/*
AlexeiFedorov2f30f102023-03-13 19:37:46 +000030 * This function reads sleep time in ms from shared buffer and spins PE
31 * in a loop for that time period.
nabkah01002e5692022-10-10 12:36:46 +010032 */
33static void realm_sleep_cmd(void)
34{
Shruti Gupta52b5f022023-10-12 22:02:29 +010035 uint64_t sleep = realm_shared_data_get_my_host_val(HOST_ARG1_INDEX);
nabkah01002e5692022-10-10 12:36:46 +010036
Shruti Guptaa276b202023-12-18 10:07:43 +000037 realm_printf("going to sleep for %llums\n", sleep);
nabkah01002e5692022-10-10 12:36:46 +010038 waitms(sleep);
39}
40
Shruti Gupta6bb95102023-10-02 13:21:37 +010041static void realm_loop_cmd(void)
42{
43 while (true) {
44 waitms(500);
45 }
46}
47
Shruti Gupta158208e2024-11-27 10:12:41 +000048static bool test_realm_enter_plane_n(void)
49{
50 u_register_t base, plane_index, perm_index, flags = 0U;
Shruti Gupta41434682024-12-05 14:57:48 +000051 bool ret1;
Shruti Gupta158208e2024-11-27 10:12:41 +000052
53 plane_index = realm_shared_data_get_my_host_val(HOST_ARG1_INDEX);
54 base = realm_shared_data_get_my_host_val(HOST_ARG2_INDEX);
55 perm_index = plane_index + 1U;
56
Shruti Gupta41434682024-12-05 14:57:48 +000057 ret1 = plane_common_init(plane_index, perm_index, base, &run);
58 if (!ret1) {
59 return ret1;
60 }
61
Shruti Gupta158208e2024-11-27 10:12:41 +000062 realm_printf("Entering plane %ld, ep=0x%lx run=0x%lx\n", plane_index, base, &run);
63 return realm_plane_enter(plane_index, perm_index, base, flags, &run);
64}
65
Shruti Gupta41434682024-12-05 14:57:48 +000066static bool test_realm_enter_plane_n_reg_rw(void)
67{
68 u_register_t base, plane_index, perm_index, flags = 0U;
69 u_register_t reg1, reg2, reg3, reg4, ret;
70 bool ret1;
71
72 if (realm_is_plane0()) {
73 plane_index = realm_shared_data_get_my_host_val(HOST_ARG1_INDEX);
74 base = realm_shared_data_get_my_host_val(HOST_ARG2_INDEX);
75 perm_index = plane_index + 1U;
76
77 ret1 = plane_common_init(plane_index, perm_index, base, &run);
78 if (!ret1) {
79 return ret1;
80 }
81
82 realm_printf("Entering plane %ld, ep=0x%lx run=0x%lx\n", plane_index, base, &run);
83 ret = realm_plane_enter(plane_index, perm_index, base, flags, &run);
84 if (ret) {
85 /* get return value from plane1 */
86 reg1 = realm_shared_data_get_plane_n_val(plane_index,
87 REC_IDX(read_mpidr_el1()), HOST_ARG1_INDEX);
88
89 reg2 = realm_shared_data_get_plane_n_val(plane_index,
90 REC_IDX(read_mpidr_el1()), HOST_ARG2_INDEX);
91
92 realm_printf("P0 read 0x%lx 0x%lx\n", reg1, reg2);
93
94 /* read pauth register for plane1 */
95 ret = rsi_plane_reg_read(plane_index, SYSREG_ID_apiakeylo_el1, &reg3);
96 if ((ret != RSI_SUCCESS) || (reg1 != reg3)) {
97 realm_printf("pauth register mismatch 0x%lx 0x%lx\n", reg1, reg3);
98 return false;
99 }
100
101 /* read sctlr register for plane1 */
102 ret = rsi_plane_reg_read(plane_index, SYSREG_ID_sctlr_el1, &reg4);
103 if ((ret != RSI_SUCCESS) || (reg2 != reg4)) {
104 realm_printf("sctlr register mismatch 0x%lx 0x%lx\n", reg2, reg4);
105 return false;
106 }
107
108 /* write pauth register and verify it is same after exiting plane n */
109 ret = rsi_plane_reg_write(plane_index, SYSREG_ID_apibkeylo_el1, 0xABCD);
110 if (ret != RSI_SUCCESS) {
111 realm_printf("pauth register write failed\n");
112 return false;
113 }
114
115 /* enter plane n */
116 ret = realm_plane_enter(plane_index, perm_index, base, flags, &run);
117 if (ret) {
118 /* read pauth register for plane1 */
119 ret = rsi_plane_reg_read(plane_index, SYSREG_ID_apibkeylo_el1,
120 &reg3);
121
122 if ((ret != RSI_SUCCESS) || (reg3 != 0xABCD)) {
123 realm_printf("reg mismatch after write 0x%lx\n", reg3);
124 return false;
125 }
126 }
127
128 /* read sysreg not supported by rmm, expect error */
129 ret = rsi_plane_reg_read(plane_index, SYSREG_ID_mpamidr_el1, &reg3);
130 if (ret == RSI_SUCCESS) {
131 realm_printf("reg read should have failed\n");
132 return false;
133 }
134 return true;
135 }
136 return false;
137 } else {
138 realm_printf("PN set 0x%lx 0x%lx\n", read_apiakeylo_el1(), read_sctlr_el1());
139
140 /* return pauth and sctlr back to p0 */
141 realm_shared_data_set_my_realm_val(HOST_ARG1_INDEX, read_apiakeylo_el1());
142 realm_shared_data_set_my_realm_val(HOST_ARG2_INDEX, read_sctlr_el1());
143 return true;
144 }
145}
146
nabkah01002e5692022-10-10 12:36:46 +0100147/*
148 * This function requests RSI/ABI version from RMM.
149 */
Shruti Gupta40de8ec2023-10-12 21:45:12 +0100150static bool realm_get_rsi_version(void)
nabkah01002e5692022-10-10 12:36:46 +0100151{
Shruti Gupta40de8ec2023-10-12 21:45:12 +0100152 u_register_t version = 0U;
nabkah01002e5692022-10-10 12:36:46 +0100153
Shruti Gupta40de8ec2023-10-12 21:45:12 +0100154 version = rsi_get_version(RSI_ABI_VERSION_VAL);
nabkah01002e5692022-10-10 12:36:46 +0100155 if (version == (u_register_t)SMC_UNKNOWN) {
Shruti Gupta40de8ec2023-10-12 21:45:12 +0100156 realm_printf("SMC_RSI_ABI_VERSION failed\n");
157 return false;
nabkah01002e5692022-10-10 12:36:46 +0100158 }
159
Shruti Gupta40de8ec2023-10-12 21:45:12 +0100160 realm_printf("RSI ABI version %u.%u (expected: %u.%u)\n",
nabkah01002e5692022-10-10 12:36:46 +0100161 RSI_ABI_VERSION_GET_MAJOR(version),
162 RSI_ABI_VERSION_GET_MINOR(version),
Shruti Gupta40de8ec2023-10-12 21:45:12 +0100163 RSI_ABI_VERSION_GET_MAJOR(RSI_ABI_VERSION_VAL),
164 RSI_ABI_VERSION_GET_MINOR(RSI_ABI_VERSION_VAL));
165 return true;
nabkah01002e5692022-10-10 12:36:46 +0100166}
167
Shruti Guptabb772192023-10-09 16:08:28 +0100168bool test_realm_set_ripas(void)
169{
AlexeiFedorov9a60ecb2024-08-06 16:39:00 +0100170 u_register_t ret, base, new_base, top, new_top;
Shruti Guptabb772192023-10-09 16:08:28 +0100171 rsi_ripas_respose_type response;
172 rsi_ripas_type ripas;
173
174 base = realm_shared_data_get_my_host_val(HOST_ARG1_INDEX);
175 top = realm_shared_data_get_my_host_val(HOST_ARG2_INDEX);
AlexeiFedorov9a60ecb2024-08-06 16:39:00 +0100176 realm_printf("base=0x%lx top=0x%lx\n", base, top);
177 ret = rsi_ipa_state_get(base, top, &new_top, &ripas);
Shruti Guptabb772192023-10-09 16:08:28 +0100178 if (ripas != RSI_EMPTY) {
179 return false;
180 }
181
182 ret = rsi_ipa_state_set(base, top, RSI_RAM,
AlexeiFedorov9a60ecb2024-08-06 16:39:00 +0100183 RSI_NO_CHANGE_DESTROYED, &new_base, &response);
184 if ((ret != RSI_SUCCESS) || (response != RSI_ACCEPT)) {
Shruti Guptabb772192023-10-09 16:08:28 +0100185 return false;
186 }
AlexeiFedorov9a60ecb2024-08-06 16:39:00 +0100187
Shruti Guptabb772192023-10-09 16:08:28 +0100188 while (new_base < top) {
AlexeiFedorov9a60ecb2024-08-06 16:39:00 +0100189 realm_printf("new_base=0x%lx top=0x%lx\n", new_base, top);
Shruti Guptabb772192023-10-09 16:08:28 +0100190 ret = rsi_ipa_state_set(new_base, top, RSI_RAM,
191 RSI_NO_CHANGE_DESTROYED, &new_base, &response);
AlexeiFedorov9a60ecb2024-08-06 16:39:00 +0100192 if ((ret != RSI_SUCCESS) || (response != RSI_ACCEPT)) {
Shruti Guptabb772192023-10-09 16:08:28 +0100193 realm_printf("rsi_ipa_state_set failed\n");
194 return false;
195 }
196 }
197
AlexeiFedorov9a60ecb2024-08-06 16:39:00 +0100198 /* Verify that RIAS has changed for range base-top */
199 ret = rsi_ipa_state_get(base, top, &new_top, &ripas);
200 if ((ret != RSI_SUCCESS) || (ripas != RSI_RAM) || (new_top != top)) {
201 realm_printf("rsi_ipa_state_get failed base=0x%lx top=0x%lx",
202 "new_top=0x%lx ripas=%u ret=0x%lx\n",
203 base, top, ripas);
204 return false;
Shruti Guptabb772192023-10-09 16:08:28 +0100205 }
AlexeiFedorov9a60ecb2024-08-06 16:39:00 +0100206
Shruti Guptabb772192023-10-09 16:08:28 +0100207 return true;
208}
209
Shruti Guptafef86212023-10-17 12:15:38 +0100210bool test_realm_reject_set_ripas(void)
211{
AlexeiFedorov9a60ecb2024-08-06 16:39:00 +0100212 u_register_t ret, base, top, new_base, new_top;
Shruti Guptafef86212023-10-17 12:15:38 +0100213 rsi_ripas_respose_type response;
214 rsi_ripas_type ripas;
215
216 base = realm_shared_data_get_my_host_val(HOST_ARG1_INDEX);
AlexeiFedorov9a60ecb2024-08-06 16:39:00 +0100217 top = base + PAGE_SIZE;
218 ret = rsi_ipa_state_get(base, top, &new_top, &ripas);
219 if ((ret != RSI_SUCCESS) || (ripas != RSI_EMPTY)) {
220 realm_printf("Wrong initial ripas=%u\n", ripas);
Shruti Guptafef86212023-10-17 12:15:38 +0100221 return false;
222 }
AlexeiFedorov9a60ecb2024-08-06 16:39:00 +0100223 ret = rsi_ipa_state_set(base, top, RSI_RAM,
224 RSI_NO_CHANGE_DESTROYED, &new_base, &response);
225 if ((ret == RSI_SUCCESS) && (response == RSI_REJECT)) {
226 realm_printf("rsi_ipa_state_set passed response=%u\n", response);
227 ret = rsi_ipa_state_get(base, top, &new_top, &ripas);
228 if ((ret == RSI_SUCCESS) && (ripas == RSI_EMPTY) &&
229 (new_top == top)) {
Shruti Guptafef86212023-10-17 12:15:38 +0100230 return true;
231 } else {
AlexeiFedorov9a60ecb2024-08-06 16:39:00 +0100232 realm_printf("rsi_ipa_state_get failed top=0x%lx",
233 "new_top=0x%lx ripas=%u ret=0x%lx\n",
234 ripas);
Shruti Guptafef86212023-10-17 12:15:38 +0100235 return false;
236 }
237 }
AlexeiFedorov9a60ecb2024-08-06 16:39:00 +0100238 realm_printf("rsi_ipa_state_set failed ret=0x%lx response=%u\n",
239 ret, response);
Shruti Guptafef86212023-10-17 12:15:38 +0100240 return false;
241}
242
Shruti Gupta2a5abad2024-01-17 13:48:44 +0000243bool test_realm_dit_check_cmd(void)
244{
245 if (is_armv8_4_dit_present()) {
246 write_dit(DIT_BIT);
247 realm_printf("Testing DIT=0x%lx\n", read_dit());
248 /* Test if DIT is preserved after HOST_CALL */
249 if (read_dit() == DIT_BIT) {
250 return true;
251 }
252 }
253 return false;
254}
255
Shruti Guptae68494e2023-11-06 11:04:57 +0000256static bool test_realm_instr_fetch_cmd(void)
257{
AlexeiFedorov9a60ecb2024-08-06 16:39:00 +0100258 u_register_t base, new_top;
Shruti Guptae68494e2023-11-06 11:04:57 +0000259 void (*func_ptr)(void);
260 rsi_ripas_type ripas;
261
262 base = realm_shared_data_get_my_host_val(HOST_ARG1_INDEX);
AlexeiFedorov9a60ecb2024-08-06 16:39:00 +0100263 rsi_ipa_state_get(base, base + PAGE_SIZE, &new_top, &ripas);
264 realm_printf("Initial ripas=%u\n", ripas);
265 /* Causes instruction abort */
Shruti Guptae68494e2023-11-06 11:04:57 +0000266 realm_printf("Generate Instruction Abort\n");
267 func_ptr = (void (*)(void))base;
268 func_ptr();
AlexeiFedorov9a60ecb2024-08-06 16:39:00 +0100269 /* Should not return */
Shruti Guptae68494e2023-11-06 11:04:57 +0000270 return false;
271}
272
273static bool test_realm_data_access_cmd(void)
274{
AlexeiFedorov9a60ecb2024-08-06 16:39:00 +0100275 u_register_t base, new_top;
Shruti Guptae68494e2023-11-06 11:04:57 +0000276 rsi_ripas_type ripas;
Shruti Guptae68494e2023-11-06 11:04:57 +0000277 base = realm_shared_data_get_my_host_val(HOST_ARG1_INDEX);
AlexeiFedorov9a60ecb2024-08-06 16:39:00 +0100278 rsi_ipa_state_get(base, base + PAGE_SIZE, &new_top, &ripas);
279 realm_printf("Initial ripas=%u\n", ripas);
280 /* Causes data abort */
Shruti Guptae68494e2023-11-06 11:04:57 +0000281 realm_printf("Generate Data Abort\n");
282 *((volatile uint64_t *)base);
Javier Almansa Sobrino7c78f7b2024-10-25 11:44:32 +0100283
Shruti Guptae68494e2023-11-06 11:04:57 +0000284 return false;
285}
286
Shruti Guptab027f572024-01-02 22:00:29 +0000287static bool realm_exception_handler(void)
288{
Shruti Gupta91105082024-11-27 05:29:55 +0000289 u_register_t base, far, esr, elr;
Shruti Guptab027f572024-01-02 22:00:29 +0000290
291 base = realm_shared_data_get_my_host_val(HOST_ARG1_INDEX);
292 far = read_far_el1();
293 esr = read_esr_el1();
Shruti Gupta91105082024-11-27 05:29:55 +0000294 elr = read_elr_el1();
Shruti Guptab027f572024-01-02 22:00:29 +0000295
296 if (far == base) {
AlexeiFedorov9a60ecb2024-08-06 16:39:00 +0100297 /* Return ESR to Host */
Shruti Guptab027f572024-01-02 22:00:29 +0000298 realm_shared_data_set_my_realm_val(HOST_ARG2_INDEX, esr);
299 rsi_exit_to_host(HOST_CALL_EXIT_SUCCESS_CMD);
300 }
Shruti Gupta91105082024-11-27 05:29:55 +0000301 realm_printf("Realm Abort fail incorrect FAR=0x%lx ESR=0x%lx ELR=0x%lx\n",
302 far, esr, elr);
Shruti Guptab027f572024-01-02 22:00:29 +0000303 rsi_exit_to_host(HOST_CALL_EXIT_FAILED_CMD);
304
AlexeiFedorov9a60ecb2024-08-06 16:39:00 +0100305 /* Should not return */
Shruti Guptab027f572024-01-02 22:00:29 +0000306 return false;
307}
308
Manish V Badarkhe46d02282024-11-18 16:58:37 +0000309static bool realm_serror_handler_doublefault(bool *incr_elr_elx)
Javier Almansa Sobrino7c78f7b2024-10-25 11:44:32 +0100310{
Manish V Badarkhe46d02282024-11-18 16:58:37 +0000311 *incr_elr_elx = false;
312
Javier Almansa Sobrino7c78f7b2024-10-25 11:44:32 +0100313 if ((read_sctlr2_el1() & SCTLR2_EASE_BIT) != 0UL) {
314 /* The serror exception should have been routed here */
Manish V Badarkhe46d02282024-11-18 16:58:37 +0000315 *incr_elr_elx = true;
316
Javier Almansa Sobrino7c78f7b2024-10-25 11:44:32 +0100317 return true;
318 }
319
320 rsi_exit_to_host(HOST_CALL_EXIT_FAILED_CMD);
321
322 /* Should have never get here */
323 return false;
324}
325
326static bool realm_sync_handler_doublefault(void)
327{
328 if ((read_sctlr2_el1() & SCTLR2_EASE_BIT) == 0UL) {
329 /* The sync exception should have been routed here */
330 return true;
331 }
332
333 rsi_exit_to_host(HOST_CALL_EXIT_FAILED_CMD);
334
335 /* Should have never get here */
336 return false;
337}
338
339static void test_realm_feat_doublefault2(void)
340{
341 u_register_t ease_bit = realm_shared_data_get_my_host_val(HOST_ARG2_INDEX);
342
343 unregister_custom_sync_exception_handler();
344 register_custom_sync_exception_handler(realm_sync_handler_doublefault);
345 register_custom_serror_handler(realm_serror_handler_doublefault);
346
347 if (ease_bit != 0UL) {
348 write_sctlr2_el1(read_sctlr2_el1() | SCTLR2_EASE_BIT);
349 } else {
350 write_sctlr2_el1(read_sctlr2_el1() & ~SCTLR2_EASE_BIT);
351 }
352
353 (void)test_realm_data_access_cmd();
354}
355
nabkah01002e5692022-10-10 12:36:46 +0100356/*
357 * This is the entry function for Realm payload, it first requests the shared buffer
358 * IPA address from Host using HOST_CALL/RSI, it reads the command to be executed,
359 * performs the request, and returns to Host with the execution state SUCCESS/FAILED
360 *
361 * Host in NS world requests Realm to execute certain operations using command
362 * depending on the test case the Host wants to perform.
363 */
364void realm_payload_main(void)
365{
nabkah01002e5692022-10-10 12:36:46 +0100366 bool test_succeed = false;
367
Shruti Guptab027f572024-01-02 22:00:29 +0000368 register_custom_sync_exception_handler(realm_exception_handler);
Javier Almansa Sobrino7c78f7b2024-10-25 11:44:32 +0100369
370 /* No serror handler registered by default */
371 unregister_custom_serror_handler();
372
Shruti Gupta69cae792024-11-27 04:30:00 +0000373 realm_set_shared_structure(realm_get_ns_buffer());
Javier Almansa Sobrino7c78f7b2024-10-25 11:44:32 +0100374
Shruti Gupta550e3e82023-08-16 13:20:11 +0100375 if (realm_get_my_shared_structure() != NULL) {
376 uint8_t cmd = realm_shared_data_get_my_realm_cmd();
AlexeiFedorov2f30f102023-03-13 19:37:46 +0000377
nabkah01002e5692022-10-10 12:36:46 +0100378 switch (cmd) {
379 case REALM_SLEEP_CMD:
380 realm_sleep_cmd();
381 test_succeed = true;
382 break;
Shruti Gupta6bb95102023-10-02 13:21:37 +0100383 case REALM_LOOP_CMD:
384 realm_loop_cmd();
385 test_succeed = true;
386 break;
Shruti Gupta158208e2024-11-27 10:12:41 +0000387 case REALM_ENTER_PLANE_N_CMD:
388 test_succeed = test_realm_enter_plane_n();
389 break;
Shruti Gupta41434682024-12-05 14:57:48 +0000390 case REALM_PLANE_N_REG_RW_CMD:
391 test_succeed = test_realm_enter_plane_n_reg_rw();
392 break;
Javier Almansa Sobrino82cd82e2025-01-17 17:37:42 +0000393 case REALM_MPAM_ACCESS:
394 test_succeed = test_realm_mpam_undef_abort();
395 break;
396 case REALM_MPAM_PRESENT:
397 /* FEAT_MPAM must be hidden to the Realm */
398 test_succeed = !is_feat_mpam_supported();
399 break;
Shruti Gupta24597d12023-10-02 10:40:19 +0100400 case REALM_MULTIPLE_REC_PSCI_DENIED_CMD:
401 test_succeed = test_realm_multiple_rec_psci_denied_cmd();
Shruti Guptae68494e2023-11-06 11:04:57 +0000402 break;
Shruti Guptaaffbae82023-08-22 12:51:11 +0100403 case REALM_MULTIPLE_REC_MULTIPLE_CPU_CMD:
404 test_succeed = test_realm_multiple_rec_multiple_cpu_cmd();
Shruti Gupta24597d12023-10-02 10:40:19 +0100405 break;
Javier Almansa Sobrino7c78f7b2024-10-25 11:44:32 +0100406 case REALM_FEAT_DOUBLEFAULT2_TEST:
407 test_realm_feat_doublefault2();
408 test_succeed = true;
409 break;
Shruti Guptae68494e2023-11-06 11:04:57 +0000410 case REALM_INSTR_FETCH_CMD:
411 test_succeed = test_realm_instr_fetch_cmd();
412 break;
413 case REALM_DATA_ACCESS_CMD:
414 test_succeed = test_realm_data_access_cmd();
415 break;
Shruti Gupta9d0cfe82023-04-17 10:57:26 +0100416 case REALM_PAUTH_SET_CMD:
417 test_succeed = test_realm_pauth_set_cmd();
418 break;
419 case REALM_PAUTH_CHECK_CMD:
420 test_succeed = test_realm_pauth_check_cmd();
421 break;
422 case REALM_PAUTH_FAULT:
423 test_succeed = test_realm_pauth_fault();
424 break;
Shruti Gupta2a5abad2024-01-17 13:48:44 +0000425 case REALM_DIT_CHECK_CMD:
426 test_succeed = test_realm_dit_check_cmd();
427 break;
nabkah01002e5692022-10-10 12:36:46 +0100428 case REALM_GET_RSI_VERSION:
Shruti Gupta40de8ec2023-10-12 21:45:12 +0100429 test_succeed = realm_get_rsi_version();
nabkah01002e5692022-10-10 12:36:46 +0100430 break;
AlexeiFedorov2f30f102023-03-13 19:37:46 +0000431 case REALM_PMU_CYCLE:
432 test_succeed = test_pmuv3_cycle_works_realm();
433 break;
Shruti Guptab1b37922024-01-13 21:49:04 +0000434 case REALM_PMU_COUNTER:
435 test_succeed = test_pmuv3_counter();
436 break;
AlexeiFedorov2f30f102023-03-13 19:37:46 +0000437 case REALM_PMU_EVENT:
438 test_succeed = test_pmuv3_event_works_realm();
439 break;
440 case REALM_PMU_PRESERVE:
441 test_succeed = test_pmuv3_rmm_preserves();
442 break;
AlexeiFedorovc398c8f2025-01-16 14:35:48 +0000443 case REALM_PMU_CYCLE_INTERRUPT:
444 test_succeed = test_pmuv3_overflow_interrupt(true);
445 break;
446 case REALM_PMU_EVENT_INTERRUPT:
447 test_succeed = test_pmuv3_overflow_interrupt(false);
AlexeiFedorov2f30f102023-03-13 19:37:46 +0000448 break;
Shruti Gupta369955a2023-04-19 18:05:56 +0100449 case REALM_REQ_FPU_FILL_CMD:
Arunachalam Ganapathy7e514f62023-08-30 13:27:36 +0100450 fpu_state_write_rand(&rl_fpu_state_write);
Shruti Gupta369955a2023-04-19 18:05:56 +0100451 test_succeed = true;
452 break;
453 case REALM_REQ_FPU_CMP_CMD:
Arunachalam Ganapathy7e514f62023-08-30 13:27:36 +0100454 fpu_state_read(&rl_fpu_state_read);
455 test_succeed = !fpu_state_compare(&rl_fpu_state_write,
456 &rl_fpu_state_read);
Arunachalam Ganapathy9af432e2023-06-02 17:18:23 +0100457 break;
Shruti Guptafef86212023-10-17 12:15:38 +0100458 case REALM_REJECT_SET_RIPAS_CMD:
459 test_succeed = test_realm_reject_set_ripas();
460 break;
Shruti Guptabb772192023-10-09 16:08:28 +0100461 case REALM_SET_RIPAS_CMD:
462 test_succeed = test_realm_set_ripas();
463 break;
Arunachalam Ganapathy0bbdc2d2023-04-05 15:30:18 +0100464 case REALM_SVE_RDVL:
465 test_succeed = test_realm_sve_rdvl();
466 break;
467 case REALM_SVE_ID_REGISTERS:
468 test_succeed = test_realm_sve_read_id_registers();
469 break;
470 case REALM_SVE_PROBE_VL:
471 test_succeed = test_realm_sve_probe_vl();
Shruti Gupta369955a2023-04-19 18:05:56 +0100472 break;
Arunachalam Ganapathyc1136a82023-04-12 15:24:44 +0100473 case REALM_SVE_OPS:
474 test_succeed = test_realm_sve_ops();
475 break;
Arunachalam Ganapathy5270d012023-04-19 14:53:42 +0100476 case REALM_SVE_FILL_REGS:
477 test_succeed = test_realm_sve_fill_regs();
478 break;
Arunachalam Ganapathyf3697172023-09-04 15:04:46 +0100479 case REALM_SVE_CMP_REGS:
480 test_succeed = test_realm_sve_cmp_regs();
481 break;
Arunachalam Ganapathy73949a22023-06-05 12:01:05 +0100482 case REALM_SVE_UNDEF_ABORT:
483 test_succeed = test_realm_sve_undef_abort();
484 break;
Arunachalam Ganapathy1768e592023-05-23 13:28:38 +0100485 case REALM_SME_ID_REGISTERS:
486 test_succeed = test_realm_sme_read_id_registers();
487 break;
488 case REALM_SME_UNDEF_ABORT:
489 test_succeed = test_realm_sme_undef_abort();
490 break;
Juan Pablo Conde88ffad22024-10-11 21:22:29 -0500491 case REALM_ATTESTATION:
492 test_succeed = test_realm_attestation();
493 break;
494 case REALM_ATTESTATION_FAULT:
495 test_succeed = test_realm_attestation_fault();
496 break;
Sona Mathewc8f5a2e2025-02-04 15:22:01 -0600497 case REALM_WRITE_BRBCR_EL1:
498 test_succeed = test_realm_write_brbcr_el1_reg();
499 break;
nabkah01002e5692022-10-10 12:36:46 +0100500 default:
AlexeiFedorov2f30f102023-03-13 19:37:46 +0000501 realm_printf("%s() invalid cmd %u\n", __func__, cmd);
nabkah01002e5692022-10-10 12:36:46 +0100502 break;
503 }
504 }
505
506 if (test_succeed) {
Shruti Gupta91105082024-11-27 05:29:55 +0000507 if (realm_is_plane0()) {
508 rsi_exit_to_host(HOST_CALL_EXIT_SUCCESS_CMD);
509 } else {
510 psi_exit_to_plane0(PSI_CALL_EXIT_SUCCESS_CMD,
511 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL);
512 }
nabkah01002e5692022-10-10 12:36:46 +0100513 } else {
Shruti Gupta91105082024-11-27 05:29:55 +0000514 if (realm_is_plane0()) {
515 rsi_exit_to_host(HOST_CALL_EXIT_FAILED_CMD);
516 } else {
517 psi_exit_to_plane0(PSI_CALL_EXIT_FAILED_CMD,
518 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL);
519 }
nabkah01002e5692022-10-10 12:36:46 +0100520 }
521}