fix(realm): fix realm PMU tests
- FEATURE_PMU_NUM_CTRS field in feature_flag was used
to pass number of PMU event counters in realm creation.
The width of this field was set to 4, which was not
enough to pass numbers > 15 and was causing PMU tests
failures in FVP configuration with more than 15 event
counters implemented.
- This patch removes all FEATURE_XXX macros for setting
feature_flag and replaces them with the corresponding
RMI_FEATURE_REGISTER_0_XXX to match feature register 0.
- In host_set_pmu_state() function was setting PMSELR_EL0
to incorrect value 0 instead of 31 to select PMU cycle
counter for configurations with no event counters implemented.
- Test host_realm_pmuv3_mul_rec() was running incorrectly
with number of event counters set to 0 or 31.
- Reads and writes of PMXEVCNTR_EL0 and PMXEVTYPER_EL0
can be constrained unpredictable depending on the
value of PMSELR_EL0.SEL and number of accessible event
counters. See corresponding TF-RMM patch
https://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/34573
This patch fixes host_set_pmu_state() and
host_check_pmu_state() functions to avoid unpredictable access
to these registers.
This patch makes Realm PMU tests pass for all possible FVP
configurations clusterN.pmu-num_counters=[0...31].
Change-Id: I07cc0c14d5705338cb946ddbeddf4c2bad93abe8
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
diff --git a/realm/realm_payload_main.c b/realm/realm_payload_main.c
index aeadb9e..5bc1ef4 100644
--- a/realm/realm_payload_main.c
+++ b/realm/realm_payload_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -433,8 +433,11 @@
case REALM_PMU_PRESERVE:
test_succeed = test_pmuv3_rmm_preserves();
break;
- case REALM_PMU_INTERRUPT:
- test_succeed = test_pmuv3_overflow_interrupt();
+ case REALM_PMU_CYCLE_INTERRUPT:
+ test_succeed = test_pmuv3_overflow_interrupt(true);
+ break;
+ case REALM_PMU_EVENT_INTERRUPT:
+ test_succeed = test_pmuv3_overflow_interrupt(false);
break;
case REALM_REQ_FPU_FILL_CMD:
fpu_state_write_rand(&rl_fpu_state_write);