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Andrew Scull5e1ddfa2018-08-14 10:06:54 +01001//===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
2//
Andrew Walbran16937d02019-10-22 13:54:20 +01003// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Andrew Scull5e1ddfa2018-08-14 10:06:54 +01006//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the TargetMachine and LLVMTargetMachine classes.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_TARGET_TARGETMACHINE_H
14#define LLVM_TARGET_TARGETMACHINE_H
15
16#include "llvm/ADT/StringRef.h"
17#include "llvm/ADT/Triple.h"
18#include "llvm/IR/DataLayout.h"
19#include "llvm/Pass.h"
20#include "llvm/Support/CodeGen.h"
21#include "llvm/Target/TargetOptions.h"
22#include <string>
23
24namespace llvm {
25
26class Function;
27class GlobalValue;
28class MachineModuleInfo;
29class Mangler;
30class MCAsmInfo;
31class MCContext;
32class MCInstrInfo;
33class MCRegisterInfo;
34class MCSubtargetInfo;
35class MCSymbol;
36class raw_pwrite_stream;
37class PassManagerBuilder;
38class Target;
39class TargetIntrinsicInfo;
40class TargetIRAnalysis;
41class TargetTransformInfo;
42class TargetLoweringObjectFile;
43class TargetPassConfig;
44class TargetSubtargetInfo;
45
46// The old pass manager infrastructure is hidden in a legacy namespace now.
47namespace legacy {
48class PassManagerBase;
49}
50using legacy::PassManagerBase;
51
52//===----------------------------------------------------------------------===//
53///
54/// Primary interface to the complete machine description for the target
55/// machine. All target-specific information should be accessible through this
56/// interface.
57///
58class TargetMachine {
59protected: // Can only create subclasses.
60 TargetMachine(const Target &T, StringRef DataLayoutString,
61 const Triple &TargetTriple, StringRef CPU, StringRef FS,
62 const TargetOptions &Options);
63
64 /// The Target that this machine was created for.
65 const Target &TheTarget;
66
67 /// DataLayout for the target: keep ABI type size and alignment.
68 ///
69 /// The DataLayout is created based on the string representation provided
70 /// during construction. It is kept here only to avoid reparsing the string
71 /// but should not really be used during compilation, because it has an
72 /// internal cache that is context specific.
73 const DataLayout DL;
74
75 /// Triple string, CPU name, and target feature strings the TargetMachine
76 /// instance is created with.
77 Triple TargetTriple;
78 std::string TargetCPU;
79 std::string TargetFS;
80
81 Reloc::Model RM = Reloc::Static;
82 CodeModel::Model CMModel = CodeModel::Small;
83 CodeGenOpt::Level OptLevel = CodeGenOpt::Default;
84
85 /// Contains target specific asm information.
Andrew Scull0372a572018-11-16 15:47:06 +000086 std::unique_ptr<const MCAsmInfo> AsmInfo;
87 std::unique_ptr<const MCRegisterInfo> MRI;
88 std::unique_ptr<const MCInstrInfo> MII;
89 std::unique_ptr<const MCSubtargetInfo> STI;
Andrew Scull5e1ddfa2018-08-14 10:06:54 +010090
91 unsigned RequireStructuredCFG : 1;
92 unsigned O0WantsFastISel : 1;
93
94public:
95 const TargetOptions DefaultOptions;
96 mutable TargetOptions Options;
97
98 TargetMachine(const TargetMachine &) = delete;
99 void operator=(const TargetMachine &) = delete;
100 virtual ~TargetMachine();
101
102 const Target &getTarget() const { return TheTarget; }
103
104 const Triple &getTargetTriple() const { return TargetTriple; }
105 StringRef getTargetCPU() const { return TargetCPU; }
106 StringRef getTargetFeatureString() const { return TargetFS; }
107
108 /// Virtual method implemented by subclasses that returns a reference to that
109 /// target's TargetSubtargetInfo-derived member variable.
110 virtual const TargetSubtargetInfo *getSubtargetImpl(const Function &) const {
111 return nullptr;
112 }
113 virtual TargetLoweringObjectFile *getObjFileLowering() const {
114 return nullptr;
115 }
116
117 /// This method returns a pointer to the specified type of
118 /// TargetSubtargetInfo. In debug builds, it verifies that the object being
119 /// returned is of the correct type.
120 template <typename STC> const STC &getSubtarget(const Function &F) const {
121 return *static_cast<const STC*>(getSubtargetImpl(F));
122 }
123
124 /// Create a DataLayout.
125 const DataLayout createDataLayout() const { return DL; }
126
127 /// Test if a DataLayout if compatible with the CodeGen for this target.
128 ///
129 /// The LLVM Module owns a DataLayout that is used for the target independent
130 /// optimizations and code generation. This hook provides a target specific
131 /// check on the validity of this DataLayout.
132 bool isCompatibleDataLayout(const DataLayout &Candidate) const {
133 return DL == Candidate;
134 }
135
136 /// Get the pointer size for this target.
137 ///
138 /// This is the only time the DataLayout in the TargetMachine is used.
139 unsigned getPointerSize(unsigned AS) const {
140 return DL.getPointerSize(AS);
141 }
142
143 unsigned getPointerSizeInBits(unsigned AS) const {
144 return DL.getPointerSizeInBits(AS);
145 }
146
147 unsigned getProgramPointerSize() const {
148 return DL.getPointerSize(DL.getProgramAddressSpace());
149 }
150
151 unsigned getAllocaPointerSize() const {
152 return DL.getPointerSize(DL.getAllocaAddrSpace());
153 }
154
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100155 /// Reset the target options based on the function's attributes.
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100156 // FIXME: Remove TargetOptions that affect per-function code generation
157 // from TargetMachine.
158 void resetTargetOptions(const Function &F) const;
159
160 /// Return target specific asm information.
Andrew Scull0372a572018-11-16 15:47:06 +0000161 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo.get(); }
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100162
Andrew Scull0372a572018-11-16 15:47:06 +0000163 const MCRegisterInfo *getMCRegisterInfo() const { return MRI.get(); }
164 const MCInstrInfo *getMCInstrInfo() const { return MII.get(); }
165 const MCSubtargetInfo *getMCSubtargetInfo() const { return STI.get(); }
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100166
167 /// If intrinsic information is available, return it. If not, return null.
168 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const {
169 return nullptr;
170 }
171
172 bool requiresStructuredCFG() const { return RequireStructuredCFG; }
173 void setRequiresStructuredCFG(bool Value) { RequireStructuredCFG = Value; }
174
175 /// Returns the code generation relocation model. The choices are static, PIC,
176 /// and dynamic-no-pic, and target default.
177 Reloc::Model getRelocationModel() const;
178
179 /// Returns the code model. The choices are small, kernel, medium, large, and
180 /// target default.
181 CodeModel::Model getCodeModel() const;
182
183 bool isPositionIndependent() const;
184
185 bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const;
186
187 /// Returns true if this target uses emulated TLS.
188 bool useEmulatedTLS() const;
189
190 /// Returns the TLS model which should be used for the given global variable.
191 TLSModel::Model getTLSModel(const GlobalValue *GV) const;
192
193 /// Returns the optimization level: None, Less, Default, or Aggressive.
194 CodeGenOpt::Level getOptLevel() const;
195
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100196 /// Overrides the optimization level.
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100197 void setOptLevel(CodeGenOpt::Level Level);
198
199 void setFastISel(bool Enable) { Options.EnableFastISel = Enable; }
200 bool getO0WantsFastISel() { return O0WantsFastISel; }
201 void setO0WantsFastISel(bool Enable) { O0WantsFastISel = Enable; }
202 void setGlobalISel(bool Enable) { Options.EnableGlobalISel = Enable; }
Andrew Walbran16937d02019-10-22 13:54:20 +0100203 void setGlobalISelAbort(GlobalISelAbortMode Mode) {
204 Options.GlobalISelAbort = Mode;
205 }
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100206 void setMachineOutliner(bool Enable) {
207 Options.EnableMachineOutliner = Enable;
208 }
209 void setSupportsDefaultOutlining(bool Enable) {
210 Options.SupportsDefaultOutlining = Enable;
211 }
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100212
213 bool shouldPrintMachineCode() const { return Options.PrintMachineCode; }
214
215 bool getUniqueSectionNames() const { return Options.UniqueSectionNames; }
216
217 /// Return true if data objects should be emitted into their own section,
218 /// corresponds to -fdata-sections.
219 bool getDataSections() const {
220 return Options.DataSections;
221 }
222
223 /// Return true if functions should be emitted into their own section,
224 /// corresponding to -ffunction-sections.
225 bool getFunctionSections() const {
226 return Options.FunctionSections;
227 }
228
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100229 /// Get a \c TargetIRAnalysis appropriate for the target.
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100230 ///
231 /// This is used to construct the new pass manager's target IR analysis pass,
232 /// set up appropriately for this target machine. Even the old pass manager
233 /// uses this to answer queries about the IR.
234 TargetIRAnalysis getTargetIRAnalysis();
235
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100236 /// Return a TargetTransformInfo for a given function.
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100237 ///
238 /// The returned TargetTransformInfo is specialized to the subtarget
239 /// corresponding to \p F.
240 virtual TargetTransformInfo getTargetTransformInfo(const Function &F);
241
242 /// Allow the target to modify the pass manager, e.g. by calling
243 /// PassManagerBuilder::addExtension.
244 virtual void adjustPassManager(PassManagerBuilder &) {}
245
246 /// These enums are meant to be passed into addPassesToEmitFile to indicate
247 /// what type of file to emit, and returned by it to indicate what type of
248 /// file could actually be made.
249 enum CodeGenFileType {
250 CGFT_AssemblyFile,
251 CGFT_ObjectFile,
252 CGFT_Null // Do not emit any output.
253 };
254
255 /// Add passes to the specified pass manager to get the specified file
256 /// emitted. Typically this will involve several steps of code generation.
257 /// This method should return true if emission of this file type is not
258 /// supported, or false on success.
259 /// \p MMI is an optional parameter that, if set to non-nullptr,
260 /// will be used to set the MachineModuloInfo for this PM.
261 virtual bool addPassesToEmitFile(PassManagerBase &, raw_pwrite_stream &,
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100262 raw_pwrite_stream *, CodeGenFileType,
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100263 bool /*DisableVerify*/ = true,
264 MachineModuleInfo *MMI = nullptr) {
265 return true;
266 }
267
268 /// Add passes to the specified pass manager to get machine code emitted with
269 /// the MCJIT. This method returns true if machine code is not supported. It
270 /// fills the MCContext Ctx pointer which can be used to build custom
271 /// MCStreamer.
272 ///
273 virtual bool addPassesToEmitMC(PassManagerBase &, MCContext *&,
274 raw_pwrite_stream &,
275 bool /*DisableVerify*/ = true) {
276 return true;
277 }
278
279 /// True if subtarget inserts the final scheduling pass on its own.
280 ///
281 /// Branch relaxation, which must happen after block placement, can
282 /// on some targets (e.g. SystemZ) expose additional post-RA
283 /// scheduling opportunities.
284 virtual bool targetSchedulesPostRAScheduling() const { return false; };
285
286 void getNameWithPrefix(SmallVectorImpl<char> &Name, const GlobalValue *GV,
287 Mangler &Mang, bool MayAlwaysUsePrivate = false) const;
288 MCSymbol *getSymbol(const GlobalValue *GV) const;
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100289};
290
291/// This class describes a target machine that is implemented with the LLVM
292/// target-independent code generator.
293///
294class LLVMTargetMachine : public TargetMachine {
295protected: // Can only create subclasses.
296 LLVMTargetMachine(const Target &T, StringRef DataLayoutString,
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100297 const Triple &TT, StringRef CPU, StringRef FS,
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100298 const TargetOptions &Options, Reloc::Model RM,
299 CodeModel::Model CM, CodeGenOpt::Level OL);
300
301 void initAsmInfo();
302
303public:
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100304 /// Get a TargetTransformInfo implementation for the target.
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100305 ///
306 /// The TTI returned uses the common code generator to answer queries about
307 /// the IR.
308 TargetTransformInfo getTargetTransformInfo(const Function &F) override;
309
310 /// Create a pass configuration object to be used by addPassToEmitX methods
311 /// for generating a pipeline of CodeGen passes.
312 virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
313
314 /// Add passes to the specified pass manager to get the specified file
315 /// emitted. Typically this will involve several steps of code generation.
316 /// \p MMI is an optional parameter that, if set to non-nullptr,
317 /// will be used to set the MachineModuloInfofor this PM.
318 bool addPassesToEmitFile(PassManagerBase &PM, raw_pwrite_stream &Out,
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100319 raw_pwrite_stream *DwoOut, CodeGenFileType FileType,
320 bool DisableVerify = true,
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100321 MachineModuleInfo *MMI = nullptr) override;
322
323 /// Add passes to the specified pass manager to get machine code emitted with
324 /// the MCJIT. This method returns true if machine code is not supported. It
325 /// fills the MCContext Ctx pointer which can be used to build custom
326 /// MCStreamer.
327 bool addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx,
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100328 raw_pwrite_stream &Out,
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100329 bool DisableVerify = true) override;
330
331 /// Returns true if the target is expected to pass all machine verifier
332 /// checks. This is a stopgap measure to fix targets one by one. We will
333 /// remove this at some point and always enable the verifier when
334 /// EXPENSIVE_CHECKS is enabled.
335 virtual bool isMachineVerifierClean() const { return true; }
336
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100337 /// Adds an AsmPrinter pass to the pipeline that prints assembly or
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100338 /// machine code from the MI representation.
339 bool addAsmPrinter(PassManagerBase &PM, raw_pwrite_stream &Out,
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100340 raw_pwrite_stream *DwoOut, CodeGenFileType FileTYpe,
341 MCContext &Context);
Andrew Walbran16937d02019-10-22 13:54:20 +0100342
343 /// True if the target uses physical regs at Prolog/Epilog insertion
344 /// time. If true (most machines), all vregs must be allocated before
345 /// PEI. If false (virtual-register machines), then callee-save register
346 /// spilling and scavenging are not needed or used.
347 virtual bool usesPhysRegsForPEI() const { return true; }
348
349 /// True if the target wants to use interprocedural register allocation by
350 /// default. The -enable-ipra flag can be used to override this.
351 virtual bool useIPRA() const {
352 return false;
353 }
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100354};
355
Andrew Walbran16937d02019-10-22 13:54:20 +0100356/// Helper method for getting the code model, returning Default if
357/// CM does not have a value. The tiny and kernel models will produce
358/// an error, so targets that support them or require more complex codemodel
359/// selection logic should implement and call their own getEffectiveCodeModel.
360inline CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM,
361 CodeModel::Model Default) {
362 if (CM) {
363 // By default, targets do not support the tiny and kernel models.
364 if (*CM == CodeModel::Tiny)
365 report_fatal_error("Target does not support the tiny CodeModel");
366 if (*CM == CodeModel::Kernel)
367 report_fatal_error("Target does not support the kernel CodeModel");
368 return *CM;
369 }
370 return Default;
371}
372
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100373} // end namespace llvm
374
375#endif // LLVM_TARGET_TARGETMACHINE_H