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review.trustedfirmware.org / hafnium / prebuilts / 16937d08ad8cc9225fd54b0caa282c84bc523947 / . / linux-x64 / clang / include / llvm / IR / IntrinsicsARM.td
blob: 229c20abaf77941044e628650877697592a5e6b5 [file] [log] [blame]
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100[diff] [blame]1//===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
2//
Andrew Walbran16937d02019-10-22 13:54:20 +0100[diff] [blame^]3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100[diff] [blame]6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines all of the ARM-specific intrinsics.
10//
11//===----------------------------------------------------------------------===//
12
13
14//===----------------------------------------------------------------------===//
15// TLS
16
17let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
18
19// A space-consuming intrinsic primarily for testing ARMConstantIslands. The
20// first argument is the number of bytes this "instruction" takes up, the second
21// and return value are essentially chains, used to force ordering during ISel.
22def int_arm_space : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
23
24// 16-bit multiplications
25def int_arm_smulbb : GCCBuiltin<"__builtin_arm_smulbb">,
26 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
27def int_arm_smulbt : GCCBuiltin<"__builtin_arm_smulbt">,
28 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
29def int_arm_smultb : GCCBuiltin<"__builtin_arm_smultb">,
30 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
31def int_arm_smultt : GCCBuiltin<"__builtin_arm_smultt">,
32 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
33def int_arm_smulwb : GCCBuiltin<"__builtin_arm_smulwb">,
34 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
35def int_arm_smulwt : GCCBuiltin<"__builtin_arm_smulwt">,
36 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
37
38//===----------------------------------------------------------------------===//
39// Saturating Arithmetic
40
41def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
42 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
43 [Commutative, IntrNoMem]>;
44def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
45 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
46def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
47 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
48def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
49 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
50
51// Accumulating multiplications
52def int_arm_smlabb : GCCBuiltin<"__builtin_arm_smlabb">,
53 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
54 [IntrNoMem]>;
55def int_arm_smlabt : GCCBuiltin<"__builtin_arm_smlabt">,
56 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
57 [IntrNoMem]>;
58def int_arm_smlatb : GCCBuiltin<"__builtin_arm_smlatb">,
59 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
60 [IntrNoMem]>;
61def int_arm_smlatt : GCCBuiltin<"__builtin_arm_smlatt">,
62 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
63 [IntrNoMem]>;
64def int_arm_smlawb : GCCBuiltin<"__builtin_arm_smlawb">,
65 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
66 [IntrNoMem]>;
67def int_arm_smlawt : GCCBuiltin<"__builtin_arm_smlawt">,
68 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
69 [IntrNoMem]>;
70
71// Parallel 16-bit saturation
72def int_arm_ssat16 : GCCBuiltin<"__builtin_arm_ssat16">,
73 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
74def int_arm_usat16 : GCCBuiltin<"__builtin_arm_usat16">,
75 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
76
77// Packing and unpacking
78def int_arm_sxtab16 : GCCBuiltin<"__builtin_arm_sxtab16">,
79 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
80def int_arm_sxtb16 : GCCBuiltin<"__builtin_arm_sxtb16">,
81 Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
82def int_arm_uxtab16 : GCCBuiltin<"__builtin_arm_uxtab16">,
83 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
84def int_arm_uxtb16 : GCCBuiltin<"__builtin_arm_uxtb16">,
85 Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
86
87// Parallel selection, reads the GE flags.
88def int_arm_sel : GCCBuiltin<"__builtin_arm_sel">,
89 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrReadMem]>;
90
91// Parallel 8-bit addition and subtraction
92def int_arm_qadd8 : GCCBuiltin<"__builtin_arm_qadd8">,
93 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
94def int_arm_qsub8 : GCCBuiltin<"__builtin_arm_qsub8">,
95 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
96// Writes to the GE bits.
97def int_arm_sadd8 : GCCBuiltin<"__builtin_arm_sadd8">,
98 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
99def int_arm_shadd8 : GCCBuiltin<"__builtin_arm_shadd8">,
100 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
101def int_arm_shsub8 : GCCBuiltin<"__builtin_arm_shsub8">,
102 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
103// Writes to the GE bits.
104def int_arm_ssub8 : GCCBuiltin<"__builtin_arm_ssub8">,
105 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
106// Writes to the GE bits.
107def int_arm_uadd8 : GCCBuiltin<"__builtin_arm_uadd8">,
108 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
109def int_arm_uhadd8 : GCCBuiltin<"__builtin_arm_uhadd8">,
110 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
111def int_arm_uhsub8 : GCCBuiltin<"__builtin_arm_uhsub8">,
112 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
113def int_arm_uqadd8 : GCCBuiltin<"__builtin_arm_uqadd8">,
114 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
115def int_arm_uqsub8 : GCCBuiltin<"__builtin_arm_uqsub8">,
116 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
117// Writes to the GE bits.
118def int_arm_usub8 : GCCBuiltin<"__builtin_arm_usub8">,
119 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
120
121// Sum of 8-bit absolute differences
122def int_arm_usad8 : GCCBuiltin<"__builtin_arm_usad8">,
123 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
124def int_arm_usada8 : GCCBuiltin<"__builtin_arm_usada8">,
125 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
126 [IntrNoMem]>;
127
128// Parallel 16-bit addition and subtraction
129def int_arm_qadd16 : GCCBuiltin<"__builtin_arm_qadd16">,
130 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
131def int_arm_qasx : GCCBuiltin<"__builtin_arm_qasx">,
132 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
133def int_arm_qsax : GCCBuiltin<"__builtin_arm_qsax">,
134 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
135def int_arm_qsub16 : GCCBuiltin<"__builtin_arm_qsub16">,
136 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
137// Writes to the GE bits.
138def int_arm_sadd16 : GCCBuiltin<"__builtin_arm_sadd16">,
139 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
140// Writes to the GE bits.
141def int_arm_sasx : GCCBuiltin<"__builtin_arm_sasx">,
142 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
143def int_arm_shadd16 : GCCBuiltin<"__builtin_arm_shadd16">,
144 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
145def int_arm_shasx : GCCBuiltin<"__builtin_arm_shasx">,
146 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
147def int_arm_shsax : GCCBuiltin<"__builtin_arm_shsax">,
148 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
149def int_arm_shsub16 : GCCBuiltin<"__builtin_arm_shsub16">,
150 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
151// Writes to the GE bits.
152def int_arm_ssax : GCCBuiltin<"__builtin_arm_ssax">,
153 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
154// Writes to the GE bits.
155def int_arm_ssub16 : GCCBuiltin<"__builtin_arm_ssub16">,
156 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
157// Writes to the GE bits.
158def int_arm_uadd16 : GCCBuiltin<"__builtin_arm_uadd16">,
159 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
160// Writes to the GE bits.
161def int_arm_uasx : GCCBuiltin<"__builtin_arm_uasx">,
162 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
163def int_arm_uhadd16 : GCCBuiltin<"__builtin_arm_uhadd16">,
164 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
165def int_arm_uhasx : GCCBuiltin<"__builtin_arm_uhasx">,
166 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
167def int_arm_uhsax : GCCBuiltin<"__builtin_arm_uhsax">,
168 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
169def int_arm_uhsub16 : GCCBuiltin<"__builtin_arm_uhsub16">,
170 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
171def int_arm_uqadd16 : GCCBuiltin<"__builtin_arm_uqadd16">,
172 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
173def int_arm_uqasx : GCCBuiltin<"__builtin_arm_uqasx">,
174 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
175def int_arm_uqsax : GCCBuiltin<"__builtin_arm_uqsax">,
176 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
177def int_arm_uqsub16 : GCCBuiltin<"__builtin_arm_uqsub16">,
178 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
179// Writes to the GE bits.
180def int_arm_usax : GCCBuiltin<"__builtin_arm_usax">,
181 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
182// Writes to the GE bits.
183def int_arm_usub16 : GCCBuiltin<"__builtin_arm_usub16">,
184 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
185
186// Parallel 16-bit multiplication
187def int_arm_smlad : GCCBuiltin<"__builtin_arm_smlad">,
188 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
189 [IntrNoMem]>;
190def int_arm_smladx : GCCBuiltin<"__builtin_arm_smladx">,
191 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
192 [IntrNoMem]>;
193def int_arm_smlald : GCCBuiltin<"__builtin_arm_smlald">,
194 Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty],
195 [IntrNoMem]>;
196def int_arm_smlaldx : GCCBuiltin<"__builtin_arm_smlaldx">,
197 Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty],
198 [IntrNoMem]>;
199def int_arm_smlsd : GCCBuiltin<"__builtin_arm_smlsd">,
200 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
201 [IntrNoMem]>;
202def int_arm_smlsdx : GCCBuiltin<"__builtin_arm_smlsdx">,
203 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
204 [IntrNoMem]>;
205def int_arm_smlsld : GCCBuiltin<"__builtin_arm_smlsld">,
206 Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty],
207 [IntrNoMem]>;
208def int_arm_smlsldx : GCCBuiltin<"__builtin_arm_smlsldx">,
209 Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty],
210 [IntrNoMem]>;
211def int_arm_smuad : GCCBuiltin<"__builtin_arm_smuad">,
212 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
213def int_arm_smuadx : GCCBuiltin<"__builtin_arm_smuadx">,
214 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
215def int_arm_smusd : GCCBuiltin<"__builtin_arm_smusd">,
216 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
217def int_arm_smusdx : GCCBuiltin<"__builtin_arm_smusdx">,
218 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
219
220
221//===----------------------------------------------------------------------===//
222// Load, Store and Clear exclusive
223
224def int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
225def int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
226
227def int_arm_ldaex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
228def int_arm_stlex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
229
230def int_arm_clrex : Intrinsic<[]>;
231
232def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
233 llvm_ptr_ty]>;
234def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
235
236def int_arm_stlexd : Intrinsic<[llvm_i32_ty],
237 [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty]>;
238def int_arm_ldaexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
239
240//===----------------------------------------------------------------------===//
241// Data barrier instructions
242def int_arm_dmb : GCCBuiltin<"__builtin_arm_dmb">, MSBuiltin<"__dmb">,
243 Intrinsic<[], [llvm_i32_ty]>;
244def int_arm_dsb : GCCBuiltin<"__builtin_arm_dsb">, MSBuiltin<"__dsb">,
245 Intrinsic<[], [llvm_i32_ty]>;
246def int_arm_isb : GCCBuiltin<"__builtin_arm_isb">, MSBuiltin<"__isb">,
247 Intrinsic<[], [llvm_i32_ty]>;
248
249//===----------------------------------------------------------------------===//
250// VFP
251
252def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
253 Intrinsic<[llvm_i32_ty], [], []>;
254def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
255 Intrinsic<[], [llvm_i32_ty], []>;
256def int_arm_vcvtr : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
257 [IntrNoMem]>;
258def int_arm_vcvtru : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
259 [IntrNoMem]>;
260
261//===----------------------------------------------------------------------===//
262// Coprocessor
263
264def int_arm_ldc : GCCBuiltin<"__builtin_arm_ldc">,
265 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
266def int_arm_ldcl : GCCBuiltin<"__builtin_arm_ldcl">,
267 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
268def int_arm_ldc2 : GCCBuiltin<"__builtin_arm_ldc2">,
269 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
270def int_arm_ldc2l : GCCBuiltin<"__builtin_arm_ldc2l">,
271 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
272
273def int_arm_stc : GCCBuiltin<"__builtin_arm_stc">,
274 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
275def int_arm_stcl : GCCBuiltin<"__builtin_arm_stcl">,
276 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100[diff] [blame]277def int_arm_stc2 : GCCBuiltin<"__builtin_arm_stc2">,
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100[diff] [blame]278 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
279def int_arm_stc2l : GCCBuiltin<"__builtin_arm_stc2l">,
280 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
281
282// Move to coprocessor
283def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
284 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
285 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
286def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
287 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
288 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
289
290// Move from coprocessor
291def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
292 MSBuiltin<"_MoveFromCoprocessor">,
293 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
294 llvm_i32_ty, llvm_i32_ty], []>;
295def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
296 MSBuiltin<"_MoveFromCoprocessor2">,
297 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
298 llvm_i32_ty, llvm_i32_ty], []>;
299
300// Coprocessor data processing
301def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
302 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
303 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
304def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
305 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
306 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
307
308// Move from two registers to coprocessor
309def int_arm_mcrr : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
310 llvm_i32_ty, llvm_i32_ty], []>;
311def int_arm_mcrr2 : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
312 llvm_i32_ty, llvm_i32_ty], []>;
313
314def int_arm_mrrc : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_i32_ty,
315 llvm_i32_ty, llvm_i32_ty], []>;
316def int_arm_mrrc2 : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_i32_ty,
317 llvm_i32_ty, llvm_i32_ty], []>;
318
319//===----------------------------------------------------------------------===//
320// CRC32
321
322def int_arm_crc32b : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
323 [IntrNoMem]>;
324def int_arm_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
325 [IntrNoMem]>;
326def int_arm_crc32h : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
327 [IntrNoMem]>;
328def int_arm_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
329 [IntrNoMem]>;
330def int_arm_crc32w : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
331 [IntrNoMem]>;
332def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
333 [IntrNoMem]>;
334
335//===----------------------------------------------------------------------===//
336// HINT
337
338def int_arm_hint : Intrinsic<[], [llvm_i32_ty]>;
339def int_arm_dbg : Intrinsic<[], [llvm_i32_ty]>;
340
341//===----------------------------------------------------------------------===//
342// UND (reserved undefined sequence)
343
344def int_arm_undefined : Intrinsic<[], [llvm_i32_ty]>;
345
346//===----------------------------------------------------------------------===//
347// Advanced SIMD (NEON)
348
349// The following classes do not correspond directly to GCC builtins.
350class Neon_1Arg_Intrinsic
351 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
352class Neon_1Arg_Narrow_Intrinsic
353 : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>], [IntrNoMem]>;
354class Neon_2Arg_Intrinsic
355 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
356 [IntrNoMem]>;
357class Neon_2Arg_Narrow_Intrinsic
358 : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>, LLVMExtendedType<0>],
359 [IntrNoMem]>;
360class Neon_2Arg_Long_Intrinsic
361 : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>, LLVMTruncatedType<0>],
362 [IntrNoMem]>;
363class Neon_3Arg_Intrinsic
364 : Intrinsic<[llvm_anyvector_ty],
365 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
366 [IntrNoMem]>;
367class Neon_3Arg_Long_Intrinsic
368 : Intrinsic<[llvm_anyvector_ty],
369 [LLVMMatchType<0>, LLVMTruncatedType<0>, LLVMTruncatedType<0>],
370 [IntrNoMem]>;
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100[diff] [blame]371
372class Neon_1FloatArg_Intrinsic
373 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
374
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100[diff] [blame]375class Neon_CvtFxToFP_Intrinsic
376 : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
377class Neon_CvtFPToFx_Intrinsic
378 : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
379class Neon_CvtFPtoInt_1Arg_Intrinsic
380 : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
381
382class Neon_Compare_Intrinsic
383 : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>],
384 [IntrNoMem]>;
385
386// The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
387// Besides the table, VTBL has one other v8i8 argument and VTBX has two.
388// Overall, the classes range from 2 to 6 v8i8 arguments.
389class Neon_Tbl2Arg_Intrinsic
390 : Intrinsic<[llvm_v8i8_ty],
391 [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
392class Neon_Tbl3Arg_Intrinsic
393 : Intrinsic<[llvm_v8i8_ty],
394 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
395class Neon_Tbl4Arg_Intrinsic
396 : Intrinsic<[llvm_v8i8_ty],
397 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
398 [IntrNoMem]>;
399class Neon_Tbl5Arg_Intrinsic
400 : Intrinsic<[llvm_v8i8_ty],
401 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
402 llvm_v8i8_ty], [IntrNoMem]>;
403class Neon_Tbl6Arg_Intrinsic
404 : Intrinsic<[llvm_v8i8_ty],
405 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
406 llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
407
408// Arithmetic ops
409
410let IntrProperties = [IntrNoMem, Commutative] in {
411
412 // Vector Add.
413 def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
414 def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
415 def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
416 def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
417 def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
418 def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
419 def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
420
421 // Vector Multiply.
422 def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
423 def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
424 def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
425 def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
426 def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
427 def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
428 def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
429
430 // Vector Maximum.
431 def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
432 def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
433 def int_arm_neon_vmaxnm : Neon_2Arg_Intrinsic;
434
435 // Vector Minimum.
436 def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
437 def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
438 def int_arm_neon_vminnm : Neon_2Arg_Intrinsic;
439
440 // Vector Reciprocal Step.
441 def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
442
443 // Vector Reciprocal Square Root Step.
444 def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
445}
446
447// Vector Subtract.
448def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
449def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
450def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
451def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
452def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
453
454// Vector Absolute Compare.
455def int_arm_neon_vacge : Neon_Compare_Intrinsic;
456def int_arm_neon_vacgt : Neon_Compare_Intrinsic;
457
458// Vector Absolute Differences.
459def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
460def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
461
462// Vector Pairwise Add.
463def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
464
465// Vector Pairwise Add Long.
466// Note: This is different than the other "long" NEON intrinsics because
467// the result vector has half as many elements as the source vector.
468// The source and destination vector types must be specified separately.
469def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
470 [IntrNoMem]>;
471def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
472 [IntrNoMem]>;
473
474// Vector Pairwise Add and Accumulate Long.
475// Note: This is similar to vpaddl but the destination vector also appears
476// as the first argument.
477def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
478 [LLVMMatchType<0>, llvm_anyvector_ty],
479 [IntrNoMem]>;
480def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
481 [LLVMMatchType<0>, llvm_anyvector_ty],
482 [IntrNoMem]>;
483
484// Vector Pairwise Maximum and Minimum.
485def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
486def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
487def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
488def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
489
490// Vector Shifts:
491//
492// The various saturating and rounding vector shift operations need to be
493// represented by intrinsics in LLVM, and even the basic VSHL variable shift
494// operation cannot be safely translated to LLVM's shift operators. VSHL can
495// be used for both left and right shifts, or even combinations of the two,
496// depending on the signs of the shift amounts. It also has well-defined
497// behavior for shift amounts that LLVM leaves undefined. Only basic shifts
498// by constants can be represented with LLVM's shift operators.
499//
500// The shift counts for these intrinsics are always vectors, even for constant
501// shifts, where the constant is replicated. For consistency with VSHL (and
502// other variable shift instructions), left shifts have positive shift counts
503// and right shifts have negative shift counts. This convention is also used
504// for constant right shift intrinsics, and to help preserve sanity, the
505// intrinsic names use "shift" instead of either "shl" or "shr". Where
506// applicable, signed and unsigned versions of the intrinsics are
507// distinguished with "s" and "u" suffixes. A few NEON shift instructions,
508// such as VQSHLU, take signed operands but produce unsigned results; these
509// use a "su" suffix.
510
511// Vector Shift.
512def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
513def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
514
515// Vector Rounding Shift.
516def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
517def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
518def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
519
520// Vector Saturating Shift.
521def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
522def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
523def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
524def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
525def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
526def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
527
528// Vector Saturating Rounding Shift.
529def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
530def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
531def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
532def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
533def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
534
535// Vector Shift and Insert.
536def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
537
538// Vector Absolute Value and Saturating Absolute Value.
539def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
540def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
541
542// Vector Saturating Negate.
543def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
544
545// Vector Count Leading Sign/Zero Bits.
546def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
547
548// Vector Reciprocal Estimate.
549def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
550
551// Vector Reciprocal Square Root Estimate.
552def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
553
554// Vector Conversions Between Floating-point and Integer
555def int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic;
556def int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic;
557def int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic;
558def int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic;
559def int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic;
560def int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic;
561def int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic;
562def int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic;
563
564// Vector Conversions Between Floating-point and Fixed-point.
565def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
566def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
567def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
568def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
569
570// Vector Conversions Between Half-Precision and Single-Precision.
571def int_arm_neon_vcvtfp2hf
572 : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
573def int_arm_neon_vcvthf2fp
574 : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
575
576// Narrowing Saturating Vector Moves.
577def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
578def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
579def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
580
581// Vector Table Lookup.
582// The first 1-4 arguments are the table.
583def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
584def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
585def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
586def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
587
588// Vector Table Extension.
589// Some elements of the destination vector may not be updated, so the original
590// value of that vector is passed as the first argument. The next 1-4
591// arguments after that are the table.
592def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
593def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
594def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
595def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
596
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100[diff] [blame]597// Vector and Scalar Rounding.
598def int_arm_neon_vrintn : Neon_1FloatArg_Intrinsic;
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100[diff] [blame]599def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
600def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
601def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
602def int_arm_neon_vrintm : Neon_1Arg_Intrinsic;
603def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
604
605// De-interleaving vector loads from N-element structures.
606// Source operands are the address and alignment.
607def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
608 [llvm_anyptr_ty, llvm_i32_ty],
609 [IntrReadMem, IntrArgMemOnly]>;
610def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
611 [llvm_anyptr_ty, llvm_i32_ty],
612 [IntrReadMem, IntrArgMemOnly]>;
613def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
614 LLVMMatchType<0>],
615 [llvm_anyptr_ty, llvm_i32_ty],
616 [IntrReadMem, IntrArgMemOnly]>;
617def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
618 LLVMMatchType<0>, LLVMMatchType<0>],
619 [llvm_anyptr_ty, llvm_i32_ty],
620 [IntrReadMem, IntrArgMemOnly]>;
621
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100[diff] [blame]622def int_arm_neon_vld1x2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
623 [LLVMAnyPointerType<LLVMMatchType<0>>],
624 [IntrReadMem, IntrArgMemOnly]>;
625def int_arm_neon_vld1x3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
626 LLVMMatchType<0>],
627 [LLVMAnyPointerType<LLVMMatchType<0>>],
628 [IntrReadMem, IntrArgMemOnly]>;
629def int_arm_neon_vld1x4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
630 LLVMMatchType<0>, LLVMMatchType<0>],
631 [LLVMAnyPointerType<LLVMMatchType<0>>],
632 [IntrReadMem, IntrArgMemOnly]>;
633
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100[diff] [blame]634// Vector load N-element structure to one lane.
635// Source operands are: the address, the N input vectors (since only one
636// lane is assigned), the lane number, and the alignment.
637def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
638 [llvm_anyptr_ty, LLVMMatchType<0>,
639 LLVMMatchType<0>, llvm_i32_ty,
640 llvm_i32_ty], [IntrReadMem, IntrArgMemOnly]>;
641def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
642 LLVMMatchType<0>],
643 [llvm_anyptr_ty, LLVMMatchType<0>,
644 LLVMMatchType<0>, LLVMMatchType<0>,
645 llvm_i32_ty, llvm_i32_ty],
646 [IntrReadMem, IntrArgMemOnly]>;
647def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
648 LLVMMatchType<0>, LLVMMatchType<0>],
649 [llvm_anyptr_ty, LLVMMatchType<0>,
650 LLVMMatchType<0>, LLVMMatchType<0>,
651 LLVMMatchType<0>, llvm_i32_ty,
652 llvm_i32_ty], [IntrReadMem, IntrArgMemOnly]>;
653
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100[diff] [blame]654// Vector load N-element structure to all lanes.
655// Source operands are the address and alignment.
656def int_arm_neon_vld2dup : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
657 [llvm_anyptr_ty, llvm_i32_ty],
658 [IntrReadMem, IntrArgMemOnly]>;
659def int_arm_neon_vld3dup : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
660 LLVMMatchType<0>],
661 [llvm_anyptr_ty, llvm_i32_ty],
662 [IntrReadMem, IntrArgMemOnly]>;
663def int_arm_neon_vld4dup : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
664 LLVMMatchType<0>, LLVMMatchType<0>],
665 [llvm_anyptr_ty, llvm_i32_ty],
666 [IntrReadMem, IntrArgMemOnly]>;
667
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100[diff] [blame]668// Interleaving vector stores from N-element structures.
669// Source operands are: the address, the N vectors, and the alignment.
670def int_arm_neon_vst1 : Intrinsic<[],
671 [llvm_anyptr_ty, llvm_anyvector_ty,
672 llvm_i32_ty], [IntrArgMemOnly]>;
673def int_arm_neon_vst2 : Intrinsic<[],
674 [llvm_anyptr_ty, llvm_anyvector_ty,
675 LLVMMatchType<1>, llvm_i32_ty],
676 [IntrArgMemOnly]>;
677def int_arm_neon_vst3 : Intrinsic<[],
678 [llvm_anyptr_ty, llvm_anyvector_ty,
679 LLVMMatchType<1>, LLVMMatchType<1>,
680 llvm_i32_ty], [IntrArgMemOnly]>;
681def int_arm_neon_vst4 : Intrinsic<[],
682 [llvm_anyptr_ty, llvm_anyvector_ty,
683 LLVMMatchType<1>, LLVMMatchType<1>,
684 LLVMMatchType<1>, llvm_i32_ty],
685 [IntrArgMemOnly]>;
686
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100[diff] [blame]687def int_arm_neon_vst1x2 : Intrinsic<[],
688 [llvm_anyptr_ty, llvm_anyvector_ty,
689 LLVMMatchType<1>],
690 [IntrArgMemOnly, NoCapture<0>]>;
691def int_arm_neon_vst1x3 : Intrinsic<[],
692 [llvm_anyptr_ty, llvm_anyvector_ty,
693 LLVMMatchType<1>, LLVMMatchType<1>],
694 [IntrArgMemOnly, NoCapture<0>]>;
695def int_arm_neon_vst1x4 : Intrinsic<[],
696 [llvm_anyptr_ty, llvm_anyvector_ty,
697 LLVMMatchType<1>, LLVMMatchType<1>,
698 LLVMMatchType<1>],
699 [IntrArgMemOnly, NoCapture<0>]>;
700
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100[diff] [blame]701// Vector store N-element structure from one lane.
702// Source operands are: the address, the N vectors, the lane number, and
703// the alignment.
704def int_arm_neon_vst2lane : Intrinsic<[],
705 [llvm_anyptr_ty, llvm_anyvector_ty,
706 LLVMMatchType<1>, llvm_i32_ty,
707 llvm_i32_ty], [IntrArgMemOnly]>;
708def int_arm_neon_vst3lane : Intrinsic<[],
709 [llvm_anyptr_ty, llvm_anyvector_ty,
710 LLVMMatchType<1>, LLVMMatchType<1>,
711 llvm_i32_ty, llvm_i32_ty],
712 [IntrArgMemOnly]>;
713def int_arm_neon_vst4lane : Intrinsic<[],
714 [llvm_anyptr_ty, llvm_anyvector_ty,
715 LLVMMatchType<1>, LLVMMatchType<1>,
716 LLVMMatchType<1>, llvm_i32_ty,
717 llvm_i32_ty], [IntrArgMemOnly]>;
718
719// Vector bitwise select.
720def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty],
721 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
722 [IntrNoMem]>;
723
724
725// Crypto instructions
726class AES_1Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
727 [llvm_v16i8_ty], [IntrNoMem]>;
728class AES_2Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
729 [llvm_v16i8_ty, llvm_v16i8_ty],
730 [IntrNoMem]>;
731
732class SHA_1Arg_Intrinsic : Intrinsic<[llvm_i32_ty], [llvm_i32_ty],
733 [IntrNoMem]>;
734class SHA_2Arg_Intrinsic : Intrinsic<[llvm_v4i32_ty],
735 [llvm_v4i32_ty, llvm_v4i32_ty],
736 [IntrNoMem]>;
737class SHA_3Arg_i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
738 [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
739 [IntrNoMem]>;
740class SHA_3Arg_v4i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
741 [llvm_v4i32_ty, llvm_v4i32_ty,llvm_v4i32_ty],
742 [IntrNoMem]>;
743
744def int_arm_neon_aesd : AES_2Arg_Intrinsic;
745def int_arm_neon_aese : AES_2Arg_Intrinsic;
746def int_arm_neon_aesimc : AES_1Arg_Intrinsic;
747def int_arm_neon_aesmc : AES_1Arg_Intrinsic;
748def int_arm_neon_sha1h : SHA_1Arg_Intrinsic;
749def int_arm_neon_sha1su1 : SHA_2Arg_Intrinsic;
750def int_arm_neon_sha256su0 : SHA_2Arg_Intrinsic;
751def int_arm_neon_sha1c : SHA_3Arg_i32_Intrinsic;
752def int_arm_neon_sha1m : SHA_3Arg_i32_Intrinsic;
753def int_arm_neon_sha1p : SHA_3Arg_i32_Intrinsic;
754def int_arm_neon_sha1su0: SHA_3Arg_v4i32_Intrinsic;
755def int_arm_neon_sha256h: SHA_3Arg_v4i32_Intrinsic;
756def int_arm_neon_sha256h2: SHA_3Arg_v4i32_Intrinsic;
757def int_arm_neon_sha256su1: SHA_3Arg_v4i32_Intrinsic;
758
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100[diff] [blame]759// Armv8.2-A dot product instructions
760class Neon_Dot_Intrinsic
761 : Intrinsic<[llvm_anyvector_ty],
762 [LLVMMatchType<0>, llvm_anyvector_ty,
763 LLVMMatchType<1>],
764 [IntrNoMem]>;
765def int_arm_neon_udot : Neon_Dot_Intrinsic;
766def int_arm_neon_sdot : Neon_Dot_Intrinsic;
767
768
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100[diff] [blame]769} // end TargetPrefix