TrustedFirmware Git Browser
Code Review Sign In
review.trustedfirmware.org / hafnium / prebuilts / 52c2969f621c443130e93da7ae16eea8d8fe620b / . / linux-x64 / clang / include / llvm / IR / IntrinsicsARM.td
blob: 4e11f9c29dd056234666f6da633061a3e074f202 [file] [log] [blame]
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100[diff] [blame]1//===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines all of the ARM-specific intrinsics.
11//
12//===----------------------------------------------------------------------===//
13
14
15//===----------------------------------------------------------------------===//
16// TLS
17
18let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
19
20// A space-consuming intrinsic primarily for testing ARMConstantIslands. The
21// first argument is the number of bytes this "instruction" takes up, the second
22// and return value are essentially chains, used to force ordering during ISel.
23def int_arm_space : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
24
25// 16-bit multiplications
26def int_arm_smulbb : GCCBuiltin<"__builtin_arm_smulbb">,
27 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
28def int_arm_smulbt : GCCBuiltin<"__builtin_arm_smulbt">,
29 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
30def int_arm_smultb : GCCBuiltin<"__builtin_arm_smultb">,
31 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
32def int_arm_smultt : GCCBuiltin<"__builtin_arm_smultt">,
33 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
34def int_arm_smulwb : GCCBuiltin<"__builtin_arm_smulwb">,
35 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
36def int_arm_smulwt : GCCBuiltin<"__builtin_arm_smulwt">,
37 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
38
39//===----------------------------------------------------------------------===//
40// Saturating Arithmetic
41
42def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
43 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
44 [Commutative, IntrNoMem]>;
45def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
46 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
47def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
48 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
49def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
50 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
51
52// Accumulating multiplications
53def int_arm_smlabb : GCCBuiltin<"__builtin_arm_smlabb">,
54 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
55 [IntrNoMem]>;
56def int_arm_smlabt : GCCBuiltin<"__builtin_arm_smlabt">,
57 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
58 [IntrNoMem]>;
59def int_arm_smlatb : GCCBuiltin<"__builtin_arm_smlatb">,
60 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
61 [IntrNoMem]>;
62def int_arm_smlatt : GCCBuiltin<"__builtin_arm_smlatt">,
63 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
64 [IntrNoMem]>;
65def int_arm_smlawb : GCCBuiltin<"__builtin_arm_smlawb">,
66 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
67 [IntrNoMem]>;
68def int_arm_smlawt : GCCBuiltin<"__builtin_arm_smlawt">,
69 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
70 [IntrNoMem]>;
71
72// Parallel 16-bit saturation
73def int_arm_ssat16 : GCCBuiltin<"__builtin_arm_ssat16">,
74 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
75def int_arm_usat16 : GCCBuiltin<"__builtin_arm_usat16">,
76 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
77
78// Packing and unpacking
79def int_arm_sxtab16 : GCCBuiltin<"__builtin_arm_sxtab16">,
80 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
81def int_arm_sxtb16 : GCCBuiltin<"__builtin_arm_sxtb16">,
82 Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
83def int_arm_uxtab16 : GCCBuiltin<"__builtin_arm_uxtab16">,
84 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
85def int_arm_uxtb16 : GCCBuiltin<"__builtin_arm_uxtb16">,
86 Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
87
88// Parallel selection, reads the GE flags.
89def int_arm_sel : GCCBuiltin<"__builtin_arm_sel">,
90 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrReadMem]>;
91
92// Parallel 8-bit addition and subtraction
93def int_arm_qadd8 : GCCBuiltin<"__builtin_arm_qadd8">,
94 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
95def int_arm_qsub8 : GCCBuiltin<"__builtin_arm_qsub8">,
96 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
97// Writes to the GE bits.
98def int_arm_sadd8 : GCCBuiltin<"__builtin_arm_sadd8">,
99 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
100def int_arm_shadd8 : GCCBuiltin<"__builtin_arm_shadd8">,
101 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
102def int_arm_shsub8 : GCCBuiltin<"__builtin_arm_shsub8">,
103 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
104// Writes to the GE bits.
105def int_arm_ssub8 : GCCBuiltin<"__builtin_arm_ssub8">,
106 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
107// Writes to the GE bits.
108def int_arm_uadd8 : GCCBuiltin<"__builtin_arm_uadd8">,
109 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
110def int_arm_uhadd8 : GCCBuiltin<"__builtin_arm_uhadd8">,
111 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
112def int_arm_uhsub8 : GCCBuiltin<"__builtin_arm_uhsub8">,
113 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
114def int_arm_uqadd8 : GCCBuiltin<"__builtin_arm_uqadd8">,
115 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
116def int_arm_uqsub8 : GCCBuiltin<"__builtin_arm_uqsub8">,
117 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
118// Writes to the GE bits.
119def int_arm_usub8 : GCCBuiltin<"__builtin_arm_usub8">,
120 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
121
122// Sum of 8-bit absolute differences
123def int_arm_usad8 : GCCBuiltin<"__builtin_arm_usad8">,
124 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
125def int_arm_usada8 : GCCBuiltin<"__builtin_arm_usada8">,
126 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
127 [IntrNoMem]>;
128
129// Parallel 16-bit addition and subtraction
130def int_arm_qadd16 : GCCBuiltin<"__builtin_arm_qadd16">,
131 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
132def int_arm_qasx : GCCBuiltin<"__builtin_arm_qasx">,
133 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
134def int_arm_qsax : GCCBuiltin<"__builtin_arm_qsax">,
135 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
136def int_arm_qsub16 : GCCBuiltin<"__builtin_arm_qsub16">,
137 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
138// Writes to the GE bits.
139def int_arm_sadd16 : GCCBuiltin<"__builtin_arm_sadd16">,
140 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
141// Writes to the GE bits.
142def int_arm_sasx : GCCBuiltin<"__builtin_arm_sasx">,
143 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
144def int_arm_shadd16 : GCCBuiltin<"__builtin_arm_shadd16">,
145 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
146def int_arm_shasx : GCCBuiltin<"__builtin_arm_shasx">,
147 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
148def int_arm_shsax : GCCBuiltin<"__builtin_arm_shsax">,
149 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
150def int_arm_shsub16 : GCCBuiltin<"__builtin_arm_shsub16">,
151 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
152// Writes to the GE bits.
153def int_arm_ssax : GCCBuiltin<"__builtin_arm_ssax">,
154 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
155// Writes to the GE bits.
156def int_arm_ssub16 : GCCBuiltin<"__builtin_arm_ssub16">,
157 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
158// Writes to the GE bits.
159def int_arm_uadd16 : GCCBuiltin<"__builtin_arm_uadd16">,
160 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
161// Writes to the GE bits.
162def int_arm_uasx : GCCBuiltin<"__builtin_arm_uasx">,
163 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
164def int_arm_uhadd16 : GCCBuiltin<"__builtin_arm_uhadd16">,
165 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
166def int_arm_uhasx : GCCBuiltin<"__builtin_arm_uhasx">,
167 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
168def int_arm_uhsax : GCCBuiltin<"__builtin_arm_uhsax">,
169 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
170def int_arm_uhsub16 : GCCBuiltin<"__builtin_arm_uhsub16">,
171 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
172def int_arm_uqadd16 : GCCBuiltin<"__builtin_arm_uqadd16">,
173 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
174def int_arm_uqasx : GCCBuiltin<"__builtin_arm_uqasx">,
175 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
176def int_arm_uqsax : GCCBuiltin<"__builtin_arm_uqsax">,
177 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
178def int_arm_uqsub16 : GCCBuiltin<"__builtin_arm_uqsub16">,
179 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
180// Writes to the GE bits.
181def int_arm_usax : GCCBuiltin<"__builtin_arm_usax">,
182 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
183// Writes to the GE bits.
184def int_arm_usub16 : GCCBuiltin<"__builtin_arm_usub16">,
185 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
186
187// Parallel 16-bit multiplication
188def int_arm_smlad : GCCBuiltin<"__builtin_arm_smlad">,
189 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
190 [IntrNoMem]>;
191def int_arm_smladx : GCCBuiltin<"__builtin_arm_smladx">,
192 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
193 [IntrNoMem]>;
194def int_arm_smlald : GCCBuiltin<"__builtin_arm_smlald">,
195 Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty],
196 [IntrNoMem]>;
197def int_arm_smlaldx : GCCBuiltin<"__builtin_arm_smlaldx">,
198 Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty],
199 [IntrNoMem]>;
200def int_arm_smlsd : GCCBuiltin<"__builtin_arm_smlsd">,
201 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
202 [IntrNoMem]>;
203def int_arm_smlsdx : GCCBuiltin<"__builtin_arm_smlsdx">,
204 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
205 [IntrNoMem]>;
206def int_arm_smlsld : GCCBuiltin<"__builtin_arm_smlsld">,
207 Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty],
208 [IntrNoMem]>;
209def int_arm_smlsldx : GCCBuiltin<"__builtin_arm_smlsldx">,
210 Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty],
211 [IntrNoMem]>;
212def int_arm_smuad : GCCBuiltin<"__builtin_arm_smuad">,
213 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
214def int_arm_smuadx : GCCBuiltin<"__builtin_arm_smuadx">,
215 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
216def int_arm_smusd : GCCBuiltin<"__builtin_arm_smusd">,
217 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
218def int_arm_smusdx : GCCBuiltin<"__builtin_arm_smusdx">,
219 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
220
221
222//===----------------------------------------------------------------------===//
223// Load, Store and Clear exclusive
224
225def int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
226def int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
227
228def int_arm_ldaex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
229def int_arm_stlex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
230
231def int_arm_clrex : Intrinsic<[]>;
232
233def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
234 llvm_ptr_ty]>;
235def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
236
237def int_arm_stlexd : Intrinsic<[llvm_i32_ty],
238 [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty]>;
239def int_arm_ldaexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
240
241//===----------------------------------------------------------------------===//
242// Data barrier instructions
243def int_arm_dmb : GCCBuiltin<"__builtin_arm_dmb">, MSBuiltin<"__dmb">,
244 Intrinsic<[], [llvm_i32_ty]>;
245def int_arm_dsb : GCCBuiltin<"__builtin_arm_dsb">, MSBuiltin<"__dsb">,
246 Intrinsic<[], [llvm_i32_ty]>;
247def int_arm_isb : GCCBuiltin<"__builtin_arm_isb">, MSBuiltin<"__isb">,
248 Intrinsic<[], [llvm_i32_ty]>;
249
250//===----------------------------------------------------------------------===//
251// VFP
252
253def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
254 Intrinsic<[llvm_i32_ty], [], []>;
255def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
256 Intrinsic<[], [llvm_i32_ty], []>;
257def int_arm_vcvtr : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
258 [IntrNoMem]>;
259def int_arm_vcvtru : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
260 [IntrNoMem]>;
261
262//===----------------------------------------------------------------------===//
263// Coprocessor
264
265def int_arm_ldc : GCCBuiltin<"__builtin_arm_ldc">,
266 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
267def int_arm_ldcl : GCCBuiltin<"__builtin_arm_ldcl">,
268 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
269def int_arm_ldc2 : GCCBuiltin<"__builtin_arm_ldc2">,
270 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
271def int_arm_ldc2l : GCCBuiltin<"__builtin_arm_ldc2l">,
272 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
273
274def int_arm_stc : GCCBuiltin<"__builtin_arm_stc">,
275 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
276def int_arm_stcl : GCCBuiltin<"__builtin_arm_stcl">,
277 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100[diff] [blame]278def int_arm_stc2 : GCCBuiltin<"__builtin_arm_stc2">,
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100[diff] [blame]279 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
280def int_arm_stc2l : GCCBuiltin<"__builtin_arm_stc2l">,
281 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
282
283// Move to coprocessor
284def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
285 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
286 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
287def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
288 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
289 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
290
291// Move from coprocessor
292def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
293 MSBuiltin<"_MoveFromCoprocessor">,
294 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
295 llvm_i32_ty, llvm_i32_ty], []>;
296def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
297 MSBuiltin<"_MoveFromCoprocessor2">,
298 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
299 llvm_i32_ty, llvm_i32_ty], []>;
300
301// Coprocessor data processing
302def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
303 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
304 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
305def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
306 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
307 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
308
309// Move from two registers to coprocessor
310def int_arm_mcrr : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
311 llvm_i32_ty, llvm_i32_ty], []>;
312def int_arm_mcrr2 : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
313 llvm_i32_ty, llvm_i32_ty], []>;
314
315def int_arm_mrrc : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_i32_ty,
316 llvm_i32_ty, llvm_i32_ty], []>;
317def int_arm_mrrc2 : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_i32_ty,
318 llvm_i32_ty, llvm_i32_ty], []>;
319
320//===----------------------------------------------------------------------===//
321// CRC32
322
323def int_arm_crc32b : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
324 [IntrNoMem]>;
325def int_arm_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
326 [IntrNoMem]>;
327def int_arm_crc32h : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
328 [IntrNoMem]>;
329def int_arm_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
330 [IntrNoMem]>;
331def int_arm_crc32w : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
332 [IntrNoMem]>;
333def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
334 [IntrNoMem]>;
335
336//===----------------------------------------------------------------------===//
337// HINT
338
339def int_arm_hint : Intrinsic<[], [llvm_i32_ty]>;
340def int_arm_dbg : Intrinsic<[], [llvm_i32_ty]>;
341
342//===----------------------------------------------------------------------===//
343// UND (reserved undefined sequence)
344
345def int_arm_undefined : Intrinsic<[], [llvm_i32_ty]>;
346
347//===----------------------------------------------------------------------===//
348// Advanced SIMD (NEON)
349
350// The following classes do not correspond directly to GCC builtins.
351class Neon_1Arg_Intrinsic
352 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
353class Neon_1Arg_Narrow_Intrinsic
354 : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>], [IntrNoMem]>;
355class Neon_2Arg_Intrinsic
356 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
357 [IntrNoMem]>;
358class Neon_2Arg_Narrow_Intrinsic
359 : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>, LLVMExtendedType<0>],
360 [IntrNoMem]>;
361class Neon_2Arg_Long_Intrinsic
362 : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>, LLVMTruncatedType<0>],
363 [IntrNoMem]>;
364class Neon_3Arg_Intrinsic
365 : Intrinsic<[llvm_anyvector_ty],
366 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
367 [IntrNoMem]>;
368class Neon_3Arg_Long_Intrinsic
369 : Intrinsic<[llvm_anyvector_ty],
370 [LLVMMatchType<0>, LLVMTruncatedType<0>, LLVMTruncatedType<0>],
371 [IntrNoMem]>;
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100[diff] [blame]372
373class Neon_1FloatArg_Intrinsic
374 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
375
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100[diff] [blame]376class Neon_CvtFxToFP_Intrinsic
377 : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
378class Neon_CvtFPToFx_Intrinsic
379 : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
380class Neon_CvtFPtoInt_1Arg_Intrinsic
381 : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
382
383class Neon_Compare_Intrinsic
384 : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>],
385 [IntrNoMem]>;
386
387// The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
388// Besides the table, VTBL has one other v8i8 argument and VTBX has two.
389// Overall, the classes range from 2 to 6 v8i8 arguments.
390class Neon_Tbl2Arg_Intrinsic
391 : Intrinsic<[llvm_v8i8_ty],
392 [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
393class Neon_Tbl3Arg_Intrinsic
394 : Intrinsic<[llvm_v8i8_ty],
395 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
396class Neon_Tbl4Arg_Intrinsic
397 : Intrinsic<[llvm_v8i8_ty],
398 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
399 [IntrNoMem]>;
400class Neon_Tbl5Arg_Intrinsic
401 : Intrinsic<[llvm_v8i8_ty],
402 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
403 llvm_v8i8_ty], [IntrNoMem]>;
404class Neon_Tbl6Arg_Intrinsic
405 : Intrinsic<[llvm_v8i8_ty],
406 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
407 llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
408
409// Arithmetic ops
410
411let IntrProperties = [IntrNoMem, Commutative] in {
412
413 // Vector Add.
414 def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
415 def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
416 def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
417 def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
418 def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
419 def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
420 def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
421
422 // Vector Multiply.
423 def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
424 def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
425 def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
426 def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
427 def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
428 def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
429 def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
430
431 // Vector Maximum.
432 def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
433 def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
434 def int_arm_neon_vmaxnm : Neon_2Arg_Intrinsic;
435
436 // Vector Minimum.
437 def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
438 def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
439 def int_arm_neon_vminnm : Neon_2Arg_Intrinsic;
440
441 // Vector Reciprocal Step.
442 def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
443
444 // Vector Reciprocal Square Root Step.
445 def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
446}
447
448// Vector Subtract.
449def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
450def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
451def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
452def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
453def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
454
455// Vector Absolute Compare.
456def int_arm_neon_vacge : Neon_Compare_Intrinsic;
457def int_arm_neon_vacgt : Neon_Compare_Intrinsic;
458
459// Vector Absolute Differences.
460def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
461def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
462
463// Vector Pairwise Add.
464def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
465
466// Vector Pairwise Add Long.
467// Note: This is different than the other "long" NEON intrinsics because
468// the result vector has half as many elements as the source vector.
469// The source and destination vector types must be specified separately.
470def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
471 [IntrNoMem]>;
472def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
473 [IntrNoMem]>;
474
475// Vector Pairwise Add and Accumulate Long.
476// Note: This is similar to vpaddl but the destination vector also appears
477// as the first argument.
478def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
479 [LLVMMatchType<0>, llvm_anyvector_ty],
480 [IntrNoMem]>;
481def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
482 [LLVMMatchType<0>, llvm_anyvector_ty],
483 [IntrNoMem]>;
484
485// Vector Pairwise Maximum and Minimum.
486def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
487def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
488def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
489def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
490
491// Vector Shifts:
492//
493// The various saturating and rounding vector shift operations need to be
494// represented by intrinsics in LLVM, and even the basic VSHL variable shift
495// operation cannot be safely translated to LLVM's shift operators. VSHL can
496// be used for both left and right shifts, or even combinations of the two,
497// depending on the signs of the shift amounts. It also has well-defined
498// behavior for shift amounts that LLVM leaves undefined. Only basic shifts
499// by constants can be represented with LLVM's shift operators.
500//
501// The shift counts for these intrinsics are always vectors, even for constant
502// shifts, where the constant is replicated. For consistency with VSHL (and
503// other variable shift instructions), left shifts have positive shift counts
504// and right shifts have negative shift counts. This convention is also used
505// for constant right shift intrinsics, and to help preserve sanity, the
506// intrinsic names use "shift" instead of either "shl" or "shr". Where
507// applicable, signed and unsigned versions of the intrinsics are
508// distinguished with "s" and "u" suffixes. A few NEON shift instructions,
509// such as VQSHLU, take signed operands but produce unsigned results; these
510// use a "su" suffix.
511
512// Vector Shift.
513def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
514def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
515
516// Vector Rounding Shift.
517def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
518def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
519def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
520
521// Vector Saturating Shift.
522def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
523def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
524def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
525def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
526def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
527def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
528
529// Vector Saturating Rounding Shift.
530def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
531def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
532def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
533def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
534def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
535
536// Vector Shift and Insert.
537def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
538
539// Vector Absolute Value and Saturating Absolute Value.
540def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
541def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
542
543// Vector Saturating Negate.
544def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
545
546// Vector Count Leading Sign/Zero Bits.
547def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
548
549// Vector Reciprocal Estimate.
550def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
551
552// Vector Reciprocal Square Root Estimate.
553def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
554
555// Vector Conversions Between Floating-point and Integer
556def int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic;
557def int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic;
558def int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic;
559def int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic;
560def int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic;
561def int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic;
562def int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic;
563def int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic;
564
565// Vector Conversions Between Floating-point and Fixed-point.
566def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
567def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
568def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
569def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
570
571// Vector Conversions Between Half-Precision and Single-Precision.
572def int_arm_neon_vcvtfp2hf
573 : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
574def int_arm_neon_vcvthf2fp
575 : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
576
577// Narrowing Saturating Vector Moves.
578def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
579def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
580def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
581
582// Vector Table Lookup.
583// The first 1-4 arguments are the table.
584def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
585def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
586def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
587def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
588
589// Vector Table Extension.
590// Some elements of the destination vector may not be updated, so the original
591// value of that vector is passed as the first argument. The next 1-4
592// arguments after that are the table.
593def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
594def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
595def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
596def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
597
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100[diff] [blame]598// Vector and Scalar Rounding.
599def int_arm_neon_vrintn : Neon_1FloatArg_Intrinsic;
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100[diff] [blame]600def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
601def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
602def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
603def int_arm_neon_vrintm : Neon_1Arg_Intrinsic;
604def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
605
606// De-interleaving vector loads from N-element structures.
607// Source operands are the address and alignment.
608def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
609 [llvm_anyptr_ty, llvm_i32_ty],
610 [IntrReadMem, IntrArgMemOnly]>;
611def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
612 [llvm_anyptr_ty, llvm_i32_ty],
613 [IntrReadMem, IntrArgMemOnly]>;
614def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
615 LLVMMatchType<0>],
616 [llvm_anyptr_ty, llvm_i32_ty],
617 [IntrReadMem, IntrArgMemOnly]>;
618def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
619 LLVMMatchType<0>, LLVMMatchType<0>],
620 [llvm_anyptr_ty, llvm_i32_ty],
621 [IntrReadMem, IntrArgMemOnly]>;
622
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100[diff] [blame]623def int_arm_neon_vld1x2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
624 [LLVMAnyPointerType<LLVMMatchType<0>>],
625 [IntrReadMem, IntrArgMemOnly]>;
626def int_arm_neon_vld1x3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
627 LLVMMatchType<0>],
628 [LLVMAnyPointerType<LLVMMatchType<0>>],
629 [IntrReadMem, IntrArgMemOnly]>;
630def int_arm_neon_vld1x4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
631 LLVMMatchType<0>, LLVMMatchType<0>],
632 [LLVMAnyPointerType<LLVMMatchType<0>>],
633 [IntrReadMem, IntrArgMemOnly]>;
634
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100[diff] [blame]635// Vector load N-element structure to one lane.
636// Source operands are: the address, the N input vectors (since only one
637// lane is assigned), the lane number, and the alignment.
638def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
639 [llvm_anyptr_ty, LLVMMatchType<0>,
640 LLVMMatchType<0>, llvm_i32_ty,
641 llvm_i32_ty], [IntrReadMem, IntrArgMemOnly]>;
642def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
643 LLVMMatchType<0>],
644 [llvm_anyptr_ty, LLVMMatchType<0>,
645 LLVMMatchType<0>, LLVMMatchType<0>,
646 llvm_i32_ty, llvm_i32_ty],
647 [IntrReadMem, IntrArgMemOnly]>;
648def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
649 LLVMMatchType<0>, LLVMMatchType<0>],
650 [llvm_anyptr_ty, LLVMMatchType<0>,
651 LLVMMatchType<0>, LLVMMatchType<0>,
652 LLVMMatchType<0>, llvm_i32_ty,
653 llvm_i32_ty], [IntrReadMem, IntrArgMemOnly]>;
654
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100[diff] [blame]655// Vector load N-element structure to all lanes.
656// Source operands are the address and alignment.
657def int_arm_neon_vld2dup : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
658 [llvm_anyptr_ty, llvm_i32_ty],
659 [IntrReadMem, IntrArgMemOnly]>;
660def int_arm_neon_vld3dup : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
661 LLVMMatchType<0>],
662 [llvm_anyptr_ty, llvm_i32_ty],
663 [IntrReadMem, IntrArgMemOnly]>;
664def int_arm_neon_vld4dup : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
665 LLVMMatchType<0>, LLVMMatchType<0>],
666 [llvm_anyptr_ty, llvm_i32_ty],
667 [IntrReadMem, IntrArgMemOnly]>;
668
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100[diff] [blame]669// Interleaving vector stores from N-element structures.
670// Source operands are: the address, the N vectors, and the alignment.
671def int_arm_neon_vst1 : Intrinsic<[],
672 [llvm_anyptr_ty, llvm_anyvector_ty,
673 llvm_i32_ty], [IntrArgMemOnly]>;
674def int_arm_neon_vst2 : Intrinsic<[],
675 [llvm_anyptr_ty, llvm_anyvector_ty,
676 LLVMMatchType<1>, llvm_i32_ty],
677 [IntrArgMemOnly]>;
678def int_arm_neon_vst3 : Intrinsic<[],
679 [llvm_anyptr_ty, llvm_anyvector_ty,
680 LLVMMatchType<1>, LLVMMatchType<1>,
681 llvm_i32_ty], [IntrArgMemOnly]>;
682def int_arm_neon_vst4 : Intrinsic<[],
683 [llvm_anyptr_ty, llvm_anyvector_ty,
684 LLVMMatchType<1>, LLVMMatchType<1>,
685 LLVMMatchType<1>, llvm_i32_ty],
686 [IntrArgMemOnly]>;
687
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100[diff] [blame]688def int_arm_neon_vst1x2 : Intrinsic<[],
689 [llvm_anyptr_ty, llvm_anyvector_ty,
690 LLVMMatchType<1>],
691 [IntrArgMemOnly, NoCapture<0>]>;
692def int_arm_neon_vst1x3 : Intrinsic<[],
693 [llvm_anyptr_ty, llvm_anyvector_ty,
694 LLVMMatchType<1>, LLVMMatchType<1>],
695 [IntrArgMemOnly, NoCapture<0>]>;
696def int_arm_neon_vst1x4 : Intrinsic<[],
697 [llvm_anyptr_ty, llvm_anyvector_ty,
698 LLVMMatchType<1>, LLVMMatchType<1>,
699 LLVMMatchType<1>],
700 [IntrArgMemOnly, NoCapture<0>]>;
701
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100[diff] [blame]702// Vector store N-element structure from one lane.
703// Source operands are: the address, the N vectors, the lane number, and
704// the alignment.
705def int_arm_neon_vst2lane : Intrinsic<[],
706 [llvm_anyptr_ty, llvm_anyvector_ty,
707 LLVMMatchType<1>, llvm_i32_ty,
708 llvm_i32_ty], [IntrArgMemOnly]>;
709def int_arm_neon_vst3lane : Intrinsic<[],
710 [llvm_anyptr_ty, llvm_anyvector_ty,
711 LLVMMatchType<1>, LLVMMatchType<1>,
712 llvm_i32_ty, llvm_i32_ty],
713 [IntrArgMemOnly]>;
714def int_arm_neon_vst4lane : Intrinsic<[],
715 [llvm_anyptr_ty, llvm_anyvector_ty,
716 LLVMMatchType<1>, LLVMMatchType<1>,
717 LLVMMatchType<1>, llvm_i32_ty,
718 llvm_i32_ty], [IntrArgMemOnly]>;
719
720// Vector bitwise select.
721def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty],
722 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
723 [IntrNoMem]>;
724
725
726// Crypto instructions
727class AES_1Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
728 [llvm_v16i8_ty], [IntrNoMem]>;
729class AES_2Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
730 [llvm_v16i8_ty, llvm_v16i8_ty],
731 [IntrNoMem]>;
732
733class SHA_1Arg_Intrinsic : Intrinsic<[llvm_i32_ty], [llvm_i32_ty],
734 [IntrNoMem]>;
735class SHA_2Arg_Intrinsic : Intrinsic<[llvm_v4i32_ty],
736 [llvm_v4i32_ty, llvm_v4i32_ty],
737 [IntrNoMem]>;
738class SHA_3Arg_i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
739 [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
740 [IntrNoMem]>;
741class SHA_3Arg_v4i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
742 [llvm_v4i32_ty, llvm_v4i32_ty,llvm_v4i32_ty],
743 [IntrNoMem]>;
744
745def int_arm_neon_aesd : AES_2Arg_Intrinsic;
746def int_arm_neon_aese : AES_2Arg_Intrinsic;
747def int_arm_neon_aesimc : AES_1Arg_Intrinsic;
748def int_arm_neon_aesmc : AES_1Arg_Intrinsic;
749def int_arm_neon_sha1h : SHA_1Arg_Intrinsic;
750def int_arm_neon_sha1su1 : SHA_2Arg_Intrinsic;
751def int_arm_neon_sha256su0 : SHA_2Arg_Intrinsic;
752def int_arm_neon_sha1c : SHA_3Arg_i32_Intrinsic;
753def int_arm_neon_sha1m : SHA_3Arg_i32_Intrinsic;
754def int_arm_neon_sha1p : SHA_3Arg_i32_Intrinsic;
755def int_arm_neon_sha1su0: SHA_3Arg_v4i32_Intrinsic;
756def int_arm_neon_sha256h: SHA_3Arg_v4i32_Intrinsic;
757def int_arm_neon_sha256h2: SHA_3Arg_v4i32_Intrinsic;
758def int_arm_neon_sha256su1: SHA_3Arg_v4i32_Intrinsic;
759
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100[diff] [blame]760// Armv8.2-A dot product instructions
761class Neon_Dot_Intrinsic
762 : Intrinsic<[llvm_anyvector_ty],
763 [LLVMMatchType<0>, llvm_anyvector_ty,
764 LLVMMatchType<1>],
765 [IntrNoMem]>;
766def int_arm_neon_udot : Neon_Dot_Intrinsic;
767def int_arm_neon_sdot : Neon_Dot_Intrinsic;
768
769
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100[diff] [blame]770} // end TargetPrefix