Andrew Scull | 5e1ddfa | 2018-08-14 10:06:54 +0100 | [diff] [blame] | 1 | //===-- TargetParser - Parser for target features ---------------*- C++ -*-===// |
| 2 | // |
Andrew Walbran | 16937d0 | 2019-10-22 13:54:20 +0100 | [diff] [blame] | 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | // See https://llvm.org/LICENSE.txt for license information. |
| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
Andrew Scull | 5e1ddfa | 2018-08-14 10:06:54 +0100 | [diff] [blame] | 6 | // |
| 7 | //===----------------------------------------------------------------------===// |
| 8 | // |
| 9 | // This file implements a target parser to recognise hardware features such as |
| 10 | // FPU/CPU/ARCH names as well as specific support such as HDIV, etc. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #ifndef LLVM_SUPPORT_TARGETPARSER_H |
| 15 | #define LLVM_SUPPORT_TARGETPARSER_H |
| 16 | |
| 17 | // FIXME: vector is used because that's what clang uses for subtarget feature |
| 18 | // lists, but SmallVector would probably be better |
| 19 | #include "llvm/ADT/Triple.h" |
Andrew Walbran | 16937d0 | 2019-10-22 13:54:20 +0100 | [diff] [blame] | 20 | #include "llvm/Support/ARMTargetParser.h" |
| 21 | #include "llvm/Support/AArch64TargetParser.h" |
Andrew Scull | 5e1ddfa | 2018-08-14 10:06:54 +0100 | [diff] [blame] | 22 | #include <vector> |
| 23 | |
| 24 | namespace llvm { |
| 25 | class StringRef; |
| 26 | |
Andrew Walbran | 16937d0 | 2019-10-22 13:54:20 +0100 | [diff] [blame] | 27 | // Target specific information in their own namespaces. |
| 28 | // (ARM/AArch64 are declared in ARM/AArch64TargetParser.h) |
| 29 | // These should be generated from TableGen because the information is already |
| 30 | // there, and there is where new information about targets will be added. |
Andrew Scull | 5e1ddfa | 2018-08-14 10:06:54 +0100 | [diff] [blame] | 31 | // FIXME: To TableGen this we need to make some table generated files available |
| 32 | // even if the back-end is not compiled with LLVM, plus we need to create a new |
| 33 | // back-end to TableGen to create these clean tables. |
Andrew Scull | 5e1ddfa | 2018-08-14 10:06:54 +0100 | [diff] [blame] | 34 | namespace X86 { |
| 35 | |
| 36 | // This should be kept in sync with libcc/compiler-rt as its included by clang |
| 37 | // as a proxy for what's in libgcc/compiler-rt. |
| 38 | enum ProcessorVendors : unsigned { |
| 39 | VENDOR_DUMMY, |
| 40 | #define X86_VENDOR(ENUM, STRING) \ |
| 41 | ENUM, |
| 42 | #include "llvm/Support/X86TargetParser.def" |
| 43 | VENDOR_OTHER |
| 44 | }; |
| 45 | |
| 46 | // This should be kept in sync with libcc/compiler-rt as its included by clang |
| 47 | // as a proxy for what's in libgcc/compiler-rt. |
| 48 | enum ProcessorTypes : unsigned { |
| 49 | CPU_TYPE_DUMMY, |
| 50 | #define X86_CPU_TYPE(ARCHNAME, ENUM) \ |
| 51 | ENUM, |
| 52 | #include "llvm/Support/X86TargetParser.def" |
| 53 | CPU_TYPE_MAX |
| 54 | }; |
| 55 | |
| 56 | // This should be kept in sync with libcc/compiler-rt as its included by clang |
| 57 | // as a proxy for what's in libgcc/compiler-rt. |
| 58 | enum ProcessorSubtypes : unsigned { |
| 59 | CPU_SUBTYPE_DUMMY, |
| 60 | #define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \ |
| 61 | ENUM, |
| 62 | #include "llvm/Support/X86TargetParser.def" |
| 63 | CPU_SUBTYPE_MAX |
| 64 | }; |
| 65 | |
| 66 | // This should be kept in sync with libcc/compiler-rt as it should be used |
| 67 | // by clang as a proxy for what's in libgcc/compiler-rt. |
| 68 | enum ProcessorFeatures { |
| 69 | #define X86_FEATURE(VAL, ENUM) \ |
| 70 | ENUM = VAL, |
| 71 | #include "llvm/Support/X86TargetParser.def" |
| 72 | |
| 73 | }; |
| 74 | |
| 75 | } // namespace X86 |
| 76 | |
Andrew Scull | 0372a57 | 2018-11-16 15:47:06 +0000 | [diff] [blame] | 77 | namespace AMDGPU { |
| 78 | |
| 79 | /// GPU kinds supported by the AMDGPU target. |
| 80 | enum GPUKind : uint32_t { |
| 81 | // Not specified processor. |
| 82 | GK_NONE = 0, |
| 83 | |
| 84 | // R600-based processors. |
| 85 | GK_R600 = 1, |
| 86 | GK_R630 = 2, |
| 87 | GK_RS880 = 3, |
| 88 | GK_RV670 = 4, |
| 89 | GK_RV710 = 5, |
| 90 | GK_RV730 = 6, |
| 91 | GK_RV770 = 7, |
| 92 | GK_CEDAR = 8, |
| 93 | GK_CYPRESS = 9, |
| 94 | GK_JUNIPER = 10, |
| 95 | GK_REDWOOD = 11, |
| 96 | GK_SUMO = 12, |
| 97 | GK_BARTS = 13, |
| 98 | GK_CAICOS = 14, |
| 99 | GK_CAYMAN = 15, |
| 100 | GK_TURKS = 16, |
| 101 | |
| 102 | GK_R600_FIRST = GK_R600, |
| 103 | GK_R600_LAST = GK_TURKS, |
| 104 | |
| 105 | // AMDGCN-based processors. |
| 106 | GK_GFX600 = 32, |
| 107 | GK_GFX601 = 33, |
| 108 | |
| 109 | GK_GFX700 = 40, |
| 110 | GK_GFX701 = 41, |
| 111 | GK_GFX702 = 42, |
| 112 | GK_GFX703 = 43, |
| 113 | GK_GFX704 = 44, |
| 114 | |
| 115 | GK_GFX801 = 50, |
| 116 | GK_GFX802 = 51, |
| 117 | GK_GFX803 = 52, |
| 118 | GK_GFX810 = 53, |
| 119 | |
| 120 | GK_GFX900 = 60, |
| 121 | GK_GFX902 = 61, |
| 122 | GK_GFX904 = 62, |
| 123 | GK_GFX906 = 63, |
Andrew Walbran | 3d2c197 | 2020-04-07 12:24:26 +0100 | [diff] [blame] | 124 | GK_GFX908 = 64, |
Andrew Walbran | 16937d0 | 2019-10-22 13:54:20 +0100 | [diff] [blame] | 125 | GK_GFX909 = 65, |
Andrew Scull | 0372a57 | 2018-11-16 15:47:06 +0000 | [diff] [blame] | 126 | |
Andrew Walbran | 3d2c197 | 2020-04-07 12:24:26 +0100 | [diff] [blame] | 127 | GK_GFX1010 = 71, |
| 128 | GK_GFX1011 = 72, |
| 129 | GK_GFX1012 = 73, |
| 130 | |
Andrew Scull | 0372a57 | 2018-11-16 15:47:06 +0000 | [diff] [blame] | 131 | GK_AMDGCN_FIRST = GK_GFX600, |
Andrew Walbran | 3d2c197 | 2020-04-07 12:24:26 +0100 | [diff] [blame] | 132 | GK_AMDGCN_LAST = GK_GFX1012, |
Andrew Scull | 0372a57 | 2018-11-16 15:47:06 +0000 | [diff] [blame] | 133 | }; |
| 134 | |
| 135 | /// Instruction set architecture version. |
| 136 | struct IsaVersion { |
| 137 | unsigned Major; |
| 138 | unsigned Minor; |
| 139 | unsigned Stepping; |
| 140 | }; |
| 141 | |
| 142 | // This isn't comprehensive for now, just things that are needed from the |
| 143 | // frontend driver. |
| 144 | enum ArchFeatureKind : uint32_t { |
| 145 | FEATURE_NONE = 0, |
| 146 | |
| 147 | // These features only exist for r600, and are implied true for amdgcn. |
| 148 | FEATURE_FMA = 1 << 1, |
| 149 | FEATURE_LDEXP = 1 << 2, |
| 150 | FEATURE_FP64 = 1 << 3, |
| 151 | |
| 152 | // Common features. |
| 153 | FEATURE_FAST_FMA_F32 = 1 << 4, |
| 154 | FEATURE_FAST_DENORMAL_F32 = 1 << 5 |
| 155 | }; |
| 156 | |
| 157 | StringRef getArchNameAMDGCN(GPUKind AK); |
| 158 | StringRef getArchNameR600(GPUKind AK); |
| 159 | StringRef getCanonicalArchName(StringRef Arch); |
| 160 | GPUKind parseArchAMDGCN(StringRef CPU); |
| 161 | GPUKind parseArchR600(StringRef CPU); |
| 162 | unsigned getArchAttrAMDGCN(GPUKind AK); |
| 163 | unsigned getArchAttrR600(GPUKind AK); |
| 164 | |
| 165 | void fillValidArchListAMDGCN(SmallVectorImpl<StringRef> &Values); |
| 166 | void fillValidArchListR600(SmallVectorImpl<StringRef> &Values); |
| 167 | |
| 168 | IsaVersion getIsaVersion(StringRef GPU); |
| 169 | |
| 170 | } // namespace AMDGPU |
| 171 | |
Andrew Scull | 5e1ddfa | 2018-08-14 10:06:54 +0100 | [diff] [blame] | 172 | } // namespace llvm |
| 173 | |
| 174 | #endif |