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Sandrine Bailleux3cd87d72018-10-09 11:12:55 +02001/*
Alexei Fedorov7cc25872020-06-02 16:35:36 +01002 * Copyright (c) 2018-2020, Arm Limited. All rights reserved.
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/*******************************************************************************
8 * FVP specific definitions. Used only by FVP specific code.
9 ******************************************************************************/
10
11#ifndef __FVP_DEF_H__
12#define __FVP_DEF_H__
13
14#include <platform_def.h>
15
16/*******************************************************************************
17 * Cluster Topology definitions
18 ******************************************************************************/
Alexei Fedorov7cc25872020-06-02 16:35:36 +010019#ifndef FVP_CLUSTER_COUNT
20#error "FVP_CLUSTER_COUNT is not set in makefile"
21#endif
22
23#ifndef FVP_MAX_CPUS_PER_CLUSTER
24#error "FVP_MAX_CPUS_PER_CLUSTER is not set in makefile"
25#endif
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +020026
27/*******************************************************************************
28 * FVP memory map related constants
29 ******************************************************************************/
30
31#define DEVICE0_BASE 0x1a000000
32#define DEVICE0_SIZE 0x12200000
33
34#define DEVICE1_BASE 0x2f000000
35#define DEVICE1_SIZE 0x400000
36
37/*******************************************************************************
38 * GIC-400 & interrupt handling related constants
39 ******************************************************************************/
40/* Base FVP compatible GIC memory map */
41#define GICD_BASE 0x2f000000
42#define GICR_BASE 0x2f100000
43#define GICC_BASE 0x2c000000
44
45/*******************************************************************************
46 * PL011 related constants
47 ******************************************************************************/
48#define PL011_UART0_BASE 0x1c090000
Antonio Nino Diaz99f4fd22018-07-03 20:25:16 +010049#define PL011_UART1_BASE 0x1c0a0000
50#define PL011_UART2_BASE 0x1c0b0000
51#define PL011_UART3_BASE 0x1c0c0000
52
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +020053#define PL011_UART0_CLK_IN_HZ 24000000
Antonio Nino Diaz99f4fd22018-07-03 20:25:16 +010054#define PL011_UART1_CLK_IN_HZ 24000000
55#define PL011_UART2_CLK_IN_HZ 24000000
56#define PL011_UART3_CLK_IN_HZ 24000000
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +020057
58#define PLAT_ARM_UART_BASE PL011_UART0_BASE
59#define PLAT_ARM_UART_CLK_IN_HZ PL011_UART0_CLK_IN_HZ
60
61#endif /* __FVP_DEF_H__ */