| Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2018, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | /******************************************************************************* |
| 8 | * FVP specific definitions. Used only by FVP specific code. |
| 9 | ******************************************************************************/ |
| 10 | |
| 11 | #ifndef __FVP_DEF_H__ |
| 12 | #define __FVP_DEF_H__ |
| 13 | |
| 14 | #include <platform_def.h> |
| 15 | |
| 16 | /******************************************************************************* |
| 17 | * Cluster Topology definitions |
| 18 | ******************************************************************************/ |
| 19 | #define FVP_MAX_CPUS_PER_CLUSTER 4 |
| 20 | /* Currently the highest cluster count on the FVP is 4 (Quad cluster) */ |
| 21 | #define FVP_CLUSTER_COUNT 4 |
| 22 | /* Currently multi-threaded CPUs only have a single thread */ |
| 23 | #define FVP_MAX_PE_PER_CPU 1 |
| 24 | |
| 25 | /******************************************************************************* |
| 26 | * FVP memory map related constants |
| 27 | ******************************************************************************/ |
| 28 | |
| 29 | #define DEVICE0_BASE 0x1a000000 |
| 30 | #define DEVICE0_SIZE 0x12200000 |
| 31 | |
| 32 | #define DEVICE1_BASE 0x2f000000 |
| 33 | #define DEVICE1_SIZE 0x400000 |
| 34 | |
| 35 | /******************************************************************************* |
| 36 | * GIC-400 & interrupt handling related constants |
| 37 | ******************************************************************************/ |
| 38 | /* Base FVP compatible GIC memory map */ |
| 39 | #define GICD_BASE 0x2f000000 |
| 40 | #define GICR_BASE 0x2f100000 |
| 41 | #define GICC_BASE 0x2c000000 |
| 42 | |
| 43 | /******************************************************************************* |
| 44 | * PL011 related constants |
| 45 | ******************************************************************************/ |
| 46 | #define PL011_UART0_BASE 0x1c090000 |
| 47 | #define PL011_UART0_CLK_IN_HZ 24000000 |
| 48 | |
| 49 | #define PLAT_ARM_UART_BASE PL011_UART0_BASE |
| 50 | #define PLAT_ARM_UART_CLK_IN_HZ PL011_UART0_CLK_IN_HZ |
| 51 | |
| 52 | #endif /* __FVP_DEF_H__ */ |