| Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame] | 1 | /* |
| Ambroise Vincent | fae7772 | 2019-03-07 10:17:15 +0000 | [diff] [blame^] | 2 | * Copyright (c) 2018-2019, Arm Limited. All rights reserved. |
| Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch_helpers.h> |
| 8 | |
| 9 | void tftf_arch_setup(void) |
| 10 | { |
| 11 | /* Do not try to configure EL2 if TFTF is running at NS-EL1 */ |
| 12 | if (IS_IN_EL2()) { |
| Sandrine Bailleux | dddec6b | 2018-12-18 15:45:01 +0100 | [diff] [blame] | 13 | /* |
| 14 | * Route physical interrupts to EL2 regardless of the value of |
| 15 | * the IMO/FMO bits. Without this, interrupts would not be taken |
| 16 | * and would remain pending, regardless of the PSTATE.{A, I, F} |
| 17 | * interrupt masks. |
| 18 | */ |
| Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame] | 19 | write_hcr_el2(HCR_TGE_BIT); |
| Ambroise Vincent | fae7772 | 2019-03-07 10:17:15 +0000 | [diff] [blame^] | 20 | |
| 21 | /* |
| 22 | * Disable trap of SVE instructions to EL2. |
| 23 | * The fields of the CPTR_EL2 register reset to an |
| 24 | * architecturally UNKNOWN value. |
| 25 | */ |
| 26 | write_cptr_el2(CPTR_EL2_RES1); |
| Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame] | 27 | isb(); |
| 28 | } |
| 29 | } |