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review.trustedfirmware.org / TF-A / tf-a-tests.git / bbb1305abc89d5b88a4cefe374e05052f27d165c / . / include / drivers / arm / gic_common.h
blob: 71387f6dd985e9bd5c5dfa7fe2382e909c810770 [file] [log] [blame]
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]1/*
Marek Bykowskid6514442019-12-17 07:41:43 -0600[diff] [blame]2 * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __GIC_COMMON_H__
8#define __GIC_COMMON_H__
9
10/***************************************************************************
11 * Defines and prototypes common to GIC v2 and v3 drivers.
12 **************************************************************************/
13/* Distributor interface register offsets */
14#define GICD_CTLR 0x0
15#define GICD_TYPER 0x4
16#define GICD_ISENABLER 0x100
17#define GICD_ICENABLER 0x180
18#define GICD_ISPENDR 0x200
19#define GICD_ICPENDR 0x280
20#define GICD_ISACTIVER 0x300
21#define GICD_ICACTIVER 0x380
22#define GICD_IPRIORITYR 0x400
23#define GICD_ICFGR 0xC00
24
25/* Distributor interface register shifts */
26#define ISENABLER_SHIFT 5
27#define ICENABLER_SHIFT ISENABLER_SHIFT
28#define ISPENDR_SHIFT 5
29#define ICPENDR_SHIFT ISPENDR_SHIFT
30#define ISACTIVER_SHIFT 5
31#define ICACTIVER_SHIFT ISACTIVER_SHIFT
32#define IPRIORITYR_SHIFT 2
33#define ICFGR_SHIFT 4
34
35/* GICD_TYPER bit definitions */
36#define IT_LINES_NO_MASK 0x1f
37
38/* GICD Priority register mask */
39#define GIC_PRI_MASK 0xff
40
41/*
42 * Number of per-cpu interrupts to save prior to system suspend.
43 * This comprises all SGIs and PPIs.
44 */
45#define NUM_PCPU_INTR 32
46
47#ifndef __ASSEMBLY__
48
49#include <mmio.h>
50
51/* Helper to detect the GIC mode (GICv2 or GICv3) configured in the system */
52unsigned int is_gicv3_mode(void);
53
54/*******************************************************************************
55 * Private GIC Distributor function prototypes for use by GIC drivers
56 ******************************************************************************/
Marek Bykowskid6514442019-12-17 07:41:43 -0600[diff] [blame]57unsigned int gicd_read_isenabler(uintptr_t base, unsigned int interrupt_id);
58unsigned int gicd_read_icenabler(uintptr_t base, unsigned int interrupt_id);
59unsigned int gicd_read_ispendr(uintptr_t base, unsigned int interrupt_id);
60unsigned int gicd_read_icpendr(uintptr_t base, unsigned int interrupt_id);
61unsigned int gicd_read_isactiver(uintptr_t base, unsigned int interrupt_id);
62unsigned int gicd_read_icactiver(uintptr_t base, unsigned int interrupt_id);
63unsigned int gicd_read_ipriorityr(uintptr_t base, unsigned int interrupt_id);
64unsigned int gicd_get_ipriorityr(uintptr_t base, unsigned int interrupt_id);
65unsigned int gicd_read_icfgr(uintptr_t base, unsigned int interrupt_id);
66void gicd_write_isenabler(uintptr_t base, unsigned int interrupt_id,
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]67 unsigned int val);
Marek Bykowskid6514442019-12-17 07:41:43 -0600[diff] [blame]68void gicd_write_icenabler(uintptr_t base, unsigned int interrupt_id,
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]69 unsigned int val);
Marek Bykowskid6514442019-12-17 07:41:43 -0600[diff] [blame]70void gicd_write_ispendr(uintptr_t base, unsigned int interrupt_id,
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]71 unsigned int val);
Marek Bykowskid6514442019-12-17 07:41:43 -0600[diff] [blame]72void gicd_write_icpendr(uintptr_t base, unsigned int interrupt_id,
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]73 unsigned int val);
Marek Bykowskid6514442019-12-17 07:41:43 -0600[diff] [blame]74void gicd_write_isactiver(uintptr_t base, unsigned int interrupt_id,
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]75 unsigned int val);
Marek Bykowskid6514442019-12-17 07:41:43 -0600[diff] [blame]76void gicd_write_icactiver(uintptr_t base, unsigned int interrupt_id,
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]77 unsigned int val);
Marek Bykowskid6514442019-12-17 07:41:43 -0600[diff] [blame]78void gicd_write_ipriorityr(uintptr_t base, unsigned int interrupt_id,
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]79 unsigned int val);
Marek Bykowskid6514442019-12-17 07:41:43 -0600[diff] [blame]80void gicd_write_icfgr(uintptr_t base, unsigned int interrupt_id,
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]81 unsigned int val);
Marek Bykowskid6514442019-12-17 07:41:43 -0600[diff] [blame]82unsigned int gicd_get_isenabler(uintptr_t base, unsigned int interrupt_id);
83void gicd_set_isenabler(uintptr_t base, unsigned int interrupt_id);
84void gicd_set_icenabler(uintptr_t base, unsigned int interrupt_id);
85void gicd_set_ispendr(uintptr_t base, unsigned int interrupt_id);
86void gicd_set_icpendr(uintptr_t base, unsigned int interrupt_id);
87void gicd_set_isactiver(uintptr_t base, unsigned int interrupt_id);
88void gicd_set_icactiver(uintptr_t base, unsigned int interrupt_id);
89void gicd_set_ipriorityr(uintptr_t base, unsigned int interrupt_id,
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]90 unsigned int priority);
91
92/*******************************************************************************
93 * Private GIC Distributor interface accessors for reading and writing
94 * entire registers
95 ******************************************************************************/
Marek Bykowskid6514442019-12-17 07:41:43 -0600[diff] [blame]96static inline unsigned int gicd_read_ctlr(uintptr_t base)
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]97{
98 return mmio_read_32(base + GICD_CTLR);
99}
100
Marek Bykowskid6514442019-12-17 07:41:43 -0600[diff] [blame]101static inline unsigned int gicd_read_typer(uintptr_t base)
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]102{
103 return mmio_read_32(base + GICD_TYPER);
104}
105
Marek Bykowskid6514442019-12-17 07:41:43 -0600[diff] [blame]106static inline void gicd_write_ctlr(uintptr_t base, unsigned int val)
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]107{
108 mmio_write_32(base + GICD_CTLR, val);
109}
110
111
112#endif /*__ASSEMBLY__*/
113#endif /* __GIC_COMMON_H__ */