| Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2018, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef __GIC_COMMON_H__ |
| 8 | #define __GIC_COMMON_H__ |
| 9 | |
| 10 | /*************************************************************************** |
| 11 | * Defines and prototypes common to GIC v2 and v3 drivers. |
| 12 | **************************************************************************/ |
| 13 | /* Distributor interface register offsets */ |
| 14 | #define GICD_CTLR 0x0 |
| 15 | #define GICD_TYPER 0x4 |
| 16 | #define GICD_ISENABLER 0x100 |
| 17 | #define GICD_ICENABLER 0x180 |
| 18 | #define GICD_ISPENDR 0x200 |
| 19 | #define GICD_ICPENDR 0x280 |
| 20 | #define GICD_ISACTIVER 0x300 |
| 21 | #define GICD_ICACTIVER 0x380 |
| 22 | #define GICD_IPRIORITYR 0x400 |
| 23 | #define GICD_ICFGR 0xC00 |
| 24 | |
| 25 | /* Distributor interface register shifts */ |
| 26 | #define ISENABLER_SHIFT 5 |
| 27 | #define ICENABLER_SHIFT ISENABLER_SHIFT |
| 28 | #define ISPENDR_SHIFT 5 |
| 29 | #define ICPENDR_SHIFT ISPENDR_SHIFT |
| 30 | #define ISACTIVER_SHIFT 5 |
| 31 | #define ICACTIVER_SHIFT ISACTIVER_SHIFT |
| 32 | #define IPRIORITYR_SHIFT 2 |
| 33 | #define ICFGR_SHIFT 4 |
| 34 | |
| 35 | /* GICD_TYPER bit definitions */ |
| 36 | #define IT_LINES_NO_MASK 0x1f |
| 37 | |
| 38 | /* GICD Priority register mask */ |
| 39 | #define GIC_PRI_MASK 0xff |
| 40 | |
| 41 | /* |
| 42 | * Number of per-cpu interrupts to save prior to system suspend. |
| 43 | * This comprises all SGIs and PPIs. |
| 44 | */ |
| 45 | #define NUM_PCPU_INTR 32 |
| 46 | |
| 47 | #ifndef __ASSEMBLY__ |
| 48 | |
| 49 | #include <mmio.h> |
| 50 | |
| 51 | /* Helper to detect the GIC mode (GICv2 or GICv3) configured in the system */ |
| 52 | unsigned int is_gicv3_mode(void); |
| 53 | |
| 54 | /******************************************************************************* |
| 55 | * Private GIC Distributor function prototypes for use by GIC drivers |
| 56 | ******************************************************************************/ |
| 57 | unsigned int gicd_read_isenabler(unsigned int base, unsigned int interrupt_id); |
| 58 | unsigned int gicd_read_icenabler(unsigned int base, unsigned int interrupt_id); |
| 59 | unsigned int gicd_read_ispendr(unsigned int base, unsigned int interrupt_id); |
| 60 | unsigned int gicd_read_icpendr(unsigned int base, unsigned int interrupt_id); |
| 61 | unsigned int gicd_read_isactiver(unsigned int base, unsigned int interrupt_id); |
| 62 | unsigned int gicd_read_icactiver(unsigned int base, unsigned int interrupt_id); |
| 63 | unsigned int gicd_read_ipriorityr(unsigned int base, unsigned int interrupt_id); |
| 64 | unsigned int gicd_get_ipriorityr(unsigned int base, unsigned int interrupt_id); |
| 65 | unsigned int gicd_read_icfgr(unsigned int base, unsigned int interrupt_id); |
| 66 | void gicd_write_isenabler(unsigned int base, unsigned int interrupt_id, |
| 67 | unsigned int val); |
| 68 | void gicd_write_icenabler(unsigned int base, unsigned int interrupt_id, |
| 69 | unsigned int val); |
| 70 | void gicd_write_ispendr(unsigned int base, unsigned int interrupt_id, |
| 71 | unsigned int val); |
| 72 | void gicd_write_icpendr(unsigned int base, unsigned int interrupt_id, |
| 73 | unsigned int val); |
| 74 | void gicd_write_isactiver(unsigned int base, unsigned int interrupt_id, |
| 75 | unsigned int val); |
| 76 | void gicd_write_icactiver(unsigned int base, unsigned int interrupt_id, |
| 77 | unsigned int val); |
| 78 | void gicd_write_ipriorityr(unsigned int base, unsigned int interrupt_id, |
| 79 | unsigned int val); |
| 80 | void gicd_write_icfgr(unsigned int base, unsigned int interrupt_id, |
| 81 | unsigned int val); |
| 82 | unsigned int gicd_get_isenabler(unsigned int base, unsigned int interrupt_id); |
| 83 | void gicd_set_isenabler(unsigned int base, unsigned int interrupt_id); |
| 84 | void gicd_set_icenabler(unsigned int base, unsigned int interrupt_id); |
| 85 | void gicd_set_ispendr(unsigned int base, unsigned int interrupt_id); |
| 86 | void gicd_set_icpendr(unsigned int base, unsigned int interrupt_id); |
| 87 | void gicd_set_isactiver(unsigned int base, unsigned int interrupt_id); |
| 88 | void gicd_set_icactiver(unsigned int base, unsigned int interrupt_id); |
| 89 | void gicd_set_ipriorityr(unsigned int base, unsigned int interrupt_id, |
| 90 | unsigned int priority); |
| 91 | |
| 92 | /******************************************************************************* |
| 93 | * Private GIC Distributor interface accessors for reading and writing |
| 94 | * entire registers |
| 95 | ******************************************************************************/ |
| 96 | static inline unsigned int gicd_read_ctlr(unsigned int base) |
| 97 | { |
| 98 | return mmio_read_32(base + GICD_CTLR); |
| 99 | } |
| 100 | |
| 101 | static inline unsigned int gicd_read_typer(unsigned int base) |
| 102 | { |
| 103 | return mmio_read_32(base + GICD_TYPER); |
| 104 | } |
| 105 | |
| 106 | static inline void gicd_write_ctlr(unsigned int base, unsigned int val) |
| 107 | { |
| 108 | mmio_write_32(base + GICD_CTLR, val); |
| 109 | } |
| 110 | |
| 111 | |
| 112 | #endif /*__ASSEMBLY__*/ |
| 113 | #endif /* __GIC_COMMON_H__ */ |