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Andre Przywaraccd81f12022-11-21 17:04:10 +00001/*
2 * Copyright (c) 2022, ARM Limited. All rights reserved.
Varun Wadekar0ed3be62023-04-13 21:06:18 +01003 * Copyright (c) 2023, NVIDIA Corporation. All rights reserved.
Andre Przywaraccd81f12022-11-21 17:04:10 +00004 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Dispatch synchronous system register traps from lower ELs.
8 */
9
10#include <bl31/sync_handle.h>
11#include <context.h>
12
13int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx)
14{
Varun Wadekar0ed3be62023-04-13 21:06:18 +010015 uint64_t __unused opcode = esr_el3 & ISS_SYSREG_OPCODE_MASK;
16
Andre Przywara1ae75522022-11-21 17:07:25 +000017#if ENABLE_FEAT_RNG_TRAP
Varun Wadekar0ed3be62023-04-13 21:06:18 +010018 if ((opcode == ISS_SYSREG_OPCODE_RNDR) || (opcode == ISS_SYSREG_OPCODE_RNDRRS)) {
Andre Przywara1ae75522022-11-21 17:07:25 +000019 return plat_handle_rng_trap(esr_el3, ctx);
Andre Przywaraccd81f12022-11-21 17:04:10 +000020 }
Varun Wadekar0ed3be62023-04-13 21:06:18 +010021#endif
22
23#if IMPDEF_SYSREG_TRAP
24 if ((opcode & ISS_SYSREG_OPCODE_IMPDEF) == ISS_SYSREG_OPCODE_IMPDEF) {
25 return plat_handle_impdef_trap(esr_el3, ctx);
26 }
27#endif
28
29 return TRAP_RET_UNHANDLED;
Andre Przywaraccd81f12022-11-21 17:04:10 +000030}