blob: a9e894ce41267a312016ee0d600406ffe74b324e [file] [log] [blame]
Rouven Czerwinskie67497f2021-06-18 11:07:20 +02001/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
2/*
3 * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
4 * Copyright (C) 2021 Rouven Czerwinski, Pengutronix
5 */
6
7/dts-v1/;
8
9#include "stm32mp157.dtsi"
10#include "stm32mp15xc.dtsi"
11#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
12#include "stm32mp15xx-osd32.dtsi"
13#include "stm32mp15xxac-pinctrl.dtsi"
14
15/ {
16 model = "Linux Automation Test Automation Controller (TAC)";
17 compatible = "lxa,stm32mp157c-tac", "oct,stm32mp15xx-osd32", "st,stm32mp157";
18
19 aliases {
20 mmc1 = &sdmmc2;
21 serial0 = &uart4;
22 };
23
24
25 chosen {
26 stdout-path = &uart4;
27 };
28
29 led-controller-0 {
30 compatible = "gpio-leds";
31
32 led-0 {
33 label = "tac:green:user1";
34 gpios = <&gpiof 10 1>;
35 linux,default-trigger = "heartbeat";
36 };
37 };
38
39 reg_3v3: regulator_3v3 {
40 compatible = "regulator-fixed";
41 regulator-name = "3V3";
42 regulator-min-microvolt = <3300000>;
43 regulator-max-microvolt = <3300000>;
44 regulator-always-on;
45 vin-supply = <&v3v3>;
46 };
47};
48
49&pinctrl {
50 tac_sdmmc2_d47_pins_b: tac-sdmmc2-d47-1 {
51 pins {
52 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
53 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
54 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
55 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
56 slew-rate = <1>;
57 drive-push-pull;
58 bias-disable;
59 };
60 };
61};
62
63/* VCO = 624 MHz => P = 208, Q = 48, R = 104 */
64&pll3 {
65 st,pll = <&pll3_cfg2>;
66
67 pll3_cfg2: pll3-cfg2 {
68 st,pll_vco = <&pll3_vco_624Mhz>;
69 st,pll_div_pqr = <2 12 5>;
70 };
71};
72
73/* VCO = 750.0 MHz => P = 125, Q = 75, R = 62.5 */
74&pll4 {
75 st,pll = <&pll4_cfg2>;
76
77 pll4_cfg2: pll4-cfg2 {
78 st,pll_vco = <&pll4_vco_750Mhz>;
79 st,pll_div_pqr = <5 9 11>;
80 };
81};
82
83&rcc {
84 /* change parent clocks */
85 st,clksrc = <
86 CLK_MPU_PLL1P
87 CLK_AXI_PLL2P
88 CLK_MCU_PLL3P
89 CLK_RTC_LSE
90 CLK_MCO1_DISABLED
91 CLK_MCO2_DISABLED
92 CLK_CKPER_HSE
93 CLK_FMC_ACLK
94 CLK_QSPI_ACLK
95 CLK_ETH_PLL4P
96 CLK_SDMMC12_PLL3R
97 CLK_DSI_DSIPLL
98 CLK_STGEN_HSE
99 CLK_USBPHY_HSE
100 CLK_SPI2S1_PLL3Q
101 CLK_SPI2S23_PLL3Q
102 CLK_SPI45_HSI
103 CLK_SPI6_HSI
104 CLK_I2C46_HSI
105 CLK_SDMMC3_DISABLED
106 CLK_USBO_USBPHY
107 CLK_ADC_CKPER
108 CLK_CEC_DISABLED
109 CLK_I2C12_HSI
110 CLK_I2C35_HSI
111 CLK_UART1_HSI
112 CLK_UART24_HSI
113 CLK_UART35_HSI
114 CLK_UART6_HSI
115 CLK_UART78_HSI
116 CLK_SPDIF_DISABLED
117 CLK_FDCAN_PLL3Q
118 CLK_SAI1_DISABLED
119 CLK_SAI2_DISABLED
120 CLK_SAI3_DISABLED
121 CLK_SAI4_DISABLED
122 CLK_RNG1_LSI
123 CLK_RNG2_LSI
124 CLK_LPTIM1_PCLK1
125 CLK_LPTIM23_PCLK3
126 CLK_LPTIM45_LSE
127 >;
128
129 st,pll_vco {
130 pll3_vco_624Mhz: pll3-vco-624Mhz {
131 src = <CLK_PLL3_HSE>;
132 divmn = <1 51>;
133 };
134
135 pll4_vco_750Mhz: pll4-vco-750Mhz {
136 src = <CLK_PLL4_HSE>;
137 divmn = <3 124>;
138 };
139 };
140};
141
142&sdmmc2 {
143 pinctrl-names = "default";
144 pinctrl-0 = <&sdmmc2_b4_pins_a &tac_sdmmc2_d47_pins_b>;
145 bus-width = <8>;
146 mmc-ddr-3_3v;
147 no-1-8-v;
148 no-sd;
149 no-sdio;
150 non-removable;
151 st,neg-edge;
152 vmmc-supply = <&reg_3v3>;
153 status = "okay";
154};
155
156&uart4 {
157 pinctrl-names = "default";
158 pinctrl-0 = <&uart4_pins_a>;
159 status = "okay";
160};