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Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +01001#
Boyan Karatotev593ae352023-03-22 15:55:36 +00002# Copyright (c) 2016-2025, Arm Limited. All rights reserved.
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +01003#
dp-arm82cb2c12017-05-03 09:38:09 +01004# SPDX-License-Identifier: BSD-3-Clause
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +01005#
6
7# Default, static values for build variables, listed in alphabetic order.
8# Dependencies between build options, if any, are handled in the top-level
9# Makefile, after this file is included. This ensures that the former is better
10# poised to handle dependencies, as all build variables would have a default
11# value by then.
12
Antonio Nino Diaz8fd9d4d2018-08-08 16:28:43 +010013# Use T32 by default
14AARCH32_INSTRUCTION_SET := T32
15
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +010016# The AArch32 Secure Payload to be built as BL32 image
17AARCH32_SP := none
18
19# The Target build architecture. Supported values are: aarch64, aarch32.
20ARCH := aarch64
21
Alexei Fedorovf1821792020-12-07 16:38:53 +000022# ARM Architecture feature modifiers: none by default
23ARM_ARCH_FEATURE := none
24
Jeenu Viswambharanc877b412017-01-16 16:52:35 +000025# ARM Architecture major and minor versions: 8.0 by default.
26ARM_ARCH_MAJOR := 8
27ARM_ARCH_MINOR := 0
28
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +010029# Base commit to perform code check on
30BASE_COMMIT := origin/master
31
Roberto Vargasb1d27b42017-10-30 14:43:43 +000032# Execute BL2 at EL3
Arvind Ram Prakash42d4d3b2022-11-22 14:41:00 -060033RESET_TO_BL2 := 0
Roberto Vargasb1d27b42017-10-30 14:43:43 +000034
Balint Dobszay46789a72021-03-26 16:23:18 +010035# Only use SP packages if SP layout JSON is defined
36BL2_ENABLE_SP_LOAD := 0
37
Jiafei Pan7d173fc2018-03-21 07:20:09 +000038# BL2 image is stored in XIP memory, for now, this option is only supported
Arvind Ram Prakash42d4d3b2022-11-22 14:41:00 -060039# when RESET_TO_BL2 is 1.
Jiafei Pan7d173fc2018-03-21 07:20:09 +000040BL2_IN_XIP_MEM := 0
41
Hadi Asyrafib90f2072019-08-20 15:33:27 +080042# Do dcache invalidate upon BL2 entry at EL3
43BL2_INV_DCACHE := 1
44
Alexei Fedorov9fc59632019-05-24 12:17:09 +010045# Select the branch protection features to use.
46BRANCH_PROTECTION := 0
47
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +010048# By default, consider that the platform may release several CPUs out of reset.
49# The platform Makefile is free to override this value.
50COLD_BOOT_SINGLE_CPU := 0
51
Julius Werner3429c772017-06-09 15:17:15 -070052# Flag to compile in coreboot support code. Exclude by default. The coreboot
53# Makefile system will set this when compiling TF as part of a coreboot image.
54COREBOOT := 0
55
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +010056# For Chain of Trust
57CREATE_KEYS := 1
58
59# Build flag to include AArch32 registers in cpu context save and restore during
60# world switch. This flag must be set to 0 for AArch64-only platforms.
61CTX_INCLUDE_AARCH32_REGS := 1
62
63# Include FP registers in cpu context
64CTX_INCLUDE_FPREGS := 0
65
Madhukar Pappireddy42422622024-06-17 15:17:03 -050066# Include SVE registers in cpu context
67CTX_INCLUDE_SVE_REGS := 0
68
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +010069# Debug build
70DEBUG := 0
71
Sumit Garg7cda17b2019-11-15 10:43:00 +053072# By default disable authenticated decryption support.
73DECRYPTION_SUPPORT := none
74
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +010075# Build platform
76DEFAULT_PLAT := fvp
77
Christoph Müllner9e4609f2019-04-24 09:45:30 +020078# Disable the generation of the binary image (ELF only).
79DISABLE_BIN_GENERATION := 0
80
Soby Mathew209a60c2018-03-26 12:43:37 +010081# Enable capability to disable authentication dynamically. Only meant for
82# development platforms.
83DYN_DISABLE_AUTH := 0
84
Chris Kay68120782021-05-05 13:38:30 +010085# Enable the Maximum Power Mitigation Mechanism on supporting cores.
86ENABLE_MPMM := 0
87
Boyan Karatotev2b5e00d2024-12-19 16:07:29 +000088# Enable support for powerdown abandons
89FEAT_PABANDON := 0
90
Soby Mathew3bd17c02018-08-28 11:13:55 +010091# Flag to Enable Position Independant support (PIE)
92ENABLE_PIE := 0
93
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +010094# Flag to enable Performance Measurement Framework
95ENABLE_PMF := 0
96
97# Flag to enable PSCI STATs functionality
98ENABLE_PSCI_STAT := 0
99
100# Flag to enable runtime instrumentation using PMF
101ENABLE_RUNTIME_INSTRUMENTATION := 0
102
Douglas Raillard51faada2017-02-24 18:14:15 +0000103# Flag to enable stack corruption protection
104ENABLE_STACK_PROTECTOR := 0
105
Jeenu Viswambharan21b818c2017-09-22 08:32:10 +0100106# Flag to enable exception handling in EL3
107EL3_EXCEPTION_HANDLING := 0
108
Boyan Karatotev593ae352023-03-22 15:55:36 +0000109# Flag to include all errata for all CPUs TF-A implements workarounds for
110# Its supposed to be used only for testing.
111ENABLE_ERRATA_ALL := 0
112
Sumit Gargc6ba9b42019-11-14 16:33:45 +0530113# By default BL31 encryption disabled
114ENCRYPT_BL31 := 0
115
116# By default BL32 encryption disabled
117ENCRYPT_BL32 := 0
118
119# Default dummy firmware encryption key
120ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef
121
122# Default dummy nonce for firmware encryption
123ENC_NONCE := 1234567890abcdef12345678
124
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +0100125# Build flag to treat usage of deprecated platform and framework APIs as error.
126ERROR_DEPRECATED := 0
127
Jeenu Viswambharan1a7c1cf2017-12-08 12:13:51 +0000128# Fault injection support
129FAULT_INJECTION_SUPPORT := 0
130
Jayanth Dodderi Chidanand6a0da732022-01-17 18:57:17 +0000131# Flag to enable architectural features detection mechanism
132FEATURE_DETECTION := 0
133
Masahiro Yamada1c75d5d2016-12-25 13:52:22 +0900134# Byte alignment that each component in FIP is aligned to
135FIP_ALIGN := 0
136
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +0100137# Default FIP file name
138FIP_NAME := fip.bin
139
140# Default FWU_FIP file name
141FWU_FIP_NAME := fwu_fip.bin
142
Sumit Gargc6ba9b42019-11-14 16:33:45 +0530143# By default firmware encryption with SSK
144FW_ENC_STATUS := 0
145
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +0100146# For Chain of Trust
147GENERATE_COT := 0
148
AlexeiFedorovd7660842024-05-13 15:35:54 +0100149# Default number of 512 blocks per bitlock
150RME_GPT_BITLOCK_BLOCK := 1
151
AlexeiFedorovec0088b2024-03-13 17:07:03 +0000152# Default maximum size of GPT contiguous block
Soby Mathew01faa992024-08-22 11:53:09 +0100153RME_GPT_MAX_BLOCK := 512
AlexeiFedorovec0088b2024-03-13 17:07:03 +0000154
Jeenu Viswambharan74dce7f2017-09-22 08:32:09 +0100155# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By
156# default, they are for Secure EL1.
157GICV2_G0_FOR_EL3 := 0
158
Boyan Karatotev5d893412025-01-07 11:00:03 +0000159# Generic implementation of a GICvX driver
160USE_GIC_DRIVER := 0
161
Manish Pandey46cc41d2022-10-10 11:43:08 +0100162# Route NS External Aborts to EL3. Disabled by default; External Aborts are handled
Jeenu Viswambharan76454ab2017-11-30 12:54:15 +0000163# by lower ELs.
Manish Pandey46cc41d2022-10-10 11:43:08 +0100164HANDLE_EA_EL3_FIRST_NS := 0
Jeenu Viswambharan76454ab2017-11-30 12:54:15 +0000165
Raymond Mao3ba2c152023-07-25 07:53:35 -0700166# Enable Handoff protocol using transfer lists
167TRANSFER_LIST := 0
168
Levi Yun89535682024-05-13 10:24:31 +0100169# Enable HOB list to generate boot information
170HOB_LIST := 0
171
Bipin Ravi538516f2023-09-28 13:17:24 -0500172# Enables support for the gcc compiler option "-mharden-sls=all".
173# By default, disables all SLS hardening.
174HARDEN_SLS := 0
175
Alexei Fedorovae3cf1f2020-10-06 15:54:12 +0100176# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512.
177# The default value is sha256.
178HASH_ALG := sha256
179
Jeenu Viswambharan3c251af2017-01-04 13:51:42 +0000180# Whether system coherency is managed in hardware, without explicit software
181# operations.
182HW_ASSISTED_COHERENCY := 0
183
Varun Wadekar0ed3be62023-04-13 21:06:18 +0100184# Flag to enable trapping of implementation defined sytem registers
185IMPDEF_SYSREG_TRAP := 0
186
Soby Mathew20917552017-08-31 11:49:32 +0100187# Set the default algorithm for the generation of Trusted Board Boot keys
188KEY_ALG := rsa
189
Leonardo Sandovalee15a172020-06-18 17:32:55 -0500190# Set the default key size in case KEY_ALG is rsa
191ifeq ($(KEY_ALG),rsa)
192KEY_SIZE := 2048
193endif
194
Alexei Fedorov8c105292020-01-23 14:27:38 +0000195# Option to build TF with Measured Boot support
196MEASURED_BOOT := 0
197
Abhi.Singh36e3d872024-08-28 14:17:52 -0500198# Option to build TF with Discrete TPM support
199DISCRETE_TPM := 0
200
Tamas Bane7f11812023-06-07 13:35:04 +0200201# Option to enable the DICE Protection Environmnet as a Measured Boot backend
202DICE_PROTECTION_ENVIRONMENT :=0
203
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +0100204# NS timer register save and restore
205NS_TIMER_SWITCH := 0
206
Varun Wadekar77f1f7a2019-01-31 09:22:30 -0800207# Include lib/libc in the final image
208OVERRIDE_LIBC := 0
209
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +0100210# Build PL011 UART driver in minimal generic UART mode
211PL011_GENERIC_UART := 0
212
213# By default, consider that the platform's reset address is not programmable.
214# The platform Makefile is free to override this value.
215PROGRAMMABLE_RESET_ADDRESS := 0
216
Antonio Nino Diaz73308612019-02-28 13:35:21 +0000217# Flag used to choose the power state format: Extended State-ID or Original
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +0100218PSCI_EXTENDED_STATE_ID := 0
219
Wing Li64b47102023-01-26 18:33:36 -0800220# Enable PSCI OS-initiated mode support
221PSCI_OS_INIT_MODE := 0
222
Boyan Karatotev8db17052024-10-25 11:38:41 +0100223# SMCCC_ARCH_FEATURE_AVAILABILITY support
224ARCH_FEATURE_AVAILABILITY := 0
225
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +0100226# By default, BL1 acts as the reset handler, not BL31
227RESET_TO_BL31 := 0
228
229# For Chain of Trust
230SAVE_KEYS := 0
231
Jeenu Viswambharanb7cb1332017-10-16 08:43:14 +0100232# Software Delegated Exception support
johpow01dc78e622021-07-08 14:14:00 -0500233SDEI_SUPPORT := 0
Jeenu Viswambharanb7cb1332017-10-16 08:43:14 +0100234
Jayanth Dodderi Chidanand0b22e592022-10-11 17:16:07 +0100235# True Random Number firmware Interface support
johpow01dc78e622021-07-08 14:14:00 -0500236TRNG_SUPPORT := 0
Jimmy Brisson7dfb9912020-06-22 14:18:42 -0500237
Sona Mathewffea3842022-11-18 18:05:38 -0600238# Check to see if Errata ABI is supported
239ERRATA_ABI_SUPPORT := 0
240
Sona Mathewef63f5b2023-03-14 14:02:03 -0500241# Check to enable Errata ABI for platforms with non-arm interconnect
242ERRATA_NON_ARM_INTERCONNECT := 0
243
Jeremy Lintonc7a28aa2020-11-18 10:12:41 -0600244# SMCCC PCI support
johpow01dc78e622021-07-08 14:14:00 -0500245SMC_PCI_SUPPORT := 0
Jeremy Lintonc7a28aa2020-11-18 10:12:41 -0600246
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +0100247# Whether code and read-only data should be put on separate memory pages. The
248# platform Makefile is free to override this value.
249SEPARATE_CODE_AND_RODATA := 0
250
Samuel Hollandf8578e62018-10-17 21:40:18 -0500251# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a
252# separate memory region, which may be discontiguous from the rest of BL31.
253SEPARATE_NOBITS_REGION := 0
254
Jiafei Pan96a8ed12022-02-24 10:47:33 +0800255# Put BL2 NOLOAD sections (.bss, stacks, page tables) in a separate memory
256# region, platform Makefile is free to override this value.
257SEPARATE_BL2_NOLOAD_REGION := 0
258
Ye Li86acbbe2022-08-26 13:48:31 +0800259# Put RW DATA sections (.rwdata) in a separate memory region, which may be
260# discontiguous from the rest of BL31.
261SEPARATE_RWDATA_REGION := 0
262
Madhukar Pappireddy308ebfa2024-06-17 15:26:00 -0500263# Put SIMD context data structures in a separate memory region. Platforms
264# have the choice to put it outside of default BSS region of EL3 firmware.
265SEPARATE_SIMD_SECTION := 0
266
Daniel Boulby1dcc28c2018-09-18 11:45:51 +0100267# If the BL31 image initialisation code is recalimed after use for the secondary
268# cores stack
269RECLAIM_INIT_CODE := 0
270
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +0100271# SPD choice
272SPD := none
273
Paul Beesley3f3c3412019-09-16 11:29:03 +0000274# Enable the Management Mode (MM)-based Secure Partition Manager implementation
275SPM_MM := 0
Antonio Nino Diaz2d7b9e52018-10-30 11:08:08 +0000276
Marc Bonnici1d63ae42021-12-01 18:00:40 +0000277# Use the FF-A SPMC implementation in EL3.
278SPMC_AT_EL3 := 0
279
Nishant Sharma801cd3c2023-06-27 00:36:01 +0100280# Enable SEL0 SP when SPMC is enabled at EL3
281SPMC_AT_EL3_SEL0_SP :=0
282
Max Shvetsov033039f2020-02-25 13:55:00 +0000283# Use SPM at S-EL2 as a default config for SPMD
284SPMD_SPM_AT_SEL2 := 1
285
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +0100286# Flag to introduce an infinite loop in BL1 just before it exits into the next
287# image. This is meant to help debugging the post-BL2 phase.
288SPIN_ON_BL1_EXIT := 0
289
290# Flags to build TF with Trusted Boot support
291TRUSTED_BOARD_BOOT := 0
292
Antonio Nino Diaze23e0572018-09-25 09:41:08 +0100293# Build option to choose whether Trusted Firmware uses Coherent memory or not.
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +0100294USE_COHERENT_MEM := 1
295
Olivier Deprez0ca39132019-09-19 17:46:46 +0200296# Build option to add debugfs support
297USE_DEBUGFS := 0
298
Louis Mayencourt0a6e7e32019-10-24 15:18:46 +0100299# Build option to fconf based io
Balint Dobszaycbf9e842019-12-18 15:28:00 +0100300ARM_IO_IN_DTB := 0
301
302# Build option to support SDEI through fconf
Madhukar Pappireddy452d5e52020-06-02 09:26:30 -0500303SDEI_IN_FCONF := 0
304
305# Build option to support Secure Interrupt descriptors through fconf
306SEC_INT_DESC_IN_FCONF := 0
Louis Mayencourt0a6e7e32019-10-24 15:18:46 +0100307
Antonio Nino Diaze23e0572018-09-25 09:41:08 +0100308# Build option to choose whether Trusted Firmware uses library at ROM
309USE_ROMLIB := 0
Roberto Vargas5accce52018-05-22 16:05:42 +0100310
Petre-Ionut Tudor60e8f3c2019-11-07 15:18:03 +0000311# Build option to choose whether the xlat tables of BL images can be read-only.
312# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES,
313# which is the per BL-image option that actually enables the read-only tables
314# API. The reason for having this additional option is to have a common high
315# level makefile where we can check for incompatible features/build options.
316ALLOW_RO_XLAT_TABLES := 0
317
Sandrine Bailleux3bff9102020-01-15 10:23:25 +0100318# Chain of trust.
319COT := tbbr
320
Masahiro Yamadabb41eb72017-05-22 12:11:24 +0900321# Use tbbr_oid.h instead of platform_oid.h
Antonio Nino Diaze23e0572018-09-25 09:41:08 +0100322USE_TBBR_DEFS := 1
Masahiro Yamadabb41eb72017-05-22 12:11:24 +0900323
Soby Mathewbcc3c492017-04-10 22:35:42 +0100324# Whether to enable D-Cache early during warm boot. This is usually
325# applicable for platforms wherein interconnect programming is not
326# required to enable cache coherency after warm reset (eg: single cluster
327# platforms).
328WARMBOOT_ENABLE_DCACHE_EARLY := 0
dp-armd832aee2017-05-23 09:32:49 +0100329
Mark Brownbebcf272022-04-20 18:14:32 +0100330# Default SVE vector length to maximum architected value
331SVE_VECTOR_LEN := 2048
332
Justin Chadwell1f461972019-08-20 11:01:52 +0100333SANITIZE_UB := off
Soby Mathewc97cba42019-09-25 14:03:41 +0100334
335# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock
336# implementation variant using the ARMv8.1-LSE compare-and-swap instruction.
337# Default: disabled
338USE_SPINLOCK_CAS := 0
zelalem-awekeedbce9a2019-11-12 16:20:17 -0600339
340# Enable Link Time Optimization
341ENABLE_LTO := 0
Max Shvetsov28f39f02020-02-25 13:56:19 +0000342
Govindraj Rajaf1910cc2022-11-21 13:10:40 +0000343# This option will include EL2 registers in cpu context save and restore during
344# EL2 firmware entry/exit. Internal flag not meant for direct setting.
345# Use SPD=spmd and SPMD_SPM_AT_SEL2=1 or ENABLE_RME=1 to enable
346# CTX_INCLUDE_EL2_REGS.
Max Shvetsov28f39f02020-02-25 13:56:19 +0000347CTX_INCLUDE_EL2_REGS := 0
Manish V Badarkhe7ff088d2020-03-22 05:06:38 +0000348
349# Enable Memory tag extension which is supported for architecture greater
350# than Armv8.5-A
351# By default it is set to "no"
352SUPPORT_STACK_MEMTAG := no
Manish V Badarkhe45aecff2020-04-28 04:53:32 +0100353
354# Select workaround for AT speculative behaviour.
johpow01dc78e622021-07-08 14:14:00 -0500355ERRATA_SPECULATIVE_AT := 0
Varun Wadekarfbc44bd2020-06-12 10:11:28 -0700356
Boyan Karatotev45c73282024-09-20 13:37:51 +0100357# select workaround for SME aborting powerdown
358ERRATA_SME_POWER_DOWN := 0
359
Manish Pandey00e8f792022-09-27 14:30:34 +0100360# Trap RAS error record access from Non secure
361RAS_TRAP_NS_ERR_REC_ACCESS := 0
Manish V Badarkhe84ef9cd2020-06-29 10:32:53 +0100362
363# Build option to create cot descriptors using fconf
364COT_DESC_IN_DTB := 0
Manish V Badarkhe582e4e72020-07-29 10:58:44 +0100365
Juan Pablo Condecf2dd172022-10-25 19:41:02 -0400366# Build option to provide OpenSSL directory path
Manish V Badarkhe582e4e72020-07-29 10:58:44 +0100367OPENSSL_DIR := /usr
Madhukar Pappireddyfddfb3b2020-08-12 13:18:19 -0500368
Salome Thirote95abc42022-07-14 16:14:15 +0100369# Select the openssl binary provided in OPENSSL_DIR variable
370ifeq ("$(wildcard ${OPENSSL_DIR}/bin)", "")
371 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/apps
372else
373 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/bin
374endif
375
Madhukar Pappireddyfddfb3b2020-08-12 13:18:19 -0500376# Build option to use the SP804 timer instead of the generic one
377USE_SP804_TIMER := 0
Manish V Badarkhe5357f832021-03-16 10:01:27 +0000378
379# Build option to define number of firmware banks, used in firmware update
380# metadata structure.
381NR_OF_FW_BANKS := 2
382
383# Build option to define number of images in firmware bank, used in firmware
384# update metadata structure.
385NR_OF_IMAGES_IN_FW_BANK := 1
Manish V Badarkhe396b3392021-06-25 23:28:59 +0100386
387# Disable Firmware update support by default
388PSA_FWU_SUPPORT := 0
Manish V Badarkhe813524e2021-07-02 09:10:56 +0100389
Sughosh Ganu11d05a72024-02-01 12:51:20 +0530390# Enable image description in FWU metadata by default when PSA_FWU_SUPPORT
391# is enabled.
392ifeq ($(PSA_FWU_SUPPORT),1)
393PSA_FWU_METADATA_FW_STORE_DESC := 1
394else
395PSA_FWU_METADATA_FW_STORE_DESC := 0
396endif
397
Manish V Badarkhe00e28872022-03-02 12:06:35 +0000398# Dynamic Root of Trust for Measurement support
399DRTM_SUPPORT := 0
Okash Khawaja04c73032022-11-04 12:38:01 +0000400
401# Check platform if cache management operations should be performed.
402# Disabled by default.
403CONDITIONAL_CMO := 0
Raghu Krishnamurthy890b5082023-02-25 13:26:10 -0800404
405# By default, disable SPMD Logical partitions
406ENABLE_SPMD_LP := 0
Manish V Badarkhe5782b892023-09-06 09:08:28 +0100407
408# By default, disable PSA crypto (use MbedTLS legacy crypto API).
409PSA_CRYPTO := 0
Sandrine Bailleux85bebe12023-10-11 08:38:00 +0200410
411# getc() support from the console(s).
412# Disabled by default because it constitutes an attack vector into TF-A. It
413# should only be enabled if there is a use case for it.
414ENABLE_CONSOLE_GETC := 0
Arvind Ram Prakash183329a2023-08-15 16:28:06 -0500415
416# Build option to disable EL2 when it is not used.
417# Most platforms switch from EL3 to NS-EL2 and hence the unused NS-EL2
418# functions must be enabled by platforms if they require it.
419# Disabled by default.
420INIT_UNUSED_NS_EL2 := 0
Arvind Ram Prakash9acff282023-10-06 14:35:21 -0500421
422# Disable including MPAM EL2 registers in context by default since currently
423# it's only enabled for NS world
424CTX_INCLUDE_MPAM_REGS := 0
Juan Pablo Condebfef8b92023-11-08 16:14:28 -0600425
426# Enable context memory usage reporting during BL31 setup.
427PLATFORM_REPORT_CTX_MEM_USE := 0
Yann Gautierae770fe2024-01-16 19:39:31 +0100428
429# Enable early console
430EARLY_CONSOLE := 0
Arvind Ram Prakashf99a69c2023-12-21 00:25:52 -0600431
432# Allow platforms to save/restore DSU PMU registers over a power cycle.
433# Disabled by default and must be enabled by individual platforms.
434PRESERVE_DSU_PMU_REGS := 0
Raghu Krishnamurthy6a88ec82024-06-03 19:02:29 -0700435
436# Enable RMMD to forward attestation requests from RMM to EL3.
437RMMD_ENABLE_EL3_TOKEN_SIGN := 0
Sona Mathew2132c702025-03-14 01:27:11 -0500438
439# Enable RMMD to program and manage IDE Keys at the PCIe Root Port(RP).
440# This flag is temporary and it is expected once the interface is
441# finalized, this flag will be removed.
442RMMD_ENABLE_IDE_KEY_PROG := 0