fdts/tc3.dts

/*
 * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <platform_def.h>

#define MHU_TX_ADDR			46040000 /* hex */
#define MHU_RX_ADDR			46140000 /* hex */

#define LIT_CPU_PMU_COMPATIBLE		"arm,cortex-a520-pmu"
#define MID_CPU_PMU_COMPATIBLE		"arm,cortex-a725-pmu"
#define BIG_CPU_PMU_COMPATIBLE		"arm,cortex-x925-pmu"

#include "tc-common.dtsi"
#if TARGET_FLAVOUR_FVP
#include "tc-fvp.dtsi"
#else
#include "tc-fpga.dtsi"
#endif /* TARGET_FLAVOUR_FVP */
#include "tc3-4-base.dtsi"

/ {
	cs-pmu@0 {
		compatible = "arm,coresight-pmu";
		reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>;
	};

	cs-pmu@1 {
		compatible = "arm,coresight-pmu";
		reg = <0x0 MCN_PMU_ADDR(1) 0x0 0xffc>;
	};

	cs-pmu@2 {
		compatible = "arm,coresight-pmu";
		reg = <0x0 MCN_PMU_ADDR(2) 0x0 0xffc>;
	};

	cs-pmu@3 {
		compatible = "arm,coresight-pmu";
		reg = <0x0 MCN_PMU_ADDR(3) 0x0 0xffc>;
	};

	spe-pmu-mid {
		status = "okay";
	};

	spe-pmu-big {
		status = "okay";
	};

	dsu-pmu {
		compatible = "arm,dsu-pmu";
		cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
	};

	ni-pmu {
		compatible = "arm,ni-tower";
		reg = <0x0 0x4f000000 0x0 0x4000000>;
	};

#if TARGET_FLAVOUR_FVP
	smmu_700: iommu@3f000000 {
		status = "okay";
	};

	smmu_700_dpu: iommu@4002a00000 {
		status = "okay";
	};
#else
	smmu_600: smmu@2ce00000 {
		status = "okay";
	};
#endif

	dp0: display@DPU_ADDR {
#if TARGET_FLAVOUR_FVP
		iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>,
			 <&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>;
#else /* TARGET_FLAVOUR_FPGA */
		iommus = <&smmu_600 0>, <&smmu_600 1>, <&smmu_600 2>, <&smmu_600 3>,
			 <&smmu_600 4>, <&smmu_600 5>, <&smmu_600 6>, <&smmu_600 7>,
			 <&smmu_600 8>, <&smmu_600 9>;
#endif
	};

	gpu: gpu@2d000000 {
#if TARGET_FLAVOUR_FVP
		iommus = <&smmu_700 0x200>;
#endif
	};
};