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Radoslaw Biernacki558a6f42018-05-17 22:52:49 +02001#
Marcin Juszkiewiczc681d022023-05-10 10:03:01 +02002# Copyright (c) 2019-2023, Linaro Limited and Contributors. All rights reserved.
Radoslaw Biernacki558a6f42018-05-17 22:52:49 +02003#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
Marcin Juszkiewicz886688d2023-07-24 21:08:16 +02007PLAT_QEMU_PATH := plat/qemu/qemu_sbsa
8PLAT_QEMU_COMMON_PATH := plat/qemu/common
9
Marcin Juszkiewicza63cdc72023-07-24 20:56:29 +020010include plat/qemu/common/common.mk
Chris Kay1fa05da2021-09-28 15:52:14 +010011
Radoslaw Biernacki558a6f42018-05-17 22:52:49 +020012CRASH_REPORTING := 1
13
Masahisa Kojima6a2426a2020-06-11 21:46:44 +090014ifeq (${SPM_MM},1)
15NEED_BL32 := yes
16EL3_EXCEPTION_HANDLING := 1
17GICV2_G0_FOR_EL3 := 1
18endif
19
Radoslaw Biernacki558a6f42018-05-17 22:52:49 +020020# Enable new version of image loading on QEMU platforms
21LOAD_IMAGE_V2 := 1
22
Chen Baozi226f4c82023-02-22 06:58:39 +000023CTX_INCLUDE_AARCH32_REGS := 0
24ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
25$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
26endif
27
Radoslaw Biernacki558a6f42018-05-17 22:52:49 +020028ifeq ($(NEED_BL32),yes)
29$(eval $(call add_define,QEMU_LOAD_BL32))
30endif
31
Chen Baozi226f4c82023-02-22 06:58:39 +000032# Treating this as a memory-constrained port for now
33USE_COHERENT_MEM := 0
34
35# This can be overridden depending on CPU(s) used in the QEMU image
36HW_ASSISTED_COHERENCY := 1
37
Marcin Juszkiewicz71f53592023-07-24 21:18:51 +020038BL2_SOURCES += $(LIBFDT_SRCS)
Radoslaw Biernacki558a6f42018-05-17 22:52:49 +020039
Alexei Fedorova6ea06f2020-03-23 18:45:17 +000040# Include GICv3 driver files
41include drivers/arm/gic/v3/gicv3.mk
42
43QEMU_GIC_SOURCES := ${GICV3_SOURCES} \
Marcin Juszkiewicz1e67b1b2023-05-15 11:07:54 +020044 plat/common/plat_gicv3.c
Radoslaw Biernacki558a6f42018-05-17 22:52:49 +020045
Marcin Juszkiewicz18884752023-07-24 21:37:00 +020046BL31_SOURCES += ${PLAT_QEMU_PATH}/sbsa_gic.c \
Graeme Gregory2fb5ed42020-08-28 18:03:35 +010047 ${PLAT_QEMU_PATH}/sbsa_pm.c \
Marcin Juszkiewiczc681d022023-05-10 10:03:01 +020048 ${PLAT_QEMU_PATH}/sbsa_sip_svc.c \
Marcin Juszkiewicz18884752023-07-24 21:37:00 +020049 ${PLAT_QEMU_PATH}/sbsa_topology.c
Chris Kay1fa05da2021-09-28 15:52:14 +010050
51BL31_SOURCES += ${FDT_WRAPPERS_SOURCES}
52
Masahisa Kojima6a2426a2020-06-11 21:46:44 +090053ifeq (${SPM_MM},1)
54 BL31_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_spm.c
55endif
Radoslaw Biernacki558a6f42018-05-17 22:52:49 +020056
57SEPARATE_CODE_AND_RODATA := 1
58ENABLE_STACK_PROTECTOR := 0
Radoslaw Biernacki558a6f42018-05-17 22:52:49 +020059
60MULTI_CONSOLE_API := 1
61
62# Disable the PSCI platform compatibility layer
63ENABLE_PLAT_COMPAT := 0
64
65# Use known base for UEFI if not given from command line
66# By default BL33 is at FLASH1 base
67PRELOADED_BL33_BASE ?= 0x10000000
68
69# Qemu SBSA plafrom only support SEC_SRAM
70BL32_RAM_LOCATION_ID = SEC_SRAM_ID
71$(eval $(call add_define,BL32_RAM_LOCATION_ID))
72
Andrew Walbran74464d52020-01-15 14:11:31 +000073# Don't have the Linux kernel as a BL33 image by default
74ARM_LINUX_KERNEL_AS_BL33 := 0
75$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33))
76$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
77
78ARM_PRELOADED_DTB_BASE := PLAT_QEMU_DT_BASE
79$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
80
Marcin Juszkiewicz9bff7ce2022-11-16 14:47:51 +010081# Later QEMU versions support SME and SVE.
Jayanth Dodderi Chidanandfc259b62023-03-31 10:42:10 +010082ENABLE_SVE_FOR_NS := 2
83ENABLE_SME_FOR_NS := 2
Marcin Juszkiewiczc5986922023-02-14 09:27:59 +010084
85# QEMU 7.2+ has support for FGT and Linux needs it enabled to boot on max
86ENABLE_FEAT_FGT := 2