blob: 0f665540987d248eaa7a301f68b451a711867b43 [file] [log] [blame]
Amit Nagalc97857d2024-06-05 12:32:38 +05301/*
2 * Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8#include <errno.h>
9#include <inttypes.h>
10
11#include <drivers/scmi-msg.h>
12#include <drivers/scmi.h>
13#include <lib/utils_def.h>
14#include <platform_def.h>
15#include <scmi.h>
16
17#include "plat_private.h"
18
19#define HIGH (1)
20#define LOW (0)
21
22struct scmi_clk {
23 unsigned long clock_id;
24 unsigned long rate;
25 const char *name;
26 bool enabled;
27};
28
29#define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled, _rate) \
30 [_scmi_id] = { \
31 .clock_id = (_id), \
32 .name = (_name), \
33 .enabled = (_init_enabled), \
34 .rate = (_rate), \
35 }
36
37static struct scmi_clk scmi0_clock[] = {
38 CLOCK_CELL(CLK_GEM0_0, CLK_GEM0_0, "gem0_pclk", true, 100000000),
39 CLOCK_CELL(CLK_GEM0_1, CLK_GEM0_1, "gem0_hclk", true, 100000000),
40 CLOCK_CELL(CLK_GEM0_2, CLK_GEM0_2, "gem0_tx_clk", true, 125000000),
41 CLOCK_CELL(CLK_GEM0_3, CLK_GEM0_3, "gem0_rx_clk", true, 100000000),
42 CLOCK_CELL(CLK_GEM0_4, CLK_GEM0_4, "gem0_tsu_clk", true, 100000000),
43 CLOCK_CELL(CLK_GEM1_0, CLK_GEM1_0, "gem1_pclk", true, 100000000),
44 CLOCK_CELL(CLK_GEM1_1, CLK_GEM1_1, "gem1_hclk", true, 100000000),
45 CLOCK_CELL(CLK_GEM1_2, CLK_GEM1_2, "gem1_tx_clk", true, 125000000),
46 CLOCK_CELL(CLK_GEM1_3, CLK_GEM1_3, "gem1_rx_clk", true, 100000000),
47 CLOCK_CELL(CLK_GEM1_4, CLK_GEM1_4, "gem1_tsu_clk", true, 100000000),
48 CLOCK_CELL(CLK_SERIAL0_0, CLK_SERIAL0_0, "uart0_uartclk", true, 100000000),
49 CLOCK_CELL(CLK_SERIAL0_1, CLK_SERIAL0_1, "uart0_apb_pclk", true, 100000000),
50 CLOCK_CELL(CLK_SERIAL1_0, CLK_SERIAL1_0, "uart1_uartclk", true, 100000000),
51 CLOCK_CELL(CLK_SERIAL1_1, CLK_SERIAL1_1, "uart1_apb_pclk", true, 100000000),
52 CLOCK_CELL(CLK_UFS0_0, CLK_UFS0_0, "ufs_core_clk", true, 100000000),
53 CLOCK_CELL(CLK_UFS0_1, CLK_UFS0_1, "ufs_phy_clk", true, 100000000),
54 CLOCK_CELL(CLK_UFS0_2, CLK_UFS0_2, "ufs_ref_pclk", true, 100000000),
55 CLOCK_CELL(CLK_USB0_0, CLK_USB0_0, "usb0_bus_clk", true, 100000000),
56 CLOCK_CELL(CLK_USB0_1, CLK_USB0_1, "usb0_ref_clk", true, 100000000),
57 CLOCK_CELL(CLK_USB0_2, CLK_USB0_2, "usb0_dwc_clk", true, 100000000),
58 CLOCK_CELL(CLK_USB1_0, CLK_USB1_0, "usb1_bus_clk", true, 100000000),
59 CLOCK_CELL(CLK_USB1_1, CLK_USB1_1, "usb1_ref_clk", true, 100000000),
60 CLOCK_CELL(CLK_USB1_2, CLK_USB1_2, "usb1_dwc_clk", true, 100000000),
61 CLOCK_CELL(CLK_MMC0_0, CLK_MMC0_0, "mmc0_xin_clk", true, 100000000),
62 CLOCK_CELL(CLK_MMC0_1, CLK_MMC0_1, "mmc0_ahb_clk", true, 100000000),
63 CLOCK_CELL(CLK_MMC0_2, CLK_MMC0_2, "mmc0_gate_clk", true, 100000000),
64 CLOCK_CELL(CLK_MMC1_0, CLK_MMC1_0, "mmc1_xin_clk", true, 100000000),
65 CLOCK_CELL(CLK_MMC1_1, CLK_MMC1_1, "mmc1_ahb_clk", true, 100000000),
66 CLOCK_CELL(CLK_MMC1_2, CLK_MMC1_2, "mmc1_gate_clk", true, 100000000),
67 CLOCK_CELL(CLK_TTC0_0, CLK_TTC0_0, "ttc0_clk", true, 100000000),
68 CLOCK_CELL(CLK_TTC1_0, CLK_TTC1_0, "ttc1_clk", true, 100000000),
69 CLOCK_CELL(CLK_TTC2_0, CLK_TTC2_0, "ttc2_clk", true, 100000000),
70 CLOCK_CELL(CLK_TTC3_0, CLK_TTC3_0, "ttc3_clk", true, 100000000),
71 CLOCK_CELL(CLK_TTC4_0, CLK_TTC4_0, "ttc4_clk", true, 100000000),
72 CLOCK_CELL(CLK_TTC5_0, CLK_TTC5_0, "ttc5_clk", true, 100000000),
73 CLOCK_CELL(CLK_TTC6_0, CLK_TTC6_0, "ttc6_clk", true, 100000000),
74 CLOCK_CELL(CLK_TTC7_0, CLK_TTC7_0, "ttc7_clk", true, 100000000),
75 CLOCK_CELL(CLK_I2C0_0, CLK_I2C0_0, "i2c0_clk", true, 100000000),
76 CLOCK_CELL(CLK_I2C1_0, CLK_I2C1_0, "i2c1_clk", true, 100000000),
77 CLOCK_CELL(CLK_I2C2_0, CLK_I2C2_0, "i2c2_clk", true, 100000000),
78 CLOCK_CELL(CLK_I2C3_0, CLK_I2C3_0, "i2c3_clk", true, 100000000),
79 CLOCK_CELL(CLK_I2C4_0, CLK_I2C4_0, "i2c4_clk", true, 100000000),
80 CLOCK_CELL(CLK_I2C5_0, CLK_I2C5_0, "i2c5_clk", true, 100000000),
81 CLOCK_CELL(CLK_I2C6_0, CLK_I2C6_0, "i2c6_clk", true, 100000000),
82 CLOCK_CELL(CLK_I2C7_0, CLK_I2C7_0, "i2c7_clk", true, 100000000),
83 CLOCK_CELL(CLK_OSPI0_0, CLK_OSPI0_0, "ospi0_clk", true, 100000000),
84 CLOCK_CELL(CLK_QSPI0_0, CLK_QSPI0_0, "qpsi0_ref_clk", true, 100000000),
85 CLOCK_CELL(CLK_QSPI0_1, CLK_QSPI0_1, "qspi0_pclk", true, 100000000),
86 CLOCK_CELL(CLK_WWDT0_0, CLK_WWDT0_0, "wwdt0_clk", true, 100000000),
87 CLOCK_CELL(CLK_WWDT1_0, CLK_WWDT1_0, "wwdt1_clk", true, 100000000),
88 CLOCK_CELL(CLK_WWDT2_0, CLK_WWDT2_0, "wwdt2_clk", true, 100000000),
89 CLOCK_CELL(CLK_WWDT3_0, CLK_WWDT3_0, "wwdt3_clk", true, 100000000),
90 CLOCK_CELL(CLK_ADMA0_0, CLK_ADMA0_0, "adma0_main_clk", true, 100000000),
91 CLOCK_CELL(CLK_ADMA0_1, CLK_ADMA0_1, "adma0_apb_clk", true, 100000000),
92 CLOCK_CELL(CLK_ADMA1_0, CLK_ADMA1_0, "adma1_main_clk", true, 100000000),
93 CLOCK_CELL(CLK_ADMA1_1, CLK_ADMA1_1, "adma1_apb_clk", true, 100000000),
94 CLOCK_CELL(CLK_ADMA2_0, CLK_ADMA2_0, "adma2_main_clk", true, 100000000),
95 CLOCK_CELL(CLK_ADMA2_1, CLK_ADMA2_1, "adma2_apb_clk", true, 100000000),
96 CLOCK_CELL(CLK_ADMA3_0, CLK_ADMA3_0, "adma3_main_clk", true, 100000000),
97 CLOCK_CELL(CLK_ADMA3_1, CLK_ADMA3_1, "adma3_apb_clk", true, 100000000),
98 CLOCK_CELL(CLK_ADMA4_0, CLK_ADMA4_0, "adma4_main_clk", true, 100000000),
99 CLOCK_CELL(CLK_ADMA4_1, CLK_ADMA4_1, "adma4_apb_clk", true, 100000000),
100 CLOCK_CELL(CLK_ADMA5_0, CLK_ADMA5_0, "adma5_main_clk", true, 100000000),
101 CLOCK_CELL(CLK_ADMA5_1, CLK_ADMA5_1, "adma5_apb_clk", true, 100000000),
102 CLOCK_CELL(CLK_ADMA6_0, CLK_ADMA6_0, "adma6_main_clk", true, 100000000),
103 CLOCK_CELL(CLK_ADMA6_1, CLK_ADMA6_1, "adma6_apb_clk", true, 100000000),
104 CLOCK_CELL(CLK_ADMA7_0, CLK_ADMA7_0, "adma7_main_clk", true, 100000000),
105 CLOCK_CELL(CLK_ADMA7_1, CLK_ADMA7_1, "adma7_apb_clk", true, 100000000),
106 CLOCK_CELL(CLK_CAN0_0, CLK_CAN0_0, "can0_can_clk", true, 100000000),
107 CLOCK_CELL(CLK_CAN0_1, CLK_CAN0_1, "can0_axi_clk", true, 100000000),
108 CLOCK_CELL(CLK_CAN1_0, CLK_CAN1_0, "can1_can_clk", true, 100000000),
109 CLOCK_CELL(CLK_CAN1_1, CLK_CAN1_1, "can1_axi_clk", true, 100000000),
110 CLOCK_CELL(CLK_CAN2_0, CLK_CAN2_0, "can2_can_clk", true, 100000000),
111 CLOCK_CELL(CLK_CAN2_1, CLK_CAN2_1, "can2_axi_clk", true, 100000000),
112 CLOCK_CELL(CLK_CAN3_0, CLK_CAN3_0, "can3_can_clk", true, 100000000),
113 CLOCK_CELL(CLK_CAN3_1, CLK_CAN3_1, "can3_axi_clk", true, 100000000),
114 CLOCK_CELL(CLK_PS_GPIO_0, CLK_PS_GPIO_0, "ps_gpio_clk", true, 100000000),
115 CLOCK_CELL(CLK_PMC_GPIO_0, CLK_PMC_GPIO_0, "pmc_gpio_clk", true, 100000000),
116 CLOCK_CELL(CLK_SPI0_0, CLK_SPI0_0, "spi0_ref_clk", true, 100000000),
117 CLOCK_CELL(CLK_SPI0_1, CLK_SPI0_1, "spi0_pclk", true, 100000000),
118 CLOCK_CELL(CLK_SPI1_0, CLK_SPI1_0, "spi1_ref_clk", true, 100000000),
119 CLOCK_CELL(CLK_SPI1_1, CLK_SPI1_1, "spi1_pclk", true, 100000000),
120 CLOCK_CELL(CLK_I3C0_0, CLK_I3C0_0, "i3c0_clk", true, 100000000),
121 CLOCK_CELL(CLK_I3C1_0, CLK_I3C1_0, "i3c1_clk", true, 100000000),
122 CLOCK_CELL(CLK_I3C2_0, CLK_I3C2_0, "i3c2_clk", true, 100000000),
123 CLOCK_CELL(CLK_I3C3_0, CLK_I3C3_0, "i3c3_clk", true, 100000000),
124 CLOCK_CELL(CLK_I3C4_0, CLK_I3C4_0, "i3c4_clk", true, 100000000),
125 CLOCK_CELL(CLK_I3C5_0, CLK_I3C5_0, "i3c5_clk", true, 100000000),
126 CLOCK_CELL(CLK_I3C6_0, CLK_I3C6_0, "i3c6_clk", true, 100000000),
127 CLOCK_CELL(CLK_I3C7_0, CLK_I3C7_0, "i3c7_clk", true, 100000000),
128};
129
130/*
131 * struct scmi_reset - Data for the exposed reset controller
132 * @reset_id: Reset identifier in RCC reset driver
133 * @name: Reset string ID exposed to agent
134 */
135struct scmi_reset {
136 unsigned long reset_id;
137 const char *name;
138};
139
140#define RESET_CELL(_scmi_id, _id, _name) \
141 [_scmi_id] = { \
142 .reset_id = (_id), \
143 .name = (_name), \
144 }
145
146static struct scmi_reset scmi0_reset[] = {
147 RESET_CELL(RESET_GEM0_0, RESET_GEM0_0, "gem0"),
148 RESET_CELL(RESET_GEM1_0, RESET_GEM1_0, "gem1"),
149 RESET_CELL(RESET_SERIAL0_0, RESET_SERIAL0_0, "serial0"),
150 RESET_CELL(RESET_SERIAL1_0, RESET_SERIAL1_0, "serial1"),
151 RESET_CELL(RESET_UFS0_0, RESET_UFS0_0, "ufs0"),
152 RESET_CELL(RESET_I2C0_0, RESET_I2C0_0, "i2c0"),
153 RESET_CELL(RESET_I2C1_0, RESET_I2C1_0, "i2c1"),
154 RESET_CELL(RESET_I2C2_0, RESET_I2C2_0, "i2c2"),
155 RESET_CELL(RESET_I2C3_0, RESET_I2C3_0, "i2c3"),
156 RESET_CELL(RESET_I2C4_0, RESET_I2C4_0, "i2c4"),
157 RESET_CELL(RESET_I2C5_0, RESET_I2C5_0, "i2c5"),
158 RESET_CELL(RESET_I2C6_0, RESET_I2C6_0, "i2c6"),
159 RESET_CELL(RESET_I2C7_0, RESET_I2C7_0, "i2c7"),
160 RESET_CELL(RESET_I2C8_0, RESET_I2C8_0, "i2c8"),
161 RESET_CELL(RESET_OSPI0_0, RESET_OSPI0_0, "ospi"),
162 RESET_CELL(RESET_USB0_0, RESET_USB0_0, "usb0_0"),
163 RESET_CELL(RESET_USB0_1, RESET_USB0_1, "usb0_1"),
164 RESET_CELL(RESET_USB0_2, RESET_USB0_2, "usb0_2"),
165 RESET_CELL(RESET_USB1_0, RESET_USB1_0, "usb1_0"),
166 RESET_CELL(RESET_USB1_1, RESET_USB1_1, "usb1_1"),
167 RESET_CELL(RESET_USB1_2, RESET_USB1_2, "usb1_2"),
168 RESET_CELL(RESET_MMC0_0, RESET_MMC0_0, "mmc0"),
169 RESET_CELL(RESET_MMC1_0, RESET_MMC1_0, "mmc1"),
170 RESET_CELL(RESET_SPI0_0, RESET_SPI0_0, "spi0"),
171 RESET_CELL(RESET_SPI1_0, RESET_SPI1_0, "spi1"),
172 RESET_CELL(RESET_QSPI0_0, RESET_QSPI0_0, "qspi"),
173 RESET_CELL(RESET_I3C0_0, RESET_I3C0_0, "i3c0"),
174 RESET_CELL(RESET_I3C1_0, RESET_I3C1_0, "i3c1"),
175 RESET_CELL(RESET_I3C2_0, RESET_I3C2_0, "i3c2"),
176 RESET_CELL(RESET_I3C3_0, RESET_I3C3_0, "i3c3"),
177 RESET_CELL(RESET_I3C4_0, RESET_I3C4_0, "i3c4"),
178 RESET_CELL(RESET_I3C5_0, RESET_I3C5_0, "i3c5"),
179 RESET_CELL(RESET_I3C6_0, RESET_I3C6_0, "i3c6"),
180 RESET_CELL(RESET_I3C7_0, RESET_I3C7_0, "i3c7"),
181 RESET_CELL(RESET_I3C8_0, RESET_I3C8_0, "i3c8"),
182};
183
Michal Simek095a20a2024-02-02 11:26:14 +0100184/**
185 * struct scmi_pd - Data for the exposed power domain controller
186 * @pd_id: pd identifier in RCC reset driver
187 * @name: pd string ID exposed to agent
188 * @state: keep state setting
189 */
190struct scmi_pd {
191 unsigned long pd_id;
192 const char *name;
193 unsigned int state;
194};
195
196#define PD_CELL(_scmi_id, _id, _name, _state) \
197 [_scmi_id] = { \
198 .pd_id = _id, \
199 .name = _name, \
200 .state = _state, \
201 }
202
203static struct scmi_pd scmi0_pd[] = {
204 PD_CELL(PD_USB0, PD_USB0, "usb0", 0),
205 PD_CELL(PD_USB1, PD_USB1, "usb1", 0),
206};
207
Amit Nagalc97857d2024-06-05 12:32:38 +0530208struct scmi_resources {
209 struct scmi_clk *clock;
210 size_t clock_count;
211 struct scmi_reset *reset;
212 size_t reset_count;
Michal Simek095a20a2024-02-02 11:26:14 +0100213 struct scmi_pd *pd;
214 size_t pd_count;
Amit Nagalc97857d2024-06-05 12:32:38 +0530215};
216
217static const struct scmi_resources resources[] = {
218 [0] = {
219 .clock = scmi0_clock,
220 .clock_count = ARRAY_SIZE(scmi0_clock),
221 .reset = scmi0_reset,
222 .reset_count = ARRAY_SIZE(scmi0_reset),
Michal Simek095a20a2024-02-02 11:26:14 +0100223 .pd = scmi0_pd,
224 .pd_count = ARRAY_SIZE(scmi0_pd),
Amit Nagalc97857d2024-06-05 12:32:38 +0530225 },
226};
227
228static const struct scmi_resources *find_resource(unsigned int agent_id)
229{
230 assert(agent_id < ARRAY_SIZE(resources));
231
232 return &resources[agent_id];
233}
234
235static struct scmi_clk *clk_find(unsigned int agent_id, unsigned int scmi_id)
236{
237 const struct scmi_resources *resource = find_resource(agent_id);
238 size_t n = 0U;
239 struct scmi_clk *ret = NULL;
240
241 if (resource != NULL) {
242 for (n = 0U; n < resource->clock_count; n++) {
243 if (n == scmi_id) {
244 ret = &resource->clock[n];
245 break;
246 }
247 }
248 }
249
250 return ret;
251}
252
253size_t plat_scmi_clock_count(unsigned int agent_id)
254{
255 const struct scmi_resources *resource = find_resource(agent_id);
256 size_t ret;
257
258 if (resource == NULL) {
259 ret = 0U;
260 } else {
261 VERBOSE("SCMI: CLK: %d clocks\n", (unsigned int)resource->clock_count);
262
263 ret = resource->clock_count;
264 }
265 return ret;
266}
267
268const char *plat_scmi_clock_get_name(unsigned int agent_id, unsigned int scmi_id)
269{
270 struct scmi_clk *clock = clk_find(agent_id, scmi_id);
271 const char *ret;
272
273 if (clock == NULL) {
274 ret = NULL;
275 } else {
276 VERBOSE("SCMI: CLK: id: %d, get_name: %s\n", scmi_id, clock->name);
277
278 ret = clock->name;
279 }
280 return ret;
281};
282
283/* Called by Linux */
284int32_t plat_scmi_clock_rates_array(unsigned int agent_id, unsigned int scmi_id,
285 unsigned long *array, size_t *nb_elts,
286 uint32_t start_idx)
287{
288 struct scmi_clk *clock = clk_find(agent_id, scmi_id);
289
290 if (clock == NULL) {
291 return SCMI_NOT_FOUND;
292 }
293
294 if (start_idx > 0) {
295 return SCMI_OUT_OF_RANGE;
296 }
297
298 if (array == NULL) {
299 *nb_elts = 1U;
300 } else if (*nb_elts == 1U) {
301 *array = clock->rate;
302 VERBOSE("SCMI: CLK: id: %d, clk_name: %s, get_rate %lu\n",
303 scmi_id, clock->name, *array);
304 } else {
305 return SCMI_GENERIC_ERROR;
306 }
307
308 return SCMI_SUCCESS;
309}
310
311unsigned long plat_scmi_clock_get_rate(unsigned int agent_id, unsigned int scmi_id)
312{
313 struct scmi_clk *clock = clk_find(agent_id, scmi_id);
314 unsigned long ret;
315
316 if ((clock == NULL)) {
317 ret = SCMI_NOT_FOUND;
318 } else {
319 VERBOSE("SCMI: CLK: id: %d, get_rate: %lu\n", scmi_id, clock->rate);
320 ret = clock->rate;
321 }
322 return ret;
323}
324
325int32_t plat_scmi_clock_set_rate(unsigned int agent_id, unsigned int scmi_id,
326 unsigned long rate)
327{
328 struct scmi_clk *clock = clk_find(agent_id, scmi_id);
329 unsigned long ret = UL(SCMI_SUCCESS);
330
331 if ((clock == NULL)) {
332 ret = SCMI_NOT_FOUND;
333 } else {
334 VERBOSE("SCMI: CLK: id: %d, set_rate: %lu\n", scmi_id, rate);
335 clock->rate = rate;
336 }
337 return ret;
338}
339
340int32_t plat_scmi_clock_get_state(unsigned int agent_id, unsigned int scmi_id)
341{
342 struct scmi_clk *clock = clk_find(agent_id, scmi_id);
343 int32_t ret;
344
345 if ((clock == NULL)) {
346 ret = SCMI_NOT_FOUND;
347 } else {
348 VERBOSE("SCMI: CLK: id: %d, get_state: %d\n", scmi_id, clock->enabled);
349
350 if (clock->enabled) {
351 ret = HIGH;
352 } else {
353 ret = LOW;
354 }
355 }
356 return ret;
357}
358
359int32_t plat_scmi_clock_set_state(unsigned int agent_id, unsigned int scmi_id,
360 bool enable_not_disable)
361{
362 struct scmi_clk *clock = clk_find(agent_id, scmi_id);
363 int32_t ret;
364
365 if (clock == NULL) {
366 ret = SCMI_NOT_FOUND;
367 } else {
368 if (enable_not_disable) {
369 if (!clock->enabled) {
370 VERBOSE("SCMI: clock: %u enable\n", scmi_id);
371 clock->enabled = true;
372 }
373 } else {
374 if (clock->enabled) {
375 VERBOSE("SCMI: clock: %u disable\n", scmi_id);
376 clock->enabled = false;
377 }
378 }
379
380 VERBOSE("SCMI: CLK: id: %d, set_state: %d\n", scmi_id, clock->enabled);
381
382 ret = SCMI_SUCCESS;
383 }
384
385 return ret;
386}
387
388
389/*
390 * Platform SCMI reset domains
391 */
392static struct scmi_reset *find_reset(unsigned int agent_id,
393 unsigned int scmi_id)
394{
395 const struct scmi_resources *resource = find_resource(agent_id);
396 size_t n;
397
398 if (resource != NULL) {
399 for (n = 0U; n < resource->reset_count; n++) {
400 if (n == scmi_id) {
401 return &resource->reset[n];
402 }
403 }
404 }
405
406 return NULL;
407}
408
409const char *plat_scmi_rstd_get_name(unsigned int agent_id, unsigned int scmi_id)
410{
411 const struct scmi_reset *reset = find_reset(agent_id, scmi_id);
412
413 if (reset == NULL) {
414 return NULL;
415 }
416
417 return reset->name;
418}
419
420size_t plat_scmi_rstd_count(unsigned int agent_id)
421{
422 const struct scmi_resources *resource = find_resource(agent_id);
423
424 if (resource == NULL) {
425 return 0U;
426 }
427
428 return resource->reset_count;
429}
430
431int32_t plat_scmi_rstd_autonomous(unsigned int agent_id, unsigned int scmi_id,
432 uint32_t state)
433{
434 const struct scmi_reset *reset = find_reset(agent_id, scmi_id);
435
436 if (reset == NULL) {
437 return SCMI_NOT_FOUND;
438 }
439
440 /* Supports only reset with context loss */
441 if (state != 0U) {
442 return SCMI_NOT_SUPPORTED;
443 }
444
445 NOTICE("SCMI reset on ID %lu/%s\n",
446 reset->reset_id, plat_scmi_rstd_get_name(agent_id, scmi_id));
447
448 return SCMI_SUCCESS;
449}
450
451int32_t plat_scmi_rstd_set_state(unsigned int agent_id, unsigned int scmi_id,
452 bool assert_not_deassert)
453{
454 const struct scmi_reset *reset = find_reset(agent_id, scmi_id);
455
456 if (reset == NULL) {
457 return SCMI_NOT_FOUND;
458 }
459
460 if (assert_not_deassert) {
461 NOTICE("SCMI reset %lu/%s set\n",
462 reset->reset_id, plat_scmi_rstd_get_name(agent_id, scmi_id));
463 } else {
464 NOTICE("SCMI reset %lu/%s release\n",
465 reset->reset_id, plat_scmi_rstd_get_name(agent_id, scmi_id));
466 }
467
468 return SCMI_SUCCESS;
469}
470
Michal Simek095a20a2024-02-02 11:26:14 +0100471/*
472 * Platform SCMI reset domains
473 */
474static struct scmi_pd *find_pd(unsigned int agent_id, unsigned int pd_id)
475{
476 const struct scmi_resources *resource = find_resource(agent_id);
477 size_t n;
478
479 if (resource != NULL) {
480 for (n = 0U; n < resource->pd_count; n++) {
481 if (n == pd_id) {
482 return &resource->pd[n];
483 }
484 }
485 }
486
487 return NULL;
488}
489
490size_t plat_scmi_pd_count(unsigned int agent_id)
491{
492 const struct scmi_resources *resource = find_resource(agent_id);
493 size_t ret;
494
495 if (resource == NULL) {
496 ret = 0U;
497 } else {
498 ret = resource->pd_count;
499
500 NOTICE("SCMI: PD: %d\n", (unsigned int)ret);
501 }
502 return ret;
503}
504
505const char *plat_scmi_pd_get_name(unsigned int agent_id, unsigned int pd_id)
506{
507 const struct scmi_pd *pd = find_pd(agent_id, pd_id);
508
509 if (pd == NULL) {
510 return NULL;
511 }
512
513 return pd->name;
514}
515
516unsigned int plat_scmi_pd_statistics(unsigned int agent_id, unsigned long *pd_id)
517{
518 return 0U;
519}
520
521unsigned int plat_scmi_pd_get_attributes(unsigned int agent_id, unsigned int pd_id)
522{
523 return 0U;
524}
525
526unsigned int plat_scmi_pd_get_state(unsigned int agent_id, unsigned int pd_id)
527{
528 const struct scmi_pd *pd = find_pd(agent_id, pd_id);
529
530 if (pd == NULL) {
531 return SCMI_NOT_SUPPORTED;
532 }
533
534 NOTICE("SCMI: PD: get id: %d, state: %x\n", pd_id, pd->state);
535
536 return pd->state;
537}
538
539int32_t plat_scmi_pd_set_state(unsigned int agent_id, unsigned int flags, unsigned int pd_id,
540 unsigned int state)
541{
542 struct scmi_pd *pd = find_pd(agent_id, pd_id);
543
544 if (pd == NULL) {
545 return SCMI_NOT_SUPPORTED;
546 }
547
548 NOTICE("SCMI: PD: set id: %d, orig state: %x, new state: %x, flags: %x\n",
549 pd_id, pd->state, state, flags);
550
551 pd->state = state;
552
553 return 0U;
554}
555
556
Amit Nagalc97857d2024-06-05 12:32:38 +0530557/* Currently only one channel is supported. Expectation is that channel 0 is used by NS SW */
558static struct scmi_msg_channel scmi_channel[] = {
559 [0] = {
560 .shm_addr = SMT_BUFFER_BASE,
561 .shm_size = SMT_BUF_SLOT_SIZE,
562 },
563};
564
565struct scmi_msg_channel *plat_scmi_get_channel(unsigned int agent_id)
566{
567 assert(agent_id < ARRAY_SIZE(scmi_channel));
568
569 VERBOSE("%d: SCMI asking for channel\n", agent_id);
570
571 /* Just in case that code is reused */
572 return &scmi_channel[agent_id];
573}
574
575/* Base protocol implementations */
576const char *plat_scmi_vendor_name(void)
577{
578 return SCMI_VENDOR;
579}
580
581const char *plat_scmi_sub_vendor_name(void)
582{
583 return SCMI_PRODUCT;
584}
585
586/* Currently supporting Clocks and Reset Domains */
587static const uint8_t plat_protocol_list[] = {
588 SCMI_PROTOCOL_ID_BASE,
589 SCMI_PROTOCOL_ID_CLOCK,
590 SCMI_PROTOCOL_ID_RESET_DOMAIN,
Michal Simek095a20a2024-02-02 11:26:14 +0100591 SCMI_PROTOCOL_ID_POWER_DOMAIN,
592 /* SCMI_PROTOCOL_ID_SENSOR, */
Amit Nagalc97857d2024-06-05 12:32:38 +0530593 0U /* Null termination */
594};
595
596size_t plat_scmi_protocol_count(void)
597{
598 const size_t count = ARRAY_SIZE(plat_protocol_list) - 1U;
599
600 VERBOSE("SCMI: Protocol count: %d\n", (int32_t)count);
601
602 return count;
603}
604
605const uint8_t *plat_scmi_protocol_list(unsigned int agent_id __unused)
606{
607 return plat_protocol_list;
608}
609
610void init_scmi_server(void)
611{
612 size_t i;
613 int32_t ret;
614
615 for (i = 0U; i < ARRAY_SIZE(scmi_channel); i++)
616 scmi_smt_init_agent_channel(&scmi_channel[i]);
617
618 INFO("SCMI: Server initialized\n");
619
620 if (platform_id == QEMU) {
621 /* default setting is for QEMU */
622 } else if (platform_id == SPP) {
623 for (i = 0U; i < ARRAY_SIZE(scmi0_clock); i++) {
624
625 /* Keep i2c on 100MHz to calculate rates properly */
626 if (i >= CLK_I2C0_0 && i <= CLK_I2C7_0)
627 continue;
628 /*
629 * SPP supports multiple versions.
630 * The cpu_clock value is set to corresponding SPP
631 * version in early platform setup, resuse the same
632 * value here.
633 */
634 ret = plat_scmi_clock_set_rate(0, i, cpu_clock);
635 if (ret < 0) {
636 NOTICE("Failed to set clock rate for SPP scmi_id=%ld\n", i);
637 }
638 }
639 } else {
640 /* Making MISRA C 2012 15.7 compliant */
641 }
642}