blob: 33f11195982bdb2dce5561a1f238d96be082ba0f [file] [log] [blame]
Achin Gupta383b7c52019-10-11 15:41:16 +01001/*
2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8#include <errno.h>
9#include <string.h>
10
11#include <arch_helpers.h>
12#include <bl31/bl31.h>
13#include <common/debug.h>
14#include <common/runtime_svc.h>
15#include <lib/el3_runtime/context_mgmt.h>
16#include <lib/smccc.h>
17#include <lib/spinlock.h>
18#include <lib/utils.h>
19#include <lib/xlat_tables/xlat_tables_v2.h>
20#include <platform_def.h>
21#include <plat/common/common_def.h>
22#include <plat/common/platform.h>
23#include <services/spci_beta0.h>
24#include <smccc_helpers.h>
25#include <services/spmd_svc.h>
26#include "spmd_private.h"
27
28/*******************************************************************************
29 * SPM Core context information.
30 ******************************************************************************/
31spmd_spm_core_context_t spm_core_context[PLATFORM_CORE_COUNT];
32
33/*******************************************************************************
34 * SPM Core attribute information read from its manifest.
35 ******************************************************************************/
36spmc_manifest_sect_attribute_t spmc_attrs;
37
38/*******************************************************************************
39 * This function takes an SP context pointer and performs a synchronous entry
40 * into it.
41 ******************************************************************************/
42uint64_t spmd_spm_core_sync_entry(spmd_spm_core_context_t *spmc_ctx)
43{
44 uint64_t rc;
45
46 assert(spmc_ctx != NULL);
47
48 cm_set_context(&(spmc_ctx->cpu_ctx), SECURE);
49
50 /* Restore the context assigned above */
51 cm_el1_sysregs_context_restore(SECURE);
52 cm_set_next_eret_context(SECURE);
53
54 /* Invalidate TLBs at EL1. */
55 tlbivmalle1();
56 dsbish();
57
58 /* Enter Secure Partition */
59 rc = spmd_spm_core_enter(&spmc_ctx->c_rt_ctx);
60
61 /* Save secure state */
62 cm_el1_sysregs_context_save(SECURE);
63
64 return rc;
65}
66
67/*******************************************************************************
68 * This function returns to the place where spm_sp_synchronous_entry() was
69 * called originally.
70 ******************************************************************************/
71__dead2 void spmd_spm_core_sync_exit(uint64_t rc)
72{
73 spmd_spm_core_context_t *ctx = &spm_core_context[plat_my_core_pos()];
74
75 /* Get context of the SP in use by this CPU. */
76 assert(cm_get_context(SECURE) == &(ctx->cpu_ctx));
77
78 /*
79 * The SPMD must have initiated the original request through a
80 * synchronous entry into SPMC. Jump back to the original C runtime
81 * context with the value of rc in x0;
82 */
83 spmd_spm_core_exit(ctx->c_rt_ctx, rc);
84
85 panic();
86}
87
88/*******************************************************************************
89 * Jump to the SPM core for the first time.
90 ******************************************************************************/
91static int32_t spmd_init(void)
92{
93 uint64_t rc = 0;
94 spmd_spm_core_context_t *ctx = &spm_core_context[plat_my_core_pos()];
95
96 INFO("SPM Core init start.\n");
97 ctx->state = SPMC_STATE_RESET;
98
99 rc = spmd_spm_core_sync_entry(ctx);
100 if (rc) {
101 ERROR("SPMC initialisation failed 0x%llx\n", rc);
102 panic();
103 }
104
105 ctx->state = SPMC_STATE_IDLE;
106 INFO("SPM Core init end.\n");
107
108 return 1;
109}
110
111/*******************************************************************************
112 * Initialize context of SPM core.
113 ******************************************************************************/
114int32_t spmd_setup(void)
115{
116 int rc;
117 void *rd_base;
118 size_t rd_size;
119 entry_point_info_t *spmc_ep_info;
120 uintptr_t rd_base_align;
121 uintptr_t rd_size_align;
122 uint32_t ep_attr;
123
124 spmc_ep_info = bl31_plat_get_next_image_ep_info(SECURE);
125 if (!spmc_ep_info) {
126 WARN("No SPM core image provided by BL2 boot loader, Booting "
127 "device without SP initialization. SMC`s destined for SPM "
128 "core will return SMC_UNK\n");
129 return 1;
130 }
131
132 /* Under no circumstances will this parameter be 0 */
133 assert (spmc_ep_info->pc != 0U);
134
135 /*
136 * Check if BL32 ep_info has a reference to 'tos_fw_config'. This will
137 * be used as a manifest for the SPM core at the next lower EL/mode.
138 */
139 if (spmc_ep_info->args.arg0 == 0U || spmc_ep_info->args.arg2 == 0U) {
140 ERROR("Invalid or absent SPM core manifest \n");
141 panic();
142 }
143
144 /* Obtain whereabouts of SPM core manifest */
145 rd_base = (void *) spmc_ep_info->args.arg0;
146 rd_size = spmc_ep_info->args.arg2;
147
148 rd_base_align = page_align((uintptr_t) rd_base, DOWN);
149 rd_size_align = page_align((uintptr_t) rd_size, UP);
150
151 /* Map the manifest in the SPMD translation regime first */
152 VERBOSE("SPM core manifest base : 0x%lx \n", rd_base_align);
153 VERBOSE("SPM core manifest size : 0x%lx \n", rd_size_align);
154 rc = mmap_add_dynamic_region((unsigned long long) rd_base_align,
155 (uintptr_t) rd_base_align,
156 rd_size_align,
157 MT_RO_DATA);
158 if (rc < 0) {
159 ERROR("Error while mapping SPM core manifest (%d).\n", rc);
160 panic();
161 }
162
163 /* Load the SPM core manifest */
164 rc = plat_spm_core_manifest_load(&spmc_attrs, rd_base, rd_size);
165 if (rc < 0) {
166 WARN("No or invalid SPM core manifest image provided by BL2 "
167 "boot loader. ");
168 goto error;
169 }
170
171 /*
172 * Ensure that the SPM core version is compatible with the SPM
173 * dispatcher version
174 */
175 if ((spmc_attrs.major_version != SPCI_VERSION_MAJOR) ||
176 (spmc_attrs.minor_version > SPCI_VERSION_MINOR)) {
177 WARN("Unsupported SPCI version (%x.%x) specified in SPM core "
178 "manifest image provided by BL2 boot loader.\n",
179 spmc_attrs.major_version, spmc_attrs.minor_version);
180 goto error;
181 }
182
183 INFO("SPCI version (%x.%x).\n", spmc_attrs.major_version,
184 spmc_attrs.minor_version);
185
186 /* Validate the SPM core runtime EL */
187 if ((spmc_attrs.runtime_el != MODE_EL1) &&
188 (spmc_attrs.runtime_el != MODE_EL2)) {
189 WARN("Unsupported SPM core run time EL%x specified in "
190 "manifest image provided by BL2 boot loader.\n",
191 spmc_attrs.runtime_el);
192 goto error;
193 }
194
195 INFO("SPM core run time EL%x.\n", spmc_attrs.runtime_el);
196
197 /* Validate the SPM core execution state */
198 if ((spmc_attrs.exec_state != MODE_RW_64) &&
199 (spmc_attrs.exec_state != MODE_RW_32)) {
200 WARN("Unsupported SPM core execution state %x specified in "
201 "manifest image provided by BL2 boot loader.\n",
202 spmc_attrs.exec_state);
203 goto error;
204 }
205
206 INFO("SPM core execution state %x.\n", spmc_attrs.exec_state);
207
208 /* Ensure manifest has not requested S-EL2 in AArch32 state */
209 if ((spmc_attrs.exec_state == MODE_RW_32) &&
210 (spmc_attrs.runtime_el == MODE_EL2)) {
211 WARN("Invalid combination of SPM core execution state (%x) "
212 "and run time EL (%x).\n", spmc_attrs.exec_state,
213 spmc_attrs.runtime_el);
214 goto error;
215 }
216
217 /* Enable S-EL2 for SPM core if required */
218 if (spmc_attrs.runtime_el == MODE_EL2) {
219 /* First check if S-EL2 is supported on this system */
220 uint64_t sel2 = read_id_aa64pfr0_el1();
221
222 sel2 >>= ID_AA64PFR0_SEL2_SHIFT;
223 sel2 &= ID_AA64PFR0_SEL2_MASK;
224
225 if (!sel2) {
226 WARN("SPM core run time EL: S-EL%x is not supported "
227 "but specified in manifest image provided by "
228 "BL2 boot loader.\n", spmc_attrs.runtime_el);
229 goto error;
230 }
231 }
232
233 /* Initialise an entrypoint to set up the CPU context */
234 ep_attr = SECURE | EP_ST_ENABLE;
235 if (read_sctlr_el3() & SCTLR_EE_BIT)
236 ep_attr |= EP_EE_BIG;
237 SET_PARAM_HEAD(spmc_ep_info, PARAM_EP, VERSION_1, ep_attr);
238 assert (spmc_ep_info->pc == BL32_BASE);
239
240 /*
241 * Populate SPSR for SPM core based upon validated parameters from the
242 * manifest
243 */
244 if (spmc_attrs.exec_state == MODE_RW_32) {
245 spmc_ep_info->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
246 SPSR_E_LITTLE,
247 DAIF_FIQ_BIT |
248 DAIF_IRQ_BIT |
249 DAIF_ABT_BIT);
250 } else {
251 spmc_ep_info->spsr = SPSR_64(spmc_attrs.runtime_el,
252 MODE_SP_ELX,
253 DISABLE_ALL_EXCEPTIONS);
254 }
255
256 /* Initialise SPM core context with this entry point information */
257 cm_setup_context(&(spm_core_context[plat_my_core_pos()].cpu_ctx),
258 spmc_ep_info);
259
260 INFO("SPM core setup done.\n");
261
262 /* Register init function for deferred init. */
263 bl31_register_bl32_init(&spmd_init);
264
265 return 0;
266
267error:
268 WARN("Booting device without SPM initialization. "
269 "SPCI SMCs destined for SPM core will return "
270 "ENOTSUPPORTED\n");
271
272 rc = mmap_remove_dynamic_region(rd_base_align, rd_size_align);
273 if (rc < 0) {
274 ERROR("Error while unmapping SPM core manifest (%d).\n",
275 rc);
276 panic();
277 }
278
279 return 1;
280}
281
282/*******************************************************************************
283 * This function handles all SMCs in the range reserved for SPCI. Each call is
284 * either forwarded to the other security state or handled by the SPM dispatcher
285 ******************************************************************************/
286uint64_t spmd_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2,
287 uint64_t x3, uint64_t x4, void *cookie, void *handle,
288 uint64_t flags)
289{
290 unsigned int in_sstate, out_sstate;
291 int32_t ret;
292 spmd_spm_core_context_t *ctx = &spm_core_context[plat_my_core_pos()];
293
294 /* Determine which security state this SMC originated from */
295 in_sstate = is_caller_non_secure(flags);
296 out_sstate = !in_sstate;
297
298 INFO("SPM: 0x%x, 0x%llx, 0x%llx, 0x%llx, 0x%llx, 0x%llx, 0x%llx, 0x%llx \n",
299 smc_fid, x1, x2, x3, x4, SMC_GET_GP(handle, CTX_GPREG_X5),
300 SMC_GET_GP(handle, CTX_GPREG_X6),
301 SMC_GET_GP(handle, CTX_GPREG_X7));
302
303
304 switch (smc_fid) {
305 case SPCI_ERROR:
306 /*
307 * Check if this is the first invocation of this interface on
308 * this CPU. If so, then indicate that the SPM core initialised
309 * unsuccessfully.
310 */
311 if ((in_sstate == SECURE) && (ctx->state == SPMC_STATE_RESET))
312 spmd_spm_core_sync_exit(x2);
313
314 /* Save incoming security state */
315 cm_el1_sysregs_context_save(in_sstate);
316
317 /* Restore outgoing security state */
318 cm_el1_sysregs_context_restore(out_sstate);
319 cm_set_next_eret_context(out_sstate);
320
321 SMC_RET8(cm_get_context(out_sstate), smc_fid, x1, x2, x3, x4,
322 SMC_GET_GP(handle, CTX_GPREG_X5),
323 SMC_GET_GP(handle, CTX_GPREG_X6),
324 SMC_GET_GP(handle, CTX_GPREG_X7));
325
326 case SPCI_VERSION:
327 /*
328 * TODO: This is an optimization that the version information
329 * provided by the SPM core manifest is returned by the SPM
330 * dispatcher. It might be a better idea to simply forward this
331 * call to the SPM core and wash our hands completely.
332 */
333 ret = MAKE_SPCI_VERSION(spmc_attrs.major_version,
334 spmc_attrs.minor_version);
335 SMC_RET8(handle, SPCI_SUCCESS, SPCI_TARGET_INFO_MBZ, ret,
336 SPCI_PARAM_MBZ, SPCI_PARAM_MBZ, SPCI_PARAM_MBZ,
337 SPCI_PARAM_MBZ, SPCI_PARAM_MBZ);
338
339 case SPCI_FEATURES:
340 /*
341 * This is an optional interface. Do the minimal checks and
342 * forward to SPM core which will handle it if implemented.
343 */
344
345 /*
346 * Check if w1 holds a valid SPCI fid. This is an
347 * optimization.
348 */
349 if (!is_spci_fid(x1))
350 SMC_RET8(handle, SPCI_ERROR,
351 SPCI_TARGET_INFO_MBZ, SPCI_NOT_SUPPORTED,
352 SPCI_PARAM_MBZ, SPCI_PARAM_MBZ, SPCI_PARAM_MBZ,
353 SPCI_PARAM_MBZ, SPCI_PARAM_MBZ);
354
355 /* Forward SMC from Normal world to the SPM core */
356 if (in_sstate == NON_SECURE) {
357 /* Save incoming security state */
358 cm_el1_sysregs_context_save(in_sstate);
359
360 /* Restore outgoing security state */
361 cm_el1_sysregs_context_restore(out_sstate);
362 cm_set_next_eret_context(out_sstate);
363
364 SMC_RET8(cm_get_context(out_sstate), smc_fid,
365 x1, x2, x3, x4,
366 SMC_GET_GP(handle, CTX_GPREG_X5),
367 SMC_GET_GP(handle, CTX_GPREG_X6),
368 SMC_GET_GP(handle, CTX_GPREG_X7));
369 } else {
370 /*
371 * Return success if call was from secure world i.e. all
372 * SPCI functions are supported. This is essentially a
373 * nop.
374 */
375 SMC_RET8(handle, SPCI_SUCCESS, x1, x2, x3, x4,
376 SMC_GET_GP(handle, CTX_GPREG_X5),
377 SMC_GET_GP(handle, CTX_GPREG_X6),
378 SMC_GET_GP(handle, CTX_GPREG_X7));
379 }
380
381 case SPCI_RX_RELEASE:
382 case SPCI_RXTX_MAP_SMC32:
383 case SPCI_RXTX_MAP_SMC64:
384 case SPCI_RXTX_UNMAP:
385 case SPCI_MSG_RUN:
386 /* This interface must be invoked only by the Normal world */
387 if (in_sstate == SECURE)
388 SMC_RET8(handle, SPCI_ERROR,
389 SPCI_TARGET_INFO_MBZ, SPCI_NOT_SUPPORTED,
390 SPCI_PARAM_MBZ, SPCI_PARAM_MBZ, SPCI_PARAM_MBZ,
391 SPCI_PARAM_MBZ, SPCI_PARAM_MBZ);
392
393 /* Fall through to forward the call to the other world */
394 case SPCI_PARTITION_INFO_GET:
395 case SPCI_MSG_SEND:
396 case SPCI_MSG_SEND_DIRECT_REQ_SMC32:
397 case SPCI_MSG_SEND_DIRECT_REQ_SMC64:
398 case SPCI_MSG_SEND_DIRECT_RESP_SMC32:
399 case SPCI_MSG_SEND_DIRECT_RESP_SMC64:
400 case SPCI_MEM_DONATE_SMC32:
401 case SPCI_MEM_DONATE_SMC64:
402 case SPCI_MEM_LEND_SMC32:
403 case SPCI_MEM_LEND_SMC64:
404 case SPCI_MEM_SHARE_SMC32:
405 case SPCI_MEM_SHARE_SMC64:
406 case SPCI_MEM_RETRIEVE_REQ_SMC32:
407 case SPCI_MEM_RETRIEVE_REQ_SMC64:
408 case SPCI_MEM_RETRIEVE_RESP:
409 case SPCI_MEM_RELINQUISH:
410 case SPCI_MEM_RECLAIM:
411 case SPCI_SUCCESS:
412 /*
413 * TODO: Assume that no requests originate from EL3 at the
414 * moment. This will change if a SP service is required in
415 * response to secure interrupts targeted to EL3. Until then
416 * simply forward the call to the Normal world.
417 */
418
419 /* Save incoming security state */
420 cm_el1_sysregs_context_save(in_sstate);
421
422 /* Restore outgoing security state */
423 cm_el1_sysregs_context_restore(out_sstate);
424 cm_set_next_eret_context(out_sstate);
425
426 SMC_RET8(cm_get_context(out_sstate), smc_fid, x1, x2, x3, x4,
427 SMC_GET_GP(handle, CTX_GPREG_X5),
428 SMC_GET_GP(handle, CTX_GPREG_X6),
429 SMC_GET_GP(handle, CTX_GPREG_X7));
430
431 case SPCI_MSG_WAIT:
432 /*
433 * Check if this is the first invocation of this interface on
434 * this CPU from the Secure world. If so, then indicate that the
435 * SPM core initialised successfully.
436 */
437 if ((in_sstate == SECURE) && (ctx->state == SPMC_STATE_RESET))
438 spmd_spm_core_sync_exit(0);
439 case SPCI_MSG_YIELD:
440 /* This interface must be invoked only by the Secure world */
441 if (in_sstate == NON_SECURE)
442 SMC_RET8(handle, SPCI_ERROR,
443 SPCI_TARGET_INFO_MBZ, SPCI_NOT_SUPPORTED,
444 SPCI_PARAM_MBZ, SPCI_PARAM_MBZ, SPCI_PARAM_MBZ,
445 SPCI_PARAM_MBZ, SPCI_PARAM_MBZ);
446
447 /* Save incoming security state */
448 cm_el1_sysregs_context_save(in_sstate);
449
450 /* Restore outgoing security state */
451 cm_el1_sysregs_context_restore(out_sstate);
452 cm_set_next_eret_context(out_sstate);
453
454 SMC_RET8(cm_get_context(out_sstate), smc_fid, x1, x2, x3, x4,
455 SMC_GET_GP(handle, CTX_GPREG_X5),
456 SMC_GET_GP(handle, CTX_GPREG_X6),
457 SMC_GET_GP(handle, CTX_GPREG_X7));
458
459 default:
460 WARN("SPM: Unsupported call 0x%08x\n", smc_fid);
461 SMC_RET8(handle, SPCI_ERROR,
462 SPCI_TARGET_INFO_MBZ, SPCI_NOT_SUPPORTED,
463 SPCI_PARAM_MBZ, SPCI_PARAM_MBZ, SPCI_PARAM_MBZ,
464 SPCI_PARAM_MBZ, SPCI_PARAM_MBZ);
465 }
466}