feat(gicv5): add a barebones GICv5 driver
This is the absolute minimum that's needed to compile an NS-only build
end exit out of EL3. The GIC is not used and/or configured in any way
but all the necessary hooks are populated.
Notably, SCR_EL3.FIQ becomes RES1 as GICv5 behaves in a similar manner
to a GICv3 with FIQ set.
Change-Id: Idae52b9df97f4ca2996b2dcd1e5efc45478a43f2
Co-developed-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
diff --git a/drivers/arm/gicv5/gicv5_cpuif.c b/drivers/arm/gicv5/gicv5_cpuif.c
index e6727f8..5dcbae9 100644
--- a/drivers/arm/gicv5/gicv5_cpuif.c
+++ b/drivers/arm/gicv5/gicv5_cpuif.c
@@ -3,3 +3,23 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+
+#include <drivers/arm/gic.h>
+#include <drivers/arm/gicv5.h>
+
+void gic_cpuif_enable(unsigned int cpu_idx)
+{
+}
+
+void gic_cpuif_disable(unsigned int cpu_idx)
+{
+}
+
+void gic_pcpu_init(unsigned int cpu_idx)
+{
+}
+
+void gic_pcpu_off(unsigned int cpu_idx)
+{
+}
+