feat(gicv5): add a barebones GICv5 driver
This is the absolute minimum that's needed to compile an NS-only build
end exit out of EL3. The GIC is not used and/or configured in any way
but all the necessary hooks are populated.
Notably, SCR_EL3.FIQ becomes RES1 as GICv5 behaves in a similar manner
to a GICv3 with FIQ set.
Change-Id: Idae52b9df97f4ca2996b2dcd1e5efc45478a43f2
Co-developed-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
diff --git a/drivers/arm/gicv5/gicv5_cpuif.c b/drivers/arm/gicv5/gicv5_cpuif.c
index e6727f8..5dcbae9 100644
--- a/drivers/arm/gicv5/gicv5_cpuif.c
+++ b/drivers/arm/gicv5/gicv5_cpuif.c
@@ -3,3 +3,23 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+
+#include <drivers/arm/gic.h>
+#include <drivers/arm/gicv5.h>
+
+void gic_cpuif_enable(unsigned int cpu_idx)
+{
+}
+
+void gic_cpuif_disable(unsigned int cpu_idx)
+{
+}
+
+void gic_pcpu_init(unsigned int cpu_idx)
+{
+}
+
+void gic_pcpu_off(unsigned int cpu_idx)
+{
+}
+
diff --git a/drivers/arm/gicv5/gicv5_iri.c b/drivers/arm/gicv5/gicv5_iri.c
index e6727f8..049f3f0 100644
--- a/drivers/arm/gicv5/gicv5_iri.c
+++ b/drivers/arm/gicv5/gicv5_iri.c
@@ -3,3 +3,24 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+
+#include <cdefs.h>
+#include <drivers/arm/gic.h>
+#include <drivers/arm/gicv5.h>
+
+#if USE_GIC_DRIVER != 5
+#error "This file should only be used with USE_GIC_DRIVER=5"
+#endif
+
+void __init gic_init(unsigned int cpu_idx)
+{
+ gicv5_driver_init();
+}
+
+void gic_save(void)
+{
+}
+
+void gic_resume(void)
+{
+}
diff --git a/drivers/arm/gicv5/gicv5_main.c b/drivers/arm/gicv5/gicv5_main.c
index e6727f8..09da488 100644
--- a/drivers/arm/gicv5/gicv5_main.c
+++ b/drivers/arm/gicv5/gicv5_main.c
@@ -3,3 +3,41 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+
+#include <cdefs.h>
+
+#include <arch_features.h>
+#include <bl31/interrupt_mgmt.h>
+#include <common/debug.h>
+#include <drivers/arm/gicv5.h>
+
+void __init gicv5_driver_init(void)
+{
+}
+
+/*
+ * There exists a theoretical configuration where FEAT_RME is enabled
+ * without using TrustZone (i.e., no Secure world present). Currently,
+ * there is no reliable mechanism to detect this scenario at runtime.
+ *
+ * TODO: Add support for this configuration in the future if required.
+ */
+bool gicv5_has_interrupt_type(unsigned int type)
+{
+ switch (type) {
+ case INTR_TYPE_EL3:
+ case INTR_TYPE_S_EL1:
+ case INTR_TYPE_NS:
+ return true;
+ case INTR_TYPE_RL:
+ return is_feat_rme_supported();
+ default:
+ return false;
+ }
+}
+
+uint8_t gicv5_get_pending_interrupt_type(void)
+{
+ /* there is no pending interrupt expected */
+ return INTR_TYPE_INVAL;
+}