| Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include "arch.h" |
| 8 | #include "asm_macros.S" |
| 9 | #include "platform.h" |
| 10 | |
| 11 | #define EOT_ASCII_CODE 4 |
| 12 | |
| 13 | .data |
| 14 | welcome_str: |
| 15 | .asciz "Booting the EL3 test payload\r\n" |
| 16 | all_cpus_booted_str: |
| 17 | .asciz "All CPUs booted!\r\n" |
| 18 | |
| 19 | .text |
| 20 | .global entrypoint |
| 21 | |
| 22 | func entrypoint |
| 23 | bl mark_cpu_presence |
| 24 | |
| 25 | /* Distinguish primary from secondary CPUs */ |
| 26 | mrs x0, mpidr_el1 |
| 27 | ldr x1, =MPIDR_AFFINITY_MASK |
| 28 | and x0, x0, x1 |
| 29 | |
| 30 | ldr x1, =PRIMARY_CPU_MPID |
| 31 | cmp x0, x1 |
| 32 | b.ne spin_forever |
| 33 | |
| 34 | /* |
| 35 | * Only the primary CPU executes the code below |
| 36 | */ |
| 37 | |
| 38 | adr x0, welcome_str |
| 39 | bl print_string |
| 40 | |
| 41 | /* Wait to see each CPU */ |
| 42 | mov x3, xzr |
| 43 | 1: |
| 44 | mov x0, x3 |
| 45 | bl is_cpu_present |
| 46 | cbz x0, 1b |
| 47 | |
| 48 | /* Next CPU, if any */ |
| 49 | add x3, x3, #1 |
| 50 | mov x0, #CPUS_COUNT |
| 51 | cmp x3, x0 |
| 52 | b.lt 1b |
| 53 | |
| 54 | /* All CPUs have been detected, announce the good news! */ |
| 55 | adr x0, all_cpus_booted_str |
| 56 | bl print_string |
| 57 | |
| 58 | /* Send EOT (End of Transmission character) character over the UART */ |
| 59 | mov x0, #EOT_ASCII_CODE |
| 60 | bl print_char |
| 61 | |
| 62 | spin_forever: |
| 63 | wfe |
| 64 | b spin_forever |
| 65 | endfunc entrypoint |