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Sandrine Bailleux3cd87d72018-10-09 11:12:55 +02001/*
johpow01465cd602020-10-08 17:29:11 -05002 * Copyright (c) 2017-2020, Arm Limited. All rights reserved.
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
johpow01465cd602020-10-08 17:29:11 -05007#ifndef AMU_H
8#define AMU_H
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +02009
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +020010#include <stdint.h>
11
johpow01465cd602020-10-08 17:29:11 -050012#include <cassert.h>
13#include <platform_def.h>
14
15#define AMU_GROUP0_COUNTERS_MASK U(0xf)
16#define AMU_GROUP0_NR_COUNTERS U(4)
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +020017
18#ifdef PLAT_AMU_GROUP1_COUNTERS_MASK
19#define AMU_GROUP1_COUNTERS_MASK PLAT_AMU_GROUP1_COUNTERS_MASK
20#else
johpow01465cd602020-10-08 17:29:11 -050021#define AMU_GROUP1_COUNTERS_MASK U(0)
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +020022#endif
23
johpow01465cd602020-10-08 17:29:11 -050024/* Calculate number of group 1 counters */
25#if (AMU_GROUP1_COUNTERS_MASK & (1 << 15))
26#define AMU_GROUP1_NR_COUNTERS 16U
27#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 14))
28#define AMU_GROUP1_NR_COUNTERS 15U
29#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 13))
30#define AMU_GROUP1_NR_COUNTERS 14U
31#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 12))
32#define AMU_GROUP1_NR_COUNTERS 13U
33#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 11))
34#define AMU_GROUP1_NR_COUNTERS 12U
35#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 10))
36#define AMU_GROUP1_NR_COUNTERS 11U
37#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 9))
38#define AMU_GROUP1_NR_COUNTERS 10U
39#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 8))
40#define AMU_GROUP1_NR_COUNTERS 9U
41#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 7))
42#define AMU_GROUP1_NR_COUNTERS 8U
43#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 6))
44#define AMU_GROUP1_NR_COUNTERS 7U
45#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 5))
46#define AMU_GROUP1_NR_COUNTERS 6U
47#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 4))
48#define AMU_GROUP1_NR_COUNTERS 5U
49#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 3))
50#define AMU_GROUP1_NR_COUNTERS 4U
51#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 2))
52#define AMU_GROUP1_NR_COUNTERS 3U
53#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 1))
54#define AMU_GROUP1_NR_COUNTERS 2U
55#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 0))
56#define AMU_GROUP1_NR_COUNTERS 1U
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +020057#else
johpow01465cd602020-10-08 17:29:11 -050058#define AMU_GROUP1_NR_COUNTERS 0U
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +020059#endif
60
johpow01465cd602020-10-08 17:29:11 -050061CASSERT(AMU_GROUP1_COUNTERS_MASK <= 0xffff, invalid_amu_group1_counters_mask);
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +020062
63int amu_supported(void);
johpow01465cd602020-10-08 17:29:11 -050064int amu_supported_8_6(void);
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +020065
johpow01465cd602020-10-08 17:29:11 -050066uint64_t amu_group0_cnt_read(unsigned int idx);
67#if __aarch64__
68uint64_t amu_group0_voffset_read(unsigned int idx);
69void amu_group0_voffset_write(unsigned int idx, uint64_t val);
70#endif
71
72#if AMU_GROUP1_NR_COUNTERS
73uint64_t amu_group1_cnt_read(unsigned int idx);
74#if __aarch64__
75uint64_t amu_group1_voffset_read(unsigned int idx);
76void amu_group1_voffset_write(unsigned int idx, uint64_t val);
77#endif
78#endif
79
80#endif /* AMU_H */