| Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef __ARCH_H__ |
| 8 | #define __ARCH_H__ |
| 9 | |
| 10 | #include <utils_def.h> |
| 11 | |
| 12 | /******************************************************************************* |
| 13 | * MIDR bit definitions |
| 14 | ******************************************************************************/ |
| 15 | #define MIDR_IMPL_MASK U(0xff) |
| 16 | #define MIDR_IMPL_SHIFT U(0x18) |
| 17 | #define MIDR_VAR_SHIFT U(20) |
| 18 | #define MIDR_VAR_BITS U(4) |
| 19 | #define MIDR_VAR_MASK U(0xf) |
| 20 | #define MIDR_REV_SHIFT U(0) |
| 21 | #define MIDR_REV_BITS U(4) |
| 22 | #define MIDR_REV_MASK U(0xf) |
| 23 | #define MIDR_PN_MASK U(0xfff) |
| 24 | #define MIDR_PN_SHIFT U(0x4) |
| 25 | |
| 26 | /******************************************************************************* |
| 27 | * MPIDR macros |
| 28 | ******************************************************************************/ |
| 29 | #define MPIDR_MT_MASK (ULL(1) << 24) |
| 30 | #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK |
| 31 | #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) |
| 32 | #define MPIDR_AFFINITY_BITS U(8) |
| 33 | #define MPIDR_AFFLVL_MASK ULL(0xff) |
| 34 | #define MPIDR_AFF0_SHIFT U(0) |
| 35 | #define MPIDR_AFF1_SHIFT U(8) |
| 36 | #define MPIDR_AFF2_SHIFT U(16) |
| 37 | #define MPIDR_AFF3_SHIFT U(32) |
| 38 | #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT |
| 39 | #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) |
| 40 | #define MPIDR_AFFLVL_SHIFT U(3) |
| 41 | #define MPIDR_AFFLVL0 ULL(0x0) |
| 42 | #define MPIDR_AFFLVL1 ULL(0x1) |
| 43 | #define MPIDR_AFFLVL2 ULL(0x2) |
| 44 | #define MPIDR_AFFLVL3 ULL(0x3) |
| 45 | #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n |
| 46 | #define MPIDR_AFFLVL0_VAL(mpidr) \ |
| 47 | (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) |
| 48 | #define MPIDR_AFFLVL1_VAL(mpidr) \ |
| 49 | (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) |
| 50 | #define MPIDR_AFFLVL2_VAL(mpidr) \ |
| 51 | (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) |
| 52 | #define MPIDR_AFFLVL3_VAL(mpidr) \ |
| 53 | (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) |
| 54 | /* |
| 55 | * The MPIDR_MAX_AFFLVL count starts from 0. Take care to |
| 56 | * add one while using this macro to define array sizes. |
| 57 | * TODO: Support only the first 3 affinity levels for now. |
| 58 | */ |
| 59 | #define MPIDR_MAX_AFFLVL U(2) |
| 60 | |
| 61 | /* Constant to highlight the assumption that MPIDR allocation starts from 0 */ |
| 62 | #define FIRST_MPIDR ULL(0) |
| 63 | |
| 64 | #define MPID_MASK (MPIDR_MT_MASK |\ |
| 65 | (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)|\ |
| 66 | (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT)|\ |
| 67 | (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) |
| 68 | |
| 69 | #define MPIDR_AFF_ID(mpid, n) \ |
| 70 | (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) |
| 71 | |
| 72 | #define MPIDR_CLUSTER_ID(mpid) MPIDR_AFF_ID(mpid, 1) |
| 73 | #define MPIDR_CPU_ID(mpid) MPIDR_AFF_ID(mpid, 0) |
| 74 | |
| 75 | /* |
| 76 | * An invalid MPID. This value can be used by functions that return an MPID to |
| 77 | * indicate an error. |
| 78 | */ |
| 79 | #define INVALID_MPID 0xFFFFFFFF |
| 80 | |
| 81 | /******************************************************************************* |
| 82 | * Definitions for CPU system register interface to GICv3 |
| 83 | ******************************************************************************/ |
| 84 | #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 |
| 85 | #define ICC_SGI1R S3_0_C12_C11_5 |
| 86 | #define ICC_SRE_EL1 S3_0_C12_C12_5 |
| 87 | #define ICC_SRE_EL2 S3_4_C12_C9_5 |
| 88 | #define ICC_SRE_EL3 S3_6_C12_C12_5 |
| 89 | #define ICC_CTLR_EL1 S3_0_C12_C12_4 |
| 90 | #define ICC_CTLR_EL3 S3_6_C12_C12_4 |
| 91 | #define ICC_PMR_EL1 S3_0_C4_C6_0 |
| 92 | #define ICC_RPR_EL1 S3_0_C12_C11_3 |
| 93 | #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 |
| 94 | #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 |
| 95 | #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 |
| 96 | #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 |
| 97 | #define ICC_IAR0_EL1 S3_0_c12_c8_0 |
| 98 | #define ICC_IAR1_EL1 S3_0_c12_c12_0 |
| 99 | #define ICC_EOIR0_EL1 S3_0_c12_c8_1 |
| 100 | #define ICC_EOIR1_EL1 S3_0_c12_c12_1 |
| 101 | #define ICC_SGI0R_EL1 S3_0_c12_c11_7 |
| 102 | |
| 103 | /******************************************************************************* |
| 104 | * Generic timer memory mapped registers & offsets |
| 105 | ******************************************************************************/ |
| 106 | #define CNTCR_OFF U(0x000) |
| 107 | #define CNTFID_OFF U(0x020) |
| 108 | |
| 109 | #define CNTCR_EN (U(1) << 0) |
| 110 | #define CNTCR_HDBG (U(1) << 1) |
| 111 | #define CNTCR_FCREQ(x) ((x) << 8) |
| 112 | |
| 113 | /******************************************************************************* |
| 114 | * System register bit definitions |
| 115 | ******************************************************************************/ |
| 116 | /* CLIDR definitions */ |
| 117 | #define LOUIS_SHIFT U(21) |
| 118 | #define LOC_SHIFT U(24) |
| 119 | #define CLIDR_FIELD_WIDTH U(3) |
| 120 | |
| 121 | /* CSSELR definitions */ |
| 122 | #define LEVEL_SHIFT U(1) |
| 123 | |
| 124 | /* Data cache set/way op type defines */ |
| 125 | #define DCISW U(0x0) |
| 126 | #define DCCISW U(0x1) |
| 127 | #define DCCSW U(0x2) |
| 128 | |
| 129 | /* ID_AA64PFR0_EL1 definitions */ |
| 130 | #define ID_AA64PFR0_EL0_SHIFT U(0) |
| 131 | #define ID_AA64PFR0_EL1_SHIFT U(4) |
| 132 | #define ID_AA64PFR0_EL2_SHIFT U(8) |
| 133 | #define ID_AA64PFR0_EL3_SHIFT U(12) |
| 134 | #define ID_AA64PFR0_AMU_SHIFT U(44) |
| 135 | #define ID_AA64PFR0_AMU_LENGTH U(4) |
| 136 | #define ID_AA64PFR0_AMU_MASK ULL(0xf) |
| 137 | #define ID_AA64PFR0_ELX_MASK ULL(0xf) |
| 138 | #define ID_AA64PFR0_SVE_SHIFT U(32) |
| 139 | #define ID_AA64PFR0_SVE_MASK ULL(0xf) |
| 140 | #define ID_AA64PFR0_SVE_LENGTH U(4) |
| 141 | #define ID_AA64PFR0_CSV2_SHIFT U(56) |
| 142 | #define ID_AA64PFR0_CSV2_MASK ULL(0xf) |
| 143 | #define ID_AA64PFR0_CSV2_LENGTH U(4) |
| 144 | |
| 145 | /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ |
| 146 | #define ID_AA64DFR0_PMS_SHIFT U(32) |
| 147 | #define ID_AA64DFR0_PMS_LENGTH U(4) |
| 148 | #define ID_AA64DFR0_PMS_MASK ULL(0xf) |
| 149 | |
| 150 | #define EL_IMPL_NONE ULL(0) |
| 151 | #define EL_IMPL_A64ONLY ULL(1) |
| 152 | #define EL_IMPL_A64_A32 ULL(2) |
| 153 | |
| 154 | #define ID_AA64PFR0_GIC_SHIFT U(24) |
| 155 | #define ID_AA64PFR0_GIC_WIDTH U(4) |
| 156 | #define ID_AA64PFR0_GIC_MASK ((ULL(1) << ID_AA64PFR0_GIC_WIDTH) - ULL(1)) |
| 157 | |
| 158 | /* ID_AA64MMFR0_EL1 definitions */ |
| 159 | #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) |
| 160 | #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) |
| 161 | |
| Jeenu Viswambharan | a1c3cca | 2018-10-16 10:09:32 +0100 | [diff] [blame^] | 162 | /* ID_AA64ISAR1_EL1 definitions */ |
| 163 | #define ID_AA64ISAR1_GPI_SHIFT U(28) |
| 164 | #define ID_AA64ISAR1_GPI_WIDTH U(4) |
| 165 | #define ID_AA64ISAR1_GPA_SHIFT U(24) |
| 166 | #define ID_AA64ISAR1_GPA_WIDTH U(4) |
| 167 | #define ID_AA64ISAR1_API_SHIFT U(8) |
| 168 | #define ID_AA64ISAR1_API_WIDTH U(4) |
| 169 | #define ID_AA64ISAR1_APA_SHIFT U(4) |
| 170 | #define ID_AA64ISAR1_APA_WIDTH U(4) |
| 171 | |
| 172 | #define ID_AA64ISAR1_GPI_MASK \ |
| 173 | (((ULL(1) << ID_AA64ISAR1_GPI_WIDTH) - ULL(1)) << ID_AA64ISAR1_GPI_SHIFT) |
| 174 | #define ID_AA64ISAR1_GPA_MASK \ |
| 175 | (((ULL(1) << ID_AA64ISAR1_GPA_WIDTH) - ULL(1)) << ID_AA64ISAR1_GPA_SHIFT) |
| 176 | #define ID_AA64ISAR1_API_MASK \ |
| 177 | (((ULL(1) << ID_AA64ISAR1_API_WIDTH) - ULL(1)) << ID_AA64ISAR1_API_SHIFT) |
| 178 | #define ID_AA64ISAR1_APA_MASK \ |
| 179 | (((ULL(1) << ID_AA64ISAR1_APA_WIDTH) - ULL(1)) << ID_AA64ISAR1_APA_SHIFT) |
| 180 | |
| Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame] | 181 | #define PARANGE_0000 U(32) |
| 182 | #define PARANGE_0001 U(36) |
| 183 | #define PARANGE_0010 U(40) |
| 184 | #define PARANGE_0011 U(42) |
| 185 | #define PARANGE_0100 U(44) |
| 186 | #define PARANGE_0101 U(48) |
| 187 | #define PARANGE_0110 U(52) |
| 188 | |
| 189 | #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) |
| 190 | #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) |
| 191 | #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) |
| 192 | #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) |
| 193 | |
| 194 | #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) |
| 195 | #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) |
| 196 | #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) |
| 197 | #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) |
| 198 | |
| 199 | #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) |
| 200 | #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) |
| 201 | #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) |
| 202 | #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) |
| 203 | |
| 204 | /* SCTLR definitions */ |
| 205 | #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ |
| 206 | (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ |
| 207 | (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) |
| 208 | |
| 209 | #define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ |
| 210 | (U(1) << 22) | (U(1) << 20) | (U(1) << 11)) |
| 211 | |
| 212 | #define SCTLR_M_BIT (U(1) << 0) |
| 213 | #define SCTLR_A_BIT (U(1) << 1) |
| 214 | #define SCTLR_C_BIT (U(1) << 2) |
| 215 | #define SCTLR_SA_BIT (U(1) << 3) |
| 216 | #define SCTLR_SA0_BIT (U(1) << 4) |
| 217 | #define SCTLR_CP15BEN_BIT (U(1) << 5) |
| 218 | #define SCTLR_ITD_BIT (U(1) << 7) |
| 219 | #define SCTLR_SED_BIT (U(1) << 8) |
| 220 | #define SCTLR_UMA_BIT (U(1) << 9) |
| 221 | #define SCTLR_I_BIT (U(1) << 12) |
| 222 | #define SCTLR_V_BIT (U(1) << 13) |
| 223 | #define SCTLR_DZE_BIT (U(1) << 14) |
| 224 | #define SCTLR_UCT_BIT (U(1) << 15) |
| 225 | #define SCTLR_NTWI_BIT (U(1) << 16) |
| 226 | #define SCTLR_NTWE_BIT (U(1) << 18) |
| 227 | #define SCTLR_WXN_BIT (U(1) << 19) |
| 228 | #define SCTLR_UWXN_BIT (U(1) << 20) |
| 229 | #define SCTLR_E0E_BIT (U(1) << 24) |
| 230 | #define SCTLR_EE_BIT (U(1) << 25) |
| 231 | #define SCTLR_UCI_BIT (U(1) << 26) |
| 232 | #define SCTLR_TRE_BIT (U(1) << 28) |
| 233 | #define SCTLR_AFE_BIT (U(1) << 29) |
| 234 | #define SCTLR_TE_BIT (U(1) << 30) |
| 235 | #define SCTLR_RESET_VAL SCTLR_EL3_RES1 |
| 236 | |
| 237 | /* CPACR_El1 definitions */ |
| 238 | #define CPACR_EL1_FPEN(x) ((x) << 20) |
| 239 | #define CPACR_EL1_FP_TRAP_EL0 U(0x1) |
| 240 | #define CPACR_EL1_FP_TRAP_ALL U(0x2) |
| 241 | #define CPACR_EL1_FP_TRAP_NONE U(0x3) |
| 242 | |
| 243 | /* SCR definitions */ |
| 244 | #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) |
| 245 | #define SCR_FIEN_BIT (U(1) << 21) |
| 246 | #define SCR_TWE_BIT (U(1) << 13) |
| 247 | #define SCR_TWI_BIT (U(1) << 12) |
| 248 | #define SCR_ST_BIT (U(1) << 11) |
| 249 | #define SCR_RW_BIT (U(1) << 10) |
| 250 | #define SCR_SIF_BIT (U(1) << 9) |
| 251 | #define SCR_HCE_BIT (U(1) << 8) |
| 252 | #define SCR_SMD_BIT (U(1) << 7) |
| 253 | #define SCR_EA_BIT (U(1) << 3) |
| 254 | #define SCR_FIQ_BIT (U(1) << 2) |
| 255 | #define SCR_IRQ_BIT (U(1) << 1) |
| 256 | #define SCR_NS_BIT (U(1) << 0) |
| 257 | #define SCR_VALID_BIT_MASK U(0x2f8f) |
| 258 | #define SCR_RESET_VAL SCR_RES1_BITS |
| 259 | |
| 260 | /* HCR definitions */ |
| 261 | #define HCR_RW_BIT (1ull << 31) |
| 262 | #define HCR_TGE_BIT (1 << 27) |
| 263 | #define HCR_AMO_BIT (1 << 5) |
| 264 | #define HCR_IMO_BIT (1 << 4) |
| 265 | #define HCR_FMO_BIT (1 << 3) |
| 266 | |
| 267 | /* CNTHCTL_EL2 definitions */ |
| 268 | #define EL1PCEN_BIT (1 << 1) |
| 269 | #define EL1PCTEN_BIT (1 << 0) |
| 270 | |
| 271 | /* CNTKCTL_EL1 definitions */ |
| 272 | #define EL0PTEN_BIT (U(1) << 9) |
| 273 | #define EL0VTEN_BIT (U(1) << 8) |
| 274 | #define EL0PCTEN_BIT (U(1) << 0) |
| 275 | #define EL0VCTEN_BIT (U(1) << 1) |
| 276 | #define EVNTEN_BIT (U(1) << 2) |
| 277 | #define EVNTDIR_BIT (U(1) << 3) |
| 278 | #define EVNTI_SHIFT U(4) |
| 279 | #define EVNTI_MASK U(0xf) |
| 280 | |
| 281 | /* CPTR_EL2 definitions */ |
| 282 | #define TCPAC_BIT (1 << 31) |
| 283 | #define TTA_BIT (1 << 20) |
| 284 | #define TFP_BIT (1 << 10) |
| 285 | |
| 286 | /* CPSR/SPSR definitions */ |
| 287 | #define DAIF_FIQ_BIT (U(1) << 0) |
| 288 | #define DAIF_IRQ_BIT (U(1) << 1) |
| 289 | #define DAIF_ABT_BIT (U(1) << 2) |
| 290 | #define DAIF_DBG_BIT (U(1) << 3) |
| 291 | #define SPSR_DAIF_SHIFT U(6) |
| 292 | #define SPSR_DAIF_MASK U(0xf) |
| 293 | |
| 294 | #define SPSR_AIF_SHIFT U(6) |
| 295 | #define SPSR_AIF_MASK U(0x7) |
| 296 | |
| 297 | #define SPSR_E_SHIFT U(9) |
| 298 | #define SPSR_E_MASK U(0x1) |
| 299 | #define SPSR_E_LITTLE U(0x0) |
| 300 | #define SPSR_E_BIG U(0x1) |
| 301 | |
| 302 | #define SPSR_T_SHIFT U(5) |
| 303 | #define SPSR_T_MASK U(0x1) |
| 304 | #define SPSR_T_ARM U(0x0) |
| 305 | #define SPSR_T_THUMB U(0x1) |
| 306 | |
| 307 | #define SPSR_M_SHIFT U(4) |
| 308 | #define SPSR_M_MASK U(0x1) |
| 309 | #define SPSR_M_AARCH64 U(0x0) |
| 310 | #define SPSR_M_AARCH32 U(0x1) |
| 311 | |
| 312 | #define DISABLE_ALL_EXCEPTIONS \ |
| 313 | (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) |
| 314 | |
| 315 | #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) |
| 316 | |
| 317 | /* |
| 318 | * TCR defintions |
| 319 | */ |
| 320 | #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) |
| 321 | #define TCR_EL3_RES1 ((U(1) << 31) | (U(1) << 23)) |
| 322 | #define TCR_EL1_IPS_SHIFT U(32) |
| 323 | #define TCR_EL2_PS_SHIFT U(16) |
| 324 | #define TCR_EL3_PS_SHIFT U(16) |
| 325 | |
| 326 | #define TCR_TxSZ_MIN ULL(16) |
| 327 | #define TCR_TxSZ_MAX ULL(39) |
| 328 | |
| 329 | /* (internal) physical address size bits in EL3/EL1 */ |
| 330 | #define TCR_PS_BITS_4GB ULL(0x0) |
| 331 | #define TCR_PS_BITS_64GB ULL(0x1) |
| 332 | #define TCR_PS_BITS_1TB ULL(0x2) |
| 333 | #define TCR_PS_BITS_4TB ULL(0x3) |
| 334 | #define TCR_PS_BITS_16TB ULL(0x4) |
| 335 | #define TCR_PS_BITS_256TB ULL(0x5) |
| 336 | |
| 337 | #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) |
| 338 | #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) |
| 339 | #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) |
| 340 | #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) |
| 341 | #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) |
| 342 | #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) |
| 343 | |
| 344 | #define TCR_RGN_INNER_NC (ULL(0x0) << 8) |
| 345 | #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) |
| 346 | #define TCR_RGN_INNER_WT (ULL(0x2) << 8) |
| 347 | #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) |
| 348 | |
| 349 | #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) |
| 350 | #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) |
| 351 | #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) |
| 352 | #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) |
| 353 | |
| 354 | #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) |
| 355 | #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) |
| 356 | #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) |
| 357 | |
| 358 | #define TCR_TG0_SHIFT U(14) |
| 359 | #define TCR_TG0_MASK ULL(3) |
| 360 | #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) |
| 361 | #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) |
| 362 | #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) |
| 363 | |
| 364 | #define TCR_EPD0_BIT (ULL(1) << 7) |
| 365 | #define TCR_EPD1_BIT (ULL(1) << 23) |
| 366 | |
| 367 | #define MODE_SP_SHIFT U(0x0) |
| 368 | #define MODE_SP_MASK U(0x1) |
| 369 | #define MODE_SP_EL0 U(0x0) |
| 370 | #define MODE_SP_ELX U(0x1) |
| 371 | |
| 372 | #define MODE_RW_SHIFT U(0x4) |
| 373 | #define MODE_RW_MASK U(0x1) |
| 374 | #define MODE_RW_64 U(0x0) |
| 375 | #define MODE_RW_32 U(0x1) |
| 376 | |
| 377 | #define MODE_EL_SHIFT U(0x2) |
| 378 | #define MODE_EL_MASK U(0x3) |
| 379 | #define MODE_EL3 U(0x3) |
| 380 | #define MODE_EL2 U(0x2) |
| 381 | #define MODE_EL1 U(0x1) |
| 382 | #define MODE_EL0 U(0x0) |
| 383 | |
| 384 | #define MODE32_SHIFT U(0) |
| 385 | #define MODE32_MASK U(0xf) |
| 386 | #define MODE32_usr U(0x0) |
| 387 | #define MODE32_fiq U(0x1) |
| 388 | #define MODE32_irq U(0x2) |
| 389 | #define MODE32_svc U(0x3) |
| 390 | #define MODE32_mon U(0x6) |
| 391 | #define MODE32_abt U(0x7) |
| 392 | #define MODE32_hyp U(0xa) |
| 393 | #define MODE32_und U(0xb) |
| 394 | #define MODE32_sys U(0xf) |
| 395 | |
| 396 | #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) |
| 397 | #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) |
| 398 | #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) |
| 399 | #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) |
| 400 | |
| 401 | #define SPSR_64(el, sp, daif) \ |
| 402 | ((MODE_RW_64 << MODE_RW_SHIFT) | \ |
| 403 | (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ |
| 404 | (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ |
| 405 | (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) |
| 406 | |
| 407 | #define SPSR_MODE32(mode, isa, endian, aif) \ |
| 408 | ((MODE_RW_32 << MODE_RW_SHIFT) | \ |
| 409 | (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ |
| 410 | (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ |
| 411 | (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ |
| 412 | (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) |
| 413 | |
| 414 | /* |
| 415 | * TTBR Definitions |
| 416 | */ |
| 417 | #define TTBR_CNP_BIT ULL(0x1) |
| 418 | |
| 419 | /* Physical timer control register bit fields shifts and masks */ |
| 420 | #define CNTP_CTL_ENABLE_SHIFT 0 |
| 421 | #define CNTP_CTL_IMASK_SHIFT 1 |
| 422 | #define CNTP_CTL_ISTATUS_SHIFT 2 |
| 423 | |
| 424 | #define CNTP_CTL_ENABLE_MASK 1 |
| 425 | #define CNTP_CTL_IMASK_MASK 1 |
| 426 | #define CNTP_CTL_ISTATUS_MASK 1 |
| 427 | |
| 428 | #define get_cntp_ctl_enable(x) ((x >> CNTP_CTL_ENABLE_SHIFT) & \ |
| 429 | CNTP_CTL_ENABLE_MASK) |
| 430 | #define get_cntp_ctl_imask(x) ((x >> CNTP_CTL_IMASK_SHIFT) & \ |
| 431 | CNTP_CTL_IMASK_MASK) |
| 432 | #define get_cntp_ctl_istatus(x) ((x >> CNTP_CTL_ISTATUS_SHIFT) & \ |
| 433 | CNTP_CTL_ISTATUS_MASK) |
| 434 | |
| 435 | #define set_cntp_ctl_enable(x) (x |= 1 << CNTP_CTL_ENABLE_SHIFT) |
| 436 | #define set_cntp_ctl_imask(x) (x |= 1 << CNTP_CTL_IMASK_SHIFT) |
| 437 | |
| 438 | #define clr_cntp_ctl_enable(x) (x &= ~(1 << CNTP_CTL_ENABLE_SHIFT)) |
| 439 | #define clr_cntp_ctl_imask(x) (x &= ~(1 << CNTP_CTL_IMASK_SHIFT)) |
| 440 | |
| 441 | /* Exception Syndrome register bits and bobs */ |
| 442 | #define ESR_EC_SHIFT U(26) |
| 443 | #define ESR_EC_MASK U(0x3f) |
| 444 | #define ESR_EC_LENGTH U(6) |
| 445 | #define EC_UNKNOWN U(0x0) |
| 446 | #define EC_WFE_WFI U(0x1) |
| 447 | #define EC_AARCH32_CP15_MRC_MCR U(0x3) |
| 448 | #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) |
| 449 | #define EC_AARCH32_CP14_MRC_MCR U(0x5) |
| 450 | #define EC_AARCH32_CP14_LDC_STC U(0x6) |
| 451 | #define EC_FP_SIMD U(0x7) |
| 452 | #define EC_AARCH32_CP10_MRC U(0x8) |
| 453 | #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) |
| 454 | #define EC_ILLEGAL U(0xe) |
| 455 | #define EC_AARCH32_SVC U(0x11) |
| 456 | #define EC_AARCH32_HVC U(0x12) |
| 457 | #define EC_AARCH32_SMC U(0x13) |
| 458 | #define EC_AARCH64_SVC U(0x15) |
| 459 | #define EC_AARCH64_HVC U(0x16) |
| 460 | #define EC_AARCH64_SMC U(0x17) |
| 461 | #define EC_AARCH64_SYS U(0x18) |
| 462 | #define EC_IABORT_LOWER_EL U(0x20) |
| 463 | #define EC_IABORT_CUR_EL U(0x21) |
| 464 | #define EC_PC_ALIGN U(0x22) |
| 465 | #define EC_DABORT_LOWER_EL U(0x24) |
| 466 | #define EC_DABORT_CUR_EL U(0x25) |
| 467 | #define EC_SP_ALIGN U(0x26) |
| 468 | #define EC_AARCH32_FP U(0x28) |
| 469 | #define EC_AARCH64_FP U(0x2c) |
| 470 | #define EC_SERROR U(0x2f) |
| 471 | |
| 472 | #define EC_BITS(x) (x >> ESR_EC_SHIFT) & ESR_EC_MASK |
| 473 | |
| 474 | /******************************************************************************* |
| 475 | * Definitions of register offsets, fields and macros for CPU system |
| 476 | * instructions. |
| 477 | ******************************************************************************/ |
| 478 | |
| 479 | #define TLBI_ADDR_SHIFT U(12) |
| 480 | #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) |
| 481 | #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) |
| 482 | |
| 483 | /******************************************************************************* |
| 484 | * Definitions of register offsets and fields in the CNTBaseN Frame of the |
| 485 | * system level implementation of the Generic Timer. |
| 486 | ******************************************************************************/ |
| 487 | /* Physical Count register. */ |
| 488 | #define CNTPCT_LO 0x0 |
| 489 | /* Counter Frequency register. */ |
| 490 | #define CNTBASEN_CNTFRQ 0x10 |
| 491 | /* Physical Timer CompareValue register. */ |
| 492 | #define CNTP_CVAL_LO 0x20 |
| 493 | /* Physical Timer Control register. */ |
| 494 | #define CNTP_CTL 0x2c |
| 495 | |
| 496 | /******************************************************************************* |
| 497 | * Definitions of MAIR encodings for device and normal memory |
| 498 | ******************************************************************************/ |
| 499 | /* |
| 500 | * MAIR encodings for device memory attributes. |
| 501 | */ |
| 502 | #define MAIR_DEV_nGnRnE ULL(0x0) |
| 503 | #define MAIR_DEV_nGnRE ULL(0x4) |
| 504 | #define MAIR_DEV_nGRE ULL(0x8) |
| 505 | #define MAIR_DEV_GRE ULL(0xc) |
| 506 | |
| 507 | /* |
| 508 | * MAIR encodings for normal memory attributes. |
| 509 | * |
| 510 | * Cache Policy |
| 511 | * WT: Write Through |
| 512 | * WB: Write Back |
| 513 | * NC: Non-Cacheable |
| 514 | * |
| 515 | * Transient Hint |
| 516 | * NTR: Non-Transient |
| 517 | * TR: Transient |
| 518 | * |
| 519 | * Allocation Policy |
| 520 | * RA: Read Allocate |
| 521 | * WA: Write Allocate |
| 522 | * RWA: Read and Write Allocate |
| 523 | * NA: No Allocation |
| 524 | */ |
| 525 | #define MAIR_NORM_WT_TR_WA ULL(0x1) |
| 526 | #define MAIR_NORM_WT_TR_RA ULL(0x2) |
| 527 | #define MAIR_NORM_WT_TR_RWA ULL(0x3) |
| 528 | #define MAIR_NORM_NC ULL(0x4) |
| 529 | #define MAIR_NORM_WB_TR_WA ULL(0x5) |
| 530 | #define MAIR_NORM_WB_TR_RA ULL(0x6) |
| 531 | #define MAIR_NORM_WB_TR_RWA ULL(0x7) |
| 532 | #define MAIR_NORM_WT_NTR_NA ULL(0x8) |
| 533 | #define MAIR_NORM_WT_NTR_WA ULL(0x9) |
| 534 | #define MAIR_NORM_WT_NTR_RA ULL(0xa) |
| 535 | #define MAIR_NORM_WT_NTR_RWA ULL(0xb) |
| 536 | #define MAIR_NORM_WB_NTR_NA ULL(0xc) |
| 537 | #define MAIR_NORM_WB_NTR_WA ULL(0xd) |
| 538 | #define MAIR_NORM_WB_NTR_RA ULL(0xe) |
| 539 | #define MAIR_NORM_WB_NTR_RWA ULL(0xf) |
| 540 | |
| 541 | #define MAIR_NORM_OUTER_SHIFT U(4) |
| 542 | |
| 543 | #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) |
| 544 | |
| 545 | /* PAR_EL1 fields */ |
| 546 | #define PAR_F_SHIFT U(0) |
| 547 | #define PAR_F_MASK ULL(0x1) |
| 548 | #define PAR_ADDR_SHIFT U(12) |
| 549 | #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ |
| 550 | |
| 551 | /******************************************************************************* |
| 552 | * Definitions for system register interface to AMU for ARMv8.4 onwards |
| 553 | ******************************************************************************/ |
| 554 | #define AMCR_EL0 S3_3_C13_C2_0 |
| 555 | #define AMCFGR_EL0 S3_3_C13_C2_1 |
| 556 | #define AMCGCR_EL0 S3_3_C13_C2_2 |
| 557 | #define AMUSERENR_EL0 S3_3_C13_C2_3 |
| 558 | #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 |
| 559 | #define AMCNTENSET0_EL0 S3_3_C13_C2_5 |
| 560 | #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 |
| 561 | #define AMCNTENSET1_EL0 S3_3_C13_C3_1 |
| 562 | |
| 563 | /* Activity Monitor Group 0 Event Counter Registers */ |
| 564 | #define AMEVCNTR00_EL0 S3_3_C13_C4_0 |
| 565 | #define AMEVCNTR01_EL0 S3_3_C13_C4_1 |
| 566 | #define AMEVCNTR02_EL0 S3_3_C13_C4_2 |
| 567 | #define AMEVCNTR03_EL0 S3_3_C13_C4_3 |
| 568 | |
| 569 | /* Activity Monitor Group 0 Event Type Registers */ |
| 570 | #define AMEVTYPER00_EL0 S3_3_C13_C6_0 |
| 571 | #define AMEVTYPER01_EL0 S3_3_C13_C6_1 |
| 572 | #define AMEVTYPER02_EL0 S3_3_C13_C6_2 |
| 573 | #define AMEVTYPER03_EL0 S3_3_C13_C6_3 |
| 574 | |
| 575 | /* Activity Monitor Group 1 Event Counter Registers */ |
| 576 | #define AMEVCNTR10_EL0 S3_3_C13_C12_0 |
| 577 | #define AMEVCNTR11_EL0 S3_3_C13_C12_1 |
| 578 | #define AMEVCNTR12_EL0 S3_3_C13_C12_2 |
| 579 | #define AMEVCNTR13_EL0 S3_3_C13_C12_3 |
| 580 | #define AMEVCNTR14_EL0 S3_3_C13_C12_4 |
| 581 | #define AMEVCNTR15_EL0 S3_3_C13_C12_5 |
| 582 | #define AMEVCNTR16_EL0 S3_3_C13_C12_6 |
| 583 | #define AMEVCNTR17_EL0 S3_3_C13_C12_7 |
| 584 | #define AMEVCNTR18_EL0 S3_3_C13_C13_0 |
| 585 | #define AMEVCNTR19_EL0 S3_3_C13_C13_1 |
| 586 | #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 |
| 587 | #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 |
| 588 | #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 |
| 589 | #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 |
| 590 | #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 |
| 591 | #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 |
| 592 | |
| 593 | /* Activity Monitor Group 1 Event Type Registers */ |
| 594 | #define AMEVTYPER10_EL0 S3_3_C13_C14_0 |
| 595 | #define AMEVTYPER11_EL0 S3_3_C13_C14_1 |
| 596 | #define AMEVTYPER12_EL0 S3_3_C13_C14_2 |
| 597 | #define AMEVTYPER13_EL0 S3_3_C13_C14_3 |
| 598 | #define AMEVTYPER14_EL0 S3_3_C13_C14_4 |
| 599 | #define AMEVTYPER15_EL0 S3_3_C13_C14_5 |
| 600 | #define AMEVTYPER16_EL0 S3_3_C13_C14_6 |
| 601 | #define AMEVTYPER17_EL0 S3_3_C13_C14_7 |
| 602 | #define AMEVTYPER18_EL0 S3_3_C13_C15_0 |
| 603 | #define AMEVTYPER19_EL0 S3_3_C13_C15_1 |
| 604 | #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 |
| 605 | #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 |
| 606 | #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 |
| 607 | #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 |
| 608 | #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 |
| 609 | #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 |
| 610 | |
| 611 | /* AMCGCR_EL0 definitions */ |
| 612 | #define AMCGCR_EL0_CG1NC_SHIFT U(8) |
| 613 | #define AMCGCR_EL0_CG1NC_LENGTH U(8) |
| 614 | #define AMCGCR_EL0_CG1NC_MASK U(0xff) |
| 615 | |
| 616 | /******************************************************************************* |
| 617 | * RAS system registers |
| 618 | *******************************************************************************/ |
| 619 | #define DISR_EL1 S3_0_C12_C1_1 |
| 620 | #define DISR_A_BIT U(31) |
| 621 | |
| 622 | #define ERRIDR_EL1 S3_0_C5_C3_0 |
| 623 | #define ERRIDR_MASK U(0xffff) |
| 624 | |
| 625 | #define ERRSELR_EL1 S3_0_C5_C3_1 |
| 626 | |
| 627 | /* Fault injection registers */ |
| 628 | #define ERXPFGF_EL1 S3_0_C5_C4_4 |
| 629 | #define ERXCTLR_EL1 S3_0_C5_C4_1 |
| 630 | #define ERXPFGCTL_EL1 S3_0_C5_C4_5 |
| 631 | #define ERXPFGCDN_EL1 S3_0_C5_C4_6 |
| 632 | |
| 633 | #define ERXCTLR_ED_BIT (1 << 0) |
| 634 | #define ERXCTLR_UE_BIT (1 << 4) |
| 635 | |
| 636 | #define ERXPFGCTL_UC_BIT (1 << 1) |
| 637 | #define ERXPFGCTL_UEU_BIT (1 << 2) |
| 638 | #define ERXPFGCTL_CDEN_BIT (1 << 31) |
| 639 | |
| Jeenu Viswambharan | a1c3cca | 2018-10-16 10:09:32 +0100 | [diff] [blame^] | 640 | /******************************************************************************* |
| 641 | * Armv8.3 Pointer Authentication Registers |
| 642 | *******************************************************************************/ |
| 643 | #define APGAKeyLo_EL1 S3_0_C2_C3_0 |
| 644 | |
| Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame] | 645 | #endif /* __ARCH_H__ */ |