blob: 3ce69869b0a824e384ac2456c37fe635a1e98acd [file] [log] [blame]
AlexeiFedorov9f0dc012024-09-10 10:22:06 +01001/*
2 * Copyright (c) 2024, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef PCIE_H
8#define PCIE_H
9
10#include <cdefs.h>
11#include <stdint.h>
12#include <utils_def.h>
13
Soby Mathew2c2810f2024-11-15 17:11:24 +000014/* platforms need to ensure that number of entries is less that this value */
15#define MAX_PCIE_INFO_ENTRIES 5
16
AlexeiFedorov9f0dc012024-09-10 10:22:06 +010017typedef struct {
18 unsigned long ecam_base; /* ECAM base address */
19 unsigned int segment_num; /* Segment number of this ECAM */
20 unsigned int start_bus_num; /* Start bus number for this ECAM space */
21 unsigned int end_bus_num; /* Last bus number */
22} pcie_info_block_t;
23
Soby Mathew2c2810f2024-11-15 17:11:24 +000024struct pcie_info_table{
AlexeiFedorov9f0dc012024-09-10 10:22:06 +010025 unsigned int num_entries; /* Number of entries */
Soby Mathew2c2810f2024-11-15 17:11:24 +000026 pcie_info_block_t block[MAX_PCIE_INFO_ENTRIES];
27};
AlexeiFedorov9f0dc012024-09-10 10:22:06 +010028
29typedef struct {
30 uint32_t bdf;
31 uint32_t rp_bdf;
32} pcie_device_attr_t;
33
34typedef struct __packed {
35 uint32_t num_entries;
36 pcie_device_attr_t device[]; /* in the format of Segment/Bus/Dev/Func */
37} pcie_device_bdf_table_t;
38
39/* Address initialisation structure */
40typedef struct {
41 /* 64 bit prefetchable memory start address */
42 uint64_t bar64_p_start;
43 uint64_t rp_bar64_value;
44 /* 32 bit non-prefetchable memory start address */
45 uint32_t bar32_np_start;
46 /* 32 bit prefetchable memory start address */
47 uint32_t bar32_p_start;
48 uint32_t rp_bar32_value;
49} pcie_bar_init_t;
50
51#define PCIE_EXTRACT_BDF_SEG(bdf) ((bdf >> 24) & 0xFF)
52#define PCIE_EXTRACT_BDF_BUS(bdf) ((bdf >> 16) & 0xFF)
53#define PCIE_EXTRACT_BDF_DEV(bdf) ((bdf >> 8) & 0xFF)
54#define PCIE_EXTRACT_BDF_FUNC(bdf) (bdf & 0xFF)
55
56/* PCI-compatible region */
57#define PCI_CMP_CFG_SIZE 256
58
59/* PCI Express Extended Configuration Space */
60#define PCIE_CFG_SIZE 4096
61
62#define PCIE_MAX_BUS 256
63#define PCIE_MAX_DEV 32
64#define PCIE_MAX_FUNC 8
65
66#define PCIE_CREATE_BDF(Seg, Bus, Dev, Func) \
67 ((Seg << 24) | (Bus << 16) | (Dev << 8) | Func)
68
69#define PCIE_SUCCESS 0x00000000 /* Operation completed successfully */
70#define PCIE_NO_MAPPING 0x10000001 /* A mapping to a Function does not exist */
71#define PCIE_CAP_NOT_FOUND 0x10000010 /* The specified capability was not found */
72#define PCIE_UNKNOWN_RESPONSE 0xFFFFFFFF /* Function not found or UR response from completer */
73
74/* Allows storage of 2048 valid BDFs */
75#define PCIE_DEVICE_BDF_TABLE_SZ 8192
76
77typedef enum {
78 HEADER = 0,
79 PCIE_CAP = 1,
80 PCIE_ECAP = 2
81} bitfield_reg_type_t;
82
83typedef enum {
84 HW_INIT = 0,
85 READ_ONLY = 1,
86 STICKY_RO = 2,
87 RSVDP_RO = 3,
88 RSVDZ_RO = 4,
89 READ_WRITE = 5,
90 STICKY_RW = 6
91} bitfield_attr_type_t;
92
93/* Class Code Masks */
94#define CC_SUB_MASK 0xFF /* Sub Class */
95#define CC_BASE_MASK 0xFF /* Base Class */
96
97/* Class Code Shifts */
98#define CC_SHIFT 8
99#define CC_SUB_SHIFT 16
100#define CC_BASE_SHIFT 24
101
102void pcie_create_info_table(void);
103pcie_device_bdf_table_t *pcie_get_bdf_table(void);
104uint32_t pcie_find_capability(uint32_t bdf, uint32_t cid_type, uint32_t cid,
105 uint32_t *cid_offset);
106uint32_t pcie_read_cfg(uint32_t bdf, uint32_t offset);
107void pcie_write_cfg(uint32_t bdf, uint32_t offset, uint32_t data);
108
109#endif /* PCIE_H */