blob: 0e56bdcc63006949e0d561ae94b2133991fc02d7 [file] [log] [blame]
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +02001/*
Deepika Bhavnanic249d5e2020-02-06 16:29:45 -06002 * Copyright (c) 2018-2020, Arm Limited. All rights reserved.
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/*
8 * Definitions related to the Power State Coordination Interface (PSCI)
9 * as per the SMC Calling Convention.
10 *
11 * PSCI calls are a subset of the Standard Service Calls.
12 */
13
14#ifndef __PSCI_H__
15#define __PSCI_H__
16
17#ifndef __ASSEMBLY__
18#include <assert.h>
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +020019#include <stdbool.h>
20#include <stdint.h>
21#endif
22
23/*******************************************************************************
24 * Macro to create the array entry for psci_functions[]
25 ******************************************************************************/
26#define DEFINE_PSCI_FUNC(_func_id, _mandatory) \
27 { SMC_##_func_id, _mandatory, "SMC_" # _func_id }
28
29/*******************************************************************************
30 * Defines for runtime services function ids
31 ******************************************************************************/
32#define SMC_PSCI_VERSION 0x84000000
33#define SMC_PSCI_CPU_SUSPEND_AARCH32 0x84000001
34#define SMC_PSCI_CPU_SUSPEND_AARCH64 0xc4000001
35#define SMC_PSCI_CPU_OFF 0x84000002
36#define SMC_PSCI_CPU_ON_AARCH32 0x84000003
37#define SMC_PSCI_CPU_ON_AARCH64 0xc4000003
38#define SMC_PSCI_AFFINITY_INFO_AARCH32 0x84000004
39#define SMC_PSCI_AFFINITY_INFO_AARCH64 0xc4000004
40#define SMC_PSCI_MIG_AARCH32 0x84000005
41#define SMC_PSCI_MIG_AARCH64 0xc4000005
42#define SMC_PSCI_MIG_INFO_TYPE 0x84000006
43#define SMC_PSCI_MIG_INFO_UP_CPU_AARCH32 0x84000007
44#define SMC_PSCI_MIG_INFO_UP_CPU_AARCH64 0xc4000007
45#define SMC_PSCI_SYSTEM_OFF 0x84000008
46#define SMC_PSCI_SYSTEM_RESET 0x84000009
47#define SMC_PSCI_FEATURES 0x8400000a
48#define SMC_PSCI_CPU_FREEZE 0x8400000b
49#define SMC_PSCI_CPU_DEFAULT_SUSPEND32 0x8400000c
50#define SMC_PSCI_CPU_DEFAULT_SUSPEND64 0xc400000c
51#define SMC_PSCI_CPU_HW_STATE32 0x8400000d
52#define SMC_PSCI_CPU_HW_STATE64 0xc400000d
53#define SMC_PSCI_SYSTEM_SUSPEND32 0x8400000e
54#define SMC_PSCI_SYSTEM_SUSPEND64 0xc400000e
55#define SMC_PSCI_SET_SUSPEND_MODE 0x8400000f
56#define SMC_PSCI_STAT_RESIDENCY32 0x84000010
57#define SMC_PSCI_STAT_RESIDENCY64 0xc4000010
58#define SMC_PSCI_STAT_COUNT32 0x84000011
59#define SMC_PSCI_STAT_COUNT64 0xc4000011
60#define SMC_PSCI_RESET2_AARCH32 0x84000012
61#define SMC_PSCI_RESET2_AARCH64 0xc4000012
62#define SMC_PSCI_MEM_PROTECT 0x84000013
63#define SMC_PSCI_MEM_PROTECT_CHECK_RANGE32 0x84000014
64#define SMC_PSCI_MEM_PROTECT_CHECK_RANGE64 0xc4000014
65
66/*
67 * Architecture-specific SMC function IDs
68 */
Deepika Bhavnanic249d5e2020-02-06 16:29:45 -060069#ifdef __aarch64__
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +020070#define SMC_PSCI_CPU_SUSPEND SMC_PSCI_CPU_SUSPEND_AARCH64
71#define SMC_PSCI_CPU_ON SMC_PSCI_CPU_ON_AARCH64
72#define SMC_PSCI_AFFINITY_INFO SMC_PSCI_AFFINITY_INFO_AARCH64
73#define SMC_PSCI_MIG SMC_PSCI_MIG_AARCH64
74#define SMC_PSCI_MIG_INFO_UP_CPU SMC_PSCI_MIG_INFO_UP_CPU_AARCH64
75#define SMC_PSCI_CPU_DEFAULT_SUSPEND SMC_PSCI_CPU_DEFAULT_SUSPEND64
76#define SMC_PSCI_CPU_HW_STATE SMC_PSCI_CPU_HW_STATE64
77#define SMC_PSCI_SYSTEM_SUSPEND SMC_PSCI_SYSTEM_SUSPEND64
78#define SMC_PSCI_STAT_RESIDENCY SMC_PSCI_STAT_RESIDENCY64
79#define SMC_PSCI_STAT_COUNT SMC_PSCI_STAT_COUNT64
80#define SMC_PSCI_RESET2 SMC_PSCI_RESET2_AARCH64
81#define SMC_PSCI_MEM_PROTECT_CHECK SMC_PSCI_MEM_PROTECT_CHECK_RANGE64
82#else
83#define SMC_PSCI_CPU_SUSPEND SMC_PSCI_CPU_SUSPEND_AARCH32
84#define SMC_PSCI_CPU_ON SMC_PSCI_CPU_ON_AARCH32
85#define SMC_PSCI_AFFINITY_INFO SMC_PSCI_AFFINITY_INFO_AARCH32
86#define SMC_PSCI_MIG SMC_PSCI_MIG_AARCH32
87#define SMC_PSCI_MIG_INFO_UP_CPU SMC_PSCI_MIG_INFO_UP_CPU_AARCH32
88#define SMC_PSCI_CPU_DEFAULT_SUSPEND SMC_PSCI_CPU_DEFAULT_SUSPEND32
89#define SMC_PSCI_CPU_HW_STATE SMC_PSCI_CPU_HW_STATE32
90#define SMC_PSCI_SYSTEM_SUSPEND SMC_PSCI_SYSTEM_SUSPEND32
91#define SMC_PSCI_STAT_RESIDENCY SMC_PSCI_STAT_RESIDENCY32
92#define SMC_PSCI_STAT_COUNT SMC_PSCI_STAT_COUNT32
93#define SMC_PSCI_RESET2 SMC_PSCI_RESET2_AARCH32
94#define SMC_PSCI_MEM_PROTECT_CHECK SMC_PSCI_MEM_PROTECT_CHECK_RANGE32
95#endif
96
97/*
98 * Number of PSCI calls defined in the PSCI specification.
99 */
100#define PSCI_NUM_CALLS 33
101
102#ifndef __ASSEMBLY__
103typedef struct {
104 uint32_t id;
105 bool mandatory;
106 const char *str;
107} psci_function_t;
108
109extern const psci_function_t psci_functions[PSCI_NUM_CALLS];
110#endif /* __ASSEMBLY__ */
111
112/*******************************************************************************
113 * PSCI Migrate specific defines
114 ******************************************************************************/
115#define PSCI_TOS_UP_MIG_CAP 0
116#define PSCI_TOS_NOT_UP_MIG_CAP 1
117#define PSCI_TOS_NOT_PRESENT_MP 2
118
119/*******************************************************************************
120 * PSCI CPU_SUSPEND 'power_state' parameter specific defines
121 ******************************************************************************/
122/* Original format */
123#define PSTATE_ID_SHIFT 0
124#define PSTATE_TYPE_SHIFT 16
125#define PSTATE_AFF_LVL_SHIFT 24
126#define PSTATE_ID_MASK 0xFFFF
127#define PSTATE_AFF_LVL_MASK 0x3
128
129#define psci_state_id_valid(state_id) \
130 (((state_id) & ~PSTATE_ID_MASK) == 0)
131
132#define psci_affinity_level_valid(aff_level) \
133 (((aff_level) & ~PSTATE_AFF_LVL_MASK) == 0)
134
135/* Extended format */
136#define PSTATE_ID_SHIFT_EXT 0
137#define PSTATE_TYPE_SHIFT_EXT 30
138#define PSTATE_ID_MASK_EXT 0xFFFFFFF
139
140#define psci_state_id_ext_valid(state_id) \
141 (((state_id) & ~PSTATE_ID_MASK_EXT) == 0)
142
143/* Definitions common to original and extended StateID formats */
144#define PSTATE_TYPE_MASK 0x1
145
146#define PSTATE_TYPE_STANDBY 0x0
147#define PSTATE_TYPE_POWERDOWN 0x1
148
149#define PSTATE_AFF_LVL_0 0
150#define PSTATE_AFF_LVL_1 1
151#define PSTATE_AFF_LVL_2 2
152#define PSTATE_AFF_LVL_3 3
153
154#define psci_state_type_valid(state_type) \
155 (((state_type) & ~PSTATE_TYPE_MASK) == 0)
156
157/*******************************************************************************
158 * PSCI 'Feature Flags' defines for CPU_SUSPEND
159 ******************************************************************************/
160#define CPU_SUSPEND_FEAT_OS_INIT_MODE_SHIFT 0
161#define CPU_SUSPEND_FEAT_PSTATE_FORMAT_SHIFT 1
162#define CPU_SUSPEND_FEAT_PSTATE_FORMAT_ORIGINAL 0
163#define CPU_SUSPEND_FEAT_PSTATE_FORMAT_EXTENDED 1
164
165#define CPU_SUSPEND_FEAT_VALID_MASK \
166 ((1 << CPU_SUSPEND_FEAT_OS_INIT_MODE_SHIFT) | \
167 (1 << CPU_SUSPEND_FEAT_PSTATE_FORMAT_SHIFT))
168
169/*******************************************************************************
170 * PSCI 'Feature Flags' defines for functions other than CPU_SUSPEND
171 ******************************************************************************/
172#define PSCI_FEATURE_FLAGS_ZERO 0
173
174#ifndef __ASSEMBLY__
175
176/*
177 * Construct the local State-ID for a particular level according to
178 * the platform specific local state-ID width.
179 */
180#define psci_make_local_state_id(level, local_state) \
181 (((local_state) & ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1)) \
182 << (PLAT_LOCAL_PSTATE_WIDTH * (level)))
183#endif
184
185/*******************************************************************************
186 * PSCI version
187 ******************************************************************************/
188#define PSCI_MAJOR_VER 1
189#define PSCI_MINOR_VER 1
190#define PSCI_MAJOR_VER_SHIFT 16
191#define PSCI_MAJOR_VER_MASK 0xFFFF0000
192#define PSCI_VERSION(major, minor) ((major << PSCI_MAJOR_VER_SHIFT) \
193 | minor)
194
195/*******************************************************************************
196 * PSCI error codes
197 ******************************************************************************/
198#define PSCI_E_SUCCESS 0
199#define PSCI_E_NOT_SUPPORTED -1
200#define PSCI_E_INVALID_PARAMS -2
201#define PSCI_E_DENIED -3
202#define PSCI_E_ALREADY_ON -4
203#define PSCI_E_ON_PENDING -5
204#define PSCI_E_INTERN_FAIL -6
205#define PSCI_E_NOT_PRESENT -7
206#define PSCI_E_DISABLED -8
207#define PSCI_E_INVALID_ADDRESS -9
208
209/*******************************************************************************
Wing Licb88add2022-10-29 02:32:06 +0100210 * PSCI suspend mode related constants.
211 ******************************************************************************/
212#define PSCI_PLAT_COORD 0x0
213#define PSCI_OS_INIT 0x1
214
215/*******************************************************************************
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200216 * PSCI affinity state related constants.
217 ******************************************************************************/
218#define PSCI_STATE_ON 0x0
219#define PSCI_STATE_OFF 0x1
220#define PSCI_STATE_ON_PENDING 0x2
221
222/*******************************************************************************
223 * PSCI node hardware state related constants.
224 ******************************************************************************/
225#define PSCI_HW_STATE_ON 0x0
226#define PSCI_HW_STATE_OFF 0x1
227#define PSCI_HW_STATE_STANDBY 0x2
228
229#endif /* __PSCI_H__ */